Lines Matching refs:v4i32
144 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
191 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
200 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
209 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
214 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
323 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
326 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
329 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
332 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
335 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
413 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
667 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
668 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
669 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
1443 return MVT::v4i32;
2901 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
4476 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
5837 VData = DAG.getBitcast(MVT::v4i32, VData);
11054 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
11088 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);