Lines Matching refs:v4i32
624 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
677 // We promote all non-typed operations to v4i32.
679 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
681 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
683 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
685 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
687 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
690 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
692 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
740 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
748 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
763 setOperationAction(ISD::AND , MVT::v4i32, Legal);
764 setOperationAction(ISD::OR , MVT::v4i32, Legal);
765 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
766 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
767 setOperationAction(ISD::SELECT, MVT::v4i32,
769 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
770 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
771 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
772 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
773 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
788 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
795 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
808 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
820 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
892 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1065 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1076 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
3205 DAG.getSetCC(dl, MVT::v4i32,
3206 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
3207 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
3523 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3603 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3733 case MVT::v4i32:
4213 case MVT::v4i32:
4410 case MVT::v4i32:
4445 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4590 case MVT::v4i32:
6115 case MVT::v4i32:
6494 case MVT::v4i32:
6708 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
6933 case MVT::v4i32:
7002 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
8529 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64;
8983 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
9062 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32));
9246 // Now load from v4i32 into the QPX register; this will extend it to
9257 dl, VTs, Ops, MVT::v4i32, PtrInfo);
9340 // Canonicalize all zero vectors to be v4i32.
9341 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
9342 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32);
9388 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
9402 SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl);
9409 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
9956 DAG.getVTList(IsFourByte ? MVT::v4i32 : MVT::v2i64, MVT::Other);
9970 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
9971 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2);
9973 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2,
9975 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl,
9979 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2,
10003 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10005 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2);
10007 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2,
10031 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10032 SDValue ReveWord = DAG.getNode(ISD::BSWAP, dl, MVT::v4i32, Conv);
10049 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10050 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
10729 dl, VTs, Ops, MVT::v4i32, PtrInfo);
10927 dl, VTs, Ops, MVT::v4i32, PtrInfo);
10961 if (Op.getValueType() == MVT::v4i32) {
10964 SDValue Zero = getCanonicalConstSplat(0, 1, MVT::v4i32, DAG, dl);
10966 SDValue Neg16 = getCanonicalConstSplat(-16, 4, MVT::v4i32, DAG, dl);
10978 LHS, RHS, DAG, dl, MVT::v4i32);
10981 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
10985 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
11030 assert((VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
13021 VT = MVT::v4i32;
13066 VT = MVT::v4i32;
13072 VT = MVT::v4i32;
14222 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 ||
14935 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
14950 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
15068 (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
15110 PermTy = MVT::v4i32;
15111 LDTy = MVT::v4i32;
15268 if ((V1.getSimpleValueType() == MVT::v4i32 ||
16119 VT = MVT::v4i32;
16153 VT = MVT::v4i32;
16205 VT = MVT::v4i32;
16238 VT = MVT::v4i32;
16276 return MVT::v4i32;
16373 VT != MVT::v4f32 && VT != MVT::v4i32)
16845 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
17074 // Transform (abs (sub a, b) to (vabsd a b 1)) if a & b of type v4i32
17080 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
17100 // For type v4i32, it can be optimized with xvnegsp + vabsduw
17101 if (N->getOperand(0).getValueType() == MVT::v4i32 &&
17113 // For type v4i32/v8ii16/v16i8, transform
17135 // ABSD only available for type v4i32/v8i16/v16i8
17136 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)