Lines Matching refs:v4i32
204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
228 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
449 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
450 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence
453 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
454 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
465 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
467 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
513 { ISD::SHL, MVT::v4i32, 1 }, // pslld
517 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
521 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
575 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org)
594 { ISD::SHL, MVT::v4i32, 1 },
595 { ISD::SRL, MVT::v4i32, 1 },
596 { ISD::SRA, MVT::v4i32, 1 },
642 { ISD::SHL, MVT::v4i32, 1 },
643 { ISD::SRL, MVT::v4i32, 2 },
644 { ISD::SRA, MVT::v4i32, 2 },
711 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
836 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
843 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend.
850 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
853 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org)
865 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
871 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
877 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
883 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle
946 // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
1143 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd
1157 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d
1284 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
1318 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
1324 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
1331 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
1337 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
1345 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
1461 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd
1472 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd
1502 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd
1503 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld
1630 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd
1634 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd
1660 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd
1661 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld
1677 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1678 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1694 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1696 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 },
1717 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1718 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1722 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1753 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1754 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1767 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1782 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1783 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1796 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
1797 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
1824 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1835 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1836 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1840 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1841 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1850 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1851 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1865 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1866 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
1891 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
1892 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 },
1901 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1902 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
1929 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1930 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1941 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1942 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1949 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
1950 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
1966 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
1967 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
2181 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb
2190 { ISD::SETCC, MVT::v4i32, 1 },
2196 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por
2268 { ISD::CTLZ, MVT::v4i32, 1 },
2346 { ISD::BITREVERSE, MVT::v4i32, 1 },
2447 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd
2448 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd
2454 { ISD::BITREVERSE, MVT::v4i32, 5 },
2458 { ISD::BSWAP, MVT::v4i32, 1 },
2461 { ISD::CTLZ, MVT::v4i32, 18 },
2465 { ISD::CTPOP, MVT::v4i32, 11 },
2469 { ISD::CTTZ, MVT::v4i32, 14 },
2475 { ISD::BITREVERSE, MVT::v4i32, 27 },
2479 { ISD::BSWAP, MVT::v4i32, 7 },
2482 { ISD::CTLZ, MVT::v4i32, 26 },
2486 { ISD::CTPOP, MVT::v4i32, 15 },
2490 { ISD::CTTZ, MVT::v4i32, 18 },
2729 { ISD::ROTL, MVT::v4i32, 1 },
2735 { ISD::ROTR, MVT::v4i32, 1 }
2744 { ISD::ROTL, MVT::v4i32, 1 },
2752 { ISD::ROTR, MVT::v4i32, 2 },
3139 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
3140 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
3248 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
3252 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
3332 // Reducing from 64 bits is a shuffle of v4f32/v4i32.
3386 {ISD::SMIN, MVT::v4i32, 1},
3387 {ISD::UMIN, MVT::v4i32, 1},
3633 // Reducing from 64 bits is a shuffle of v4f32/v4i32.