Lines Matching refs:v4i32
232 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
256 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
400 // It is legal to extload from v4i8 to v4i16 or v4i32.
402 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
403 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
413 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
414 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
796 addQRTypeForNEON(MVT::v4i32);
886 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
913 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
930 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
940 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
957 // It is legal to extload from v4i8 to v4i16 or v4i32.
1580 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1799 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
5628 NewTy = MVT::v4i32;
5701 DestVecType = MVT::v4i32;
6027 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6201 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
6666 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
6990 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
7067 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
7138 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
8073 return MVT::v4i32;
8114 // appropriate for the shuffle, i.e. v4i32 for a real v4i1 predicate.
8211 SDValue BitCast = DAG.getBitcast(MVT::v4i32, Input);
8222 // v4i32 and extract_vector_elts
8231 SDValue BitCast = DAG.getBitcast(MVT::v4i32, NewShuffle);
8240 SDValue NewVec = DAG.getBuildVector(MVT::v4i32, dl, Parts);
8573 // the promoted vector is v4i32. The result of concatentation gives a v8i1,
8666 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
8670 if (BVN->getValueType(0) != MVT::v4i32 ||
8823 // have been legalized as a BITCAST from v4i32.
8827 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
8955 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
8956 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
8969 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
8970 Y = DAG.getConstant(0xb000, dl, MVT::v4i32);
8971 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
8974 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
8987 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
8988 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
9007 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
9008 N1 = DAG.getConstant(0x89, dl, MVT::v4i32);
9009 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
9013 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
9095 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
9096 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
9120 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
9121 N1 = DAG.getConstant(2, dl, MVT::v4i32);
9122 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
9126 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
12566 Mask.getValueType() != MVT::v4i32)
12579 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);
12580 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1);
12586 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);
12587 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1);
13155 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
14499 Extract = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v4i32, FPTrunc);
14618 // these intructions only support v2i32/v4i32 types.
14633 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
14676 // these intructions only support v2i32/v4i32 types.
14691 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
14757 if (SDValue A = IsVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32}))
14759 if (SDValue A = IsVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}))
14767 if (IsVMLAV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B))
14769 if (IsVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B))
15315 if (VT != MVT::v4i32 && VT != MVT::v8i16)
15326 if (VT == MVT::v4i32)
15344 if (VT == MVT::v4i32) {
15369 if (VT == MVT::v4i32)
15385 if (VT == MVT::v4i32) {
15893 // Convert v4f32 bitcast (v4i32 vdup (i32)) -> v4f32 vdup (i32) under MVE.
16166 Ty == MVT::v4i32 || Ty == MVT::v4f32 || Ty == MVT::v2i64 ||
16871 (CanChangeType || VT == MVT::v4i32 || VT == MVT::v4f32) &&