/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.cpp | 1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 14 #include "RISCV.h" 30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); 32 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive"); 33 static_assert(RISCV [all...] |
H A D | RISCVInstrInfo.cpp | 1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 14 #include "RISCV.h" 36 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), 44 case RISCV::LB: 45 case RISCV::LBU: 46 case RISCV::LH: 47 case RISCV::LHU: 48 case RISCV [all...] |
H A D | RISCVMergeBaseOffset.cpp | 26 #include "RISCV.h" 36 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset" 82 if (HiLUI.getOpcode() != RISCV::LUI || 90 if (LoADDI->getOpcode() != RISCV::ADDI || 137 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); 147 if (OffsetTail.getOpcode() == RISCV::ADDI) { 157 if (OffsetLui.getOpcode() != RISCV::LUI || 168 } else if (OffsetTail.getOpcode() == RISCV::LUI) { 190 case RISCV::ADDI: { 197 case RISCV [all...] |
H A D | RISCVExpandAtomicPseudoInsts.cpp | 16 #include "RISCV.h" 27 "RISCV atomic pseudo instruction expansion pass" 93 case RISCV::PseudoAtomicLoadNand32: 96 case RISCV::PseudoAtomicLoadNand64: 99 case RISCV::PseudoMaskedAtomicSwap32: 102 case RISCV::PseudoMaskedAtomicLoadAdd32: 104 case RISCV::PseudoMaskedAtomicLoadSub32: 106 case RISCV::PseudoMaskedAtomicLoadNand32: 109 case RISCV::PseudoMaskedAtomicLoadMax32: 112 case RISCV [all...] |
H A D | RISCVISelLowering.cpp | 1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 15 #include "RISCV.h" 84 addRegisterClass(XLenVT, &RISCV::GPRRegClass); 87 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); 89 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); 94 setStackPointerRegisterToSaveRestore(RISCV::X2); 411 return RISCV::BEQ; 413 return RISCV::BNE; 415 return RISCV [all...] |
H A D | RISCVFrameLowering.cpp | 1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===// 9 // This file contains the RISCV implementation of TargetFrameLowering class. 37 Register MaxReg = RISCV::NoRegister; 44 if (MaxReg == RISCV::NoRegister) 50 case /*s11*/ RISCV::X27: return 12; 51 case /*s10*/ RISCV::X26: return 11; 52 case /*s9*/ RISCV::X25: return 10; 53 case /*s8*/ RISCV::X24: return 9; 54 case /*s7*/ RISCV::X23: return 8; 55 case /*s6*/ RISCV [all...] |
H A D | RISCVExpandPseudoInsts.cpp | 15 #include "RISCV.h" 25 #define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass" 94 case RISCV::PseudoLLA: 96 case RISCV::PseudoLA: 98 case RISCV::PseudoLA_TLS_IE: 100 case RISCV::PseudoLA_TLS_GD: 126 BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg) 152 RISCV::ADDI); 164 SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV [all...] |
H A D | RISCVISelDAGToDAG.cpp | 1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===// 9 // This file defines an instruction selector for the RISCV target. 36 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); 39 if (Inst.Opc == RISCV::LUI) 40 Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); 93 auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, 95 auto *NodeAddi1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, 106 RISCV::X0, XLenVT); 121 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); 141 CurDAG->SelectNodeTo(Node, RISCV [all...] |
H A D | RISCVCallLowering.cpp | 28 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
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H A D | RISCVRegisterInfo.h | 1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===// 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 60 return &RISCV::GPRRegClass;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVELFObjectWriter.cpp | 1 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===// 65 case RISCV::fixup_riscv_pcrel_hi20: 67 case RISCV::fixup_riscv_pcrel_lo12_i: 69 case RISCV::fixup_riscv_pcrel_lo12_s: 71 case RISCV::fixup_riscv_got_hi20: 73 case RISCV::fixup_riscv_tls_got_hi20: 75 case RISCV::fixup_riscv_tls_gd_hi20: 77 case RISCV::fixup_riscv_jal: 79 case RISCV::fixup_riscv_branch: 81 case RISCV [all...] |
H A D | RISCVAsmBackend.cpp | 1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===// 31 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 71 static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds, 105 case RISCV::fixup_riscv_got_hi20: 106 case RISCV::fixup_riscv_tls_got_hi20: 107 case RISCV::fixup_riscv_tls_gd_hi20: 111 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; 131 case RISCV::fixup_riscv_rvc_branch: 135 case RISCV::fixup_riscv_rvc_jump: 149 case RISCV [all...] |
H A D | RISCVMCCodeEmitter.cpp | 1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 98 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed 110 if (MI.getOpcode() == RISCV::PseudoTAIL) { 112 Ra = RISCV::X6; 113 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 116 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 118 Ra = RISCV::X1; 119 } else if (MI.getOpcode() == RISCV::PseudoJump) { 130 TmpInst = MCInstBuilder(RISCV::AUIPC) 136 if (MI.getOpcode() == RISCV [all...] |
H A D | RISCVFixupKinds.h | 1 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===// 14 #undef RISCV macro 17 namespace RISCV { namespace in namespace:llvm 89 } // end namespace RISCV
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H A D | RISCVTargetStreamer.cpp | 1 //===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===// 9 // This file provides RISCV specific target streamer methods. 41 if (STI.hasFeature(RISCV::FeatureRV32E)) 47 if (STI.hasFeature(RISCV::Feature64Bit)) 49 if (STI.hasFeature(RISCV::FeatureRV32E)) 53 if (STI.hasFeature(RISCV::FeatureStdExtM)) 55 if (STI.hasFeature(RISCV::FeatureStdExtA)) 57 if (STI.hasFeature(RISCV::FeatureStdExtF)) 59 if (STI.hasFeature(RISCV::FeatureStdExtD)) 61 if (STI.hasFeature(RISCV [all...] |
H A D | RISCVMCTargetDesc.cpp | 1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// 9 /// This file provides RISCV-specific target descriptions. 50 InitRISCVMCRegisterInfo(X, RISCV::X1); 59 Register SP = MRI.getDwarfRegNum(RISCV::X2, true); 120 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { 125 if (Inst.getOpcode() == RISCV::JAL) {
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H A D | RISCVMCExpr.cpp | 1 //===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===// 10 // accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...). 16 #include "RISCV.h" 80 case RISCV::fixup_riscv_got_hi20: 81 case RISCV::fixup_riscv_tls_got_hi20: 82 case RISCV::fixup_riscv_tls_gd_hi20: 83 case RISCV::fixup_riscv_pcrel_hi20:
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H A D | RISCVInstPrinter.cpp | 1 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// 9 // This class prints an RISCV MCInst to a .s file. 170 if (MO.getReg() == RISCV::NoRegister) 187 return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName 188 : RISCV::ABIRegAltName);
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H A D | RISCVAsmBackend.h | 1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===// 49 return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax]; 97 return RISCV::NumTargetFixupKinds;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/ |
H A D | RISCVMatInt.cpp | 32 Res.push_back(Inst(RISCV::LUI, Hi20)); 35 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; 73 Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); 75 Res.push_back(Inst(RISCV::ADDI, Lo12));
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H A D | RISCVBaseInfo.cpp | 17 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; 68 Register getBPReg() { return RISCV::X9; } 75 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
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/freebsd-13-stable/contrib/llvm-project/clang/lib/Basic/Targets/ |
H A D | RISCV.cpp | 1 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===// 9 // This file implements RISCV TargetInfo objects. 13 #include "RISCV.h" 178 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), 184 llvm::RISCV::fillValidCPUArchList(Values, false); 188 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), 194 llvm::RISCV [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===// 69 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; 74 Register Reg = RISCV::X0 + RegNo; 85 Register Reg = RISCV::F0_F + RegNo; 96 Register Reg = RISCV::F8_F + RegNo; 107 Register Reg = RISCV::F0_D + RegNo; 118 Register Reg = RISCV::F8_D + RegNo; 149 Register Reg = RISCV::X8 + RegNo; 160 Register Reg = RISCV::V0 + RegNo; 167 Register Reg = RISCV [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 1 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===// 68 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } 69 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } 234 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { 239 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { 338 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; 347 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); 956 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); 957 return Reg - RISCV [all...] |
/freebsd-13-stable/contrib/llvm-project/lld/ELF/Arch/ |
H A D | RISCV.cpp | 1 //===- RISCV.cpp ----------------------------------------------------------===// 23 class RISCV final : public TargetInfo { 25 RISCV(); 74 RISCV::RISCV() { function in class:RISCV 111 uint32_t RISCV::calcEFlags() const { 136 void RISCV::writeGotHeader(uint8_t *buf) const { 143 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const { 150 void RISCV::writePltHeader(uint8_t *buf) const { 171 void RISCV [all...] |