1//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVMCExpr.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmLayout.h"
13#include "llvm/MC/MCAssembler.h"
14#include "llvm/MC/MCContext.h"
15#include "llvm/MC/MCDirectives.h"
16#include "llvm/MC/MCELFObjectWriter.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCObjectWriter.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/MC/MCValue.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/raw_ostream.h"
23
24using namespace llvm;
25
26Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
27  if (STI.getTargetTriple().isOSBinFormatELF()) {
28    unsigned Type;
29    Type = llvm::StringSwitch<unsigned>(Name)
30#define ELF_RELOC(X, Y) .Case(#X, Y)
31#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
32#undef ELF_RELOC
33               .Default(-1u);
34    if (Type != -1u)
35      return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
36  }
37  return None;
38}
39
40const MCFixupKindInfo &
41RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
42  const static MCFixupKindInfo Infos[] = {
43      // This table *must* be in the order that the fixup_* kinds are defined in
44      // RISCVFixupKinds.h.
45      //
46      // name                      offset bits  flags
47      {"fixup_riscv_hi20", 12, 20, 0},
48      {"fixup_riscv_lo12_i", 20, 12, 0},
49      {"fixup_riscv_lo12_s", 0, 32, 0},
50      {"fixup_riscv_pcrel_hi20", 12, 20,
51       MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
52      {"fixup_riscv_pcrel_lo12_i", 20, 12,
53       MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
54      {"fixup_riscv_pcrel_lo12_s", 0, 32,
55       MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
56      {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
57      {"fixup_riscv_tprel_hi20", 12, 20, 0},
58      {"fixup_riscv_tprel_lo12_i", 20, 12, 0},
59      {"fixup_riscv_tprel_lo12_s", 0, 32, 0},
60      {"fixup_riscv_tprel_add", 0, 0, 0},
61      {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
62      {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
63      {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
64      {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65      {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
66      {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
67      {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
68      {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
69      {"fixup_riscv_relax", 0, 0, 0},
70      {"fixup_riscv_align", 0, 0, 0}};
71  static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
72                "Not all fixup kinds added to Infos array");
73
74  // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
75  // do not require any extra processing.
76  if (Kind >= FirstLiteralRelocationKind)
77    return MCAsmBackend::getFixupKindInfo(FK_NONE);
78
79  if (Kind < FirstTargetFixupKind)
80    return MCAsmBackend::getFixupKindInfo(Kind);
81
82  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
83         "Invalid kind!");
84  return Infos[Kind - FirstTargetFixupKind];
85}
86
87// If linker relaxation is enabled, or the relax option had previously been
88// enabled, always emit relocations even if the fixup can be resolved. This is
89// necessary for correctness as offsets may change during relaxation.
90bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
91                                            const MCFixup &Fixup,
92                                            const MCValue &Target) {
93  if (Fixup.getKind() >= FirstLiteralRelocationKind)
94    return true;
95  switch (Fixup.getTargetKind()) {
96  default:
97    break;
98  case FK_Data_1:
99  case FK_Data_2:
100  case FK_Data_4:
101  case FK_Data_8:
102    if (Target.isAbsolute())
103      return false;
104    break;
105  case RISCV::fixup_riscv_got_hi20:
106  case RISCV::fixup_riscv_tls_got_hi20:
107  case RISCV::fixup_riscv_tls_gd_hi20:
108    return true;
109  }
110
111  return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
112}
113
114bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
115                                                   bool Resolved,
116                                                   uint64_t Value,
117                                                   const MCRelaxableFragment *DF,
118                                                   const MCAsmLayout &Layout,
119                                                   const bool WasForced) const {
120  // Return true if the symbol is actually unresolved.
121  // Resolved could be always false when shouldForceRelocation return true.
122  // We use !WasForced to indicate that the symbol is unresolved and not forced
123  // by shouldForceRelocation.
124  if (!Resolved && !WasForced)
125    return true;
126
127  int64_t Offset = int64_t(Value);
128  switch (Fixup.getTargetKind()) {
129  default:
130    return false;
131  case RISCV::fixup_riscv_rvc_branch:
132    // For compressed branch instructions the immediate must be
133    // in the range [-256, 254].
134    return Offset > 254 || Offset < -256;
135  case RISCV::fixup_riscv_rvc_jump:
136    // For compressed jump instructions the immediate must be
137    // in the range [-2048, 2046].
138    return Offset > 2046 || Offset < -2048;
139  }
140}
141
142void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
143                                       const MCSubtargetInfo &STI) const {
144  // TODO: replace this with call to auto generated uncompressinstr() function.
145  MCInst Res;
146  switch (Inst.getOpcode()) {
147  default:
148    llvm_unreachable("Opcode not expected!");
149  case RISCV::C_BEQZ:
150    // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
151    Res.setOpcode(RISCV::BEQ);
152    Res.addOperand(Inst.getOperand(0));
153    Res.addOperand(MCOperand::createReg(RISCV::X0));
154    Res.addOperand(Inst.getOperand(1));
155    break;
156  case RISCV::C_BNEZ:
157    // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
158    Res.setOpcode(RISCV::BNE);
159    Res.addOperand(Inst.getOperand(0));
160    Res.addOperand(MCOperand::createReg(RISCV::X0));
161    Res.addOperand(Inst.getOperand(1));
162    break;
163  case RISCV::C_J:
164    // c.j $imm -> jal X0, $imm.
165    Res.setOpcode(RISCV::JAL);
166    Res.addOperand(MCOperand::createReg(RISCV::X0));
167    Res.addOperand(Inst.getOperand(0));
168    break;
169  case RISCV::C_JAL:
170    // c.jal $imm -> jal X1, $imm.
171    Res.setOpcode(RISCV::JAL);
172    Res.addOperand(MCOperand::createReg(RISCV::X1));
173    Res.addOperand(Inst.getOperand(0));
174    break;
175  }
176  Inst = std::move(Res);
177}
178
179// Given a compressed control flow instruction this function returns
180// the expanded instruction.
181unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
182  switch (Op) {
183  default:
184    return Op;
185  case RISCV::C_BEQZ:
186    return RISCV::BEQ;
187  case RISCV::C_BNEZ:
188    return RISCV::BNE;
189  case RISCV::C_J:
190  case RISCV::C_JAL: // fall through.
191    return RISCV::JAL;
192  }
193}
194
195bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
196                                        const MCSubtargetInfo &STI) const {
197  return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
198}
199
200bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
201  bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
202  unsigned MinNopLen = HasStdExtC ? 2 : 4;
203
204  if ((Count % MinNopLen) != 0)
205    return false;
206
207  // The canonical nop on RISC-V is addi x0, x0, 0.
208  for (; Count >= 4; Count -= 4)
209    OS.write("\x13\0\0\0", 4);
210
211  // The canonical nop on RVC is c.nop.
212  if (Count && HasStdExtC)
213    OS.write("\x01\0", 2);
214
215  return true;
216}
217
218static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
219                                 MCContext &Ctx) {
220  switch (Fixup.getTargetKind()) {
221  default:
222    llvm_unreachable("Unknown fixup kind!");
223  case RISCV::fixup_riscv_got_hi20:
224  case RISCV::fixup_riscv_tls_got_hi20:
225  case RISCV::fixup_riscv_tls_gd_hi20:
226    llvm_unreachable("Relocation should be unconditionally forced\n");
227  case FK_Data_1:
228  case FK_Data_2:
229  case FK_Data_4:
230  case FK_Data_8:
231  case FK_Data_6b:
232    return Value;
233  case RISCV::fixup_riscv_lo12_i:
234  case RISCV::fixup_riscv_pcrel_lo12_i:
235  case RISCV::fixup_riscv_tprel_lo12_i:
236    return Value & 0xfff;
237  case RISCV::fixup_riscv_lo12_s:
238  case RISCV::fixup_riscv_pcrel_lo12_s:
239  case RISCV::fixup_riscv_tprel_lo12_s:
240    return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
241  case RISCV::fixup_riscv_hi20:
242  case RISCV::fixup_riscv_pcrel_hi20:
243  case RISCV::fixup_riscv_tprel_hi20:
244    // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
245    return ((Value + 0x800) >> 12) & 0xfffff;
246  case RISCV::fixup_riscv_jal: {
247    if (!isInt<21>(Value))
248      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
249    if (Value & 0x1)
250      Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
251    // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
252    unsigned Sbit = (Value >> 20) & 0x1;
253    unsigned Hi8 = (Value >> 12) & 0xff;
254    unsigned Mid1 = (Value >> 11) & 0x1;
255    unsigned Lo10 = (Value >> 1) & 0x3ff;
256    // Inst{31} = Sbit;
257    // Inst{30-21} = Lo10;
258    // Inst{20} = Mid1;
259    // Inst{19-12} = Hi8;
260    Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
261    return Value;
262  }
263  case RISCV::fixup_riscv_branch: {
264    if (!isInt<13>(Value))
265      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
266    if (Value & 0x1)
267      Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
268    // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
269    // Value.
270    unsigned Sbit = (Value >> 12) & 0x1;
271    unsigned Hi1 = (Value >> 11) & 0x1;
272    unsigned Mid6 = (Value >> 5) & 0x3f;
273    unsigned Lo4 = (Value >> 1) & 0xf;
274    // Inst{31} = Sbit;
275    // Inst{30-25} = Mid6;
276    // Inst{11-8} = Lo4;
277    // Inst{7} = Hi1;
278    Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
279    return Value;
280  }
281  case RISCV::fixup_riscv_call:
282  case RISCV::fixup_riscv_call_plt: {
283    // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
284    // we need to add 0x800ULL before extract upper bits to reflect the
285    // effect of the sign extension.
286    uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
287    uint64_t LowerImm = Value & 0xfffULL;
288    return UpperImm | ((LowerImm << 20) << 32);
289  }
290  case RISCV::fixup_riscv_rvc_jump: {
291    // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
292    unsigned Bit11  = (Value >> 11) & 0x1;
293    unsigned Bit4   = (Value >> 4) & 0x1;
294    unsigned Bit9_8 = (Value >> 8) & 0x3;
295    unsigned Bit10  = (Value >> 10) & 0x1;
296    unsigned Bit6   = (Value >> 6) & 0x1;
297    unsigned Bit7   = (Value >> 7) & 0x1;
298    unsigned Bit3_1 = (Value >> 1) & 0x7;
299    unsigned Bit5   = (Value >> 5) & 0x1;
300    Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
301            (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
302    return Value;
303  }
304  case RISCV::fixup_riscv_rvc_branch: {
305    // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
306    unsigned Bit8   = (Value >> 8) & 0x1;
307    unsigned Bit7_6 = (Value >> 6) & 0x3;
308    unsigned Bit5   = (Value >> 5) & 0x1;
309    unsigned Bit4_3 = (Value >> 3) & 0x3;
310    unsigned Bit2_1 = (Value >> 1) & 0x3;
311    Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
312            (Bit5 << 2);
313    return Value;
314  }
315
316  }
317}
318
319bool RISCVAsmBackend::evaluateTargetFixup(
320    const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
321    const MCFragment *DF, const MCValue &Target, uint64_t &Value,
322    bool &WasForced) {
323  const MCFixup *AUIPCFixup;
324  const MCFragment *AUIPCDF;
325  MCValue AUIPCTarget;
326  switch (Fixup.getTargetKind()) {
327  default:
328    llvm_unreachable("Unexpected fixup kind!");
329  case RISCV::fixup_riscv_pcrel_hi20:
330    AUIPCFixup = &Fixup;
331    AUIPCDF = DF;
332    AUIPCTarget = Target;
333    break;
334  case RISCV::fixup_riscv_pcrel_lo12_i:
335  case RISCV::fixup_riscv_pcrel_lo12_s: {
336    AUIPCFixup = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF);
337    if (!AUIPCFixup) {
338      Asm.getContext().reportError(Fixup.getLoc(),
339                                   "could not find corresponding %pcrel_hi");
340      return true;
341    }
342
343    // MCAssembler::evaluateFixup will emit an error for this case when it sees
344    // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
345    const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
346    if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup))
347      return true;
348    break;
349  }
350  }
351
352  if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
353    return false;
354
355  const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
356  const MCSymbol &SA = A->getSymbol();
357  if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
358    return false;
359
360  auto *Writer = Asm.getWriterPtr();
361  if (!Writer)
362    return false;
363
364  bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
365      Asm, SA, *AUIPCDF, false, true);
366  if (!IsResolved)
367    return false;
368
369  Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant();
370  Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset();
371
372  if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
373    WasForced = true;
374    return false;
375  }
376
377  return true;
378}
379
380void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
381                                 const MCValue &Target,
382                                 MutableArrayRef<char> Data, uint64_t Value,
383                                 bool IsResolved,
384                                 const MCSubtargetInfo *STI) const {
385  MCFixupKind Kind = Fixup.getKind();
386  if (Kind >= FirstLiteralRelocationKind)
387    return;
388  MCContext &Ctx = Asm.getContext();
389  MCFixupKindInfo Info = getFixupKindInfo(Kind);
390  if (!Value)
391    return; // Doesn't change encoding.
392  // Apply any target-specific value adjustments.
393  Value = adjustFixupValue(Fixup, Value, Ctx);
394
395  // Shift the value into position.
396  Value <<= Info.TargetOffset;
397
398  unsigned Offset = Fixup.getOffset();
399  unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
400
401  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
402
403  // For each byte of the fragment that the fixup touches, mask in the
404  // bits from the fixup value.
405  for (unsigned i = 0; i != NumBytes; ++i) {
406    Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
407  }
408}
409
410// Linker relaxation may change code size. We have to insert Nops
411// for .align directive when linker relaxation enabled. So then Linker
412// could satisfy alignment by removing Nops.
413// The function return the total Nops Size we need to insert.
414bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
415    const MCAlignFragment &AF, unsigned &Size) {
416  // Calculate Nops Size only when linker relaxation enabled.
417  if (!STI.getFeatureBits()[RISCV::FeatureRelax])
418    return false;
419
420  bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
421  unsigned MinNopLen = HasStdExtC ? 2 : 4;
422
423  if (AF.getAlignment() <= MinNopLen) {
424    return false;
425  } else {
426    Size = AF.getAlignment() - MinNopLen;
427    return true;
428  }
429}
430
431// We need to insert R_RISCV_ALIGN relocation type to indicate the
432// position of Nops and the total bytes of the Nops have been inserted
433// when linker relaxation enabled.
434// The function insert fixup_riscv_align fixup which eventually will
435// transfer to R_RISCV_ALIGN relocation type.
436bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
437                                                    const MCAsmLayout &Layout,
438                                                    MCAlignFragment &AF) {
439  // Insert the fixup only when linker relaxation enabled.
440  if (!STI.getFeatureBits()[RISCV::FeatureRelax])
441    return false;
442
443  // Calculate total Nops we need to insert. If there are none to insert
444  // then simply return.
445  unsigned Count;
446  if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
447    return false;
448
449  MCContext &Ctx = Asm.getContext();
450  const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
451  // Create fixup_riscv_align fixup.
452  MCFixup Fixup =
453      MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc());
454
455  uint64_t FixedValue = 0;
456  MCValue NopBytes = MCValue::get(Count);
457
458  Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
459                                   FixedValue);
460
461  return true;
462}
463
464std::unique_ptr<MCObjectTargetWriter>
465RISCVAsmBackend::createObjectTargetWriter() const {
466  return createRISCVELFObjectWriter(OSABI, Is64Bit);
467}
468
469MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
470                                          const MCSubtargetInfo &STI,
471                                          const MCRegisterInfo &MRI,
472                                          const MCTargetOptions &Options) {
473  const Triple &TT = STI.getTargetTriple();
474  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
475  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
476}
477