1//===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file implements the RISCVMCCodeEmitter class. 10// 11//===----------------------------------------------------------------------===// 12 13#include "MCTargetDesc/RISCVFixupKinds.h" 14#include "MCTargetDesc/RISCVMCExpr.h" 15#include "MCTargetDesc/RISCVMCTargetDesc.h" 16#include "Utils/RISCVBaseInfo.h" 17#include "llvm/ADT/Statistic.h" 18#include "llvm/CodeGen/Register.h" 19#include "llvm/MC/MCAsmInfo.h" 20#include "llvm/MC/MCCodeEmitter.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCExpr.h" 23#include "llvm/MC/MCInst.h" 24#include "llvm/MC/MCInstBuilder.h" 25#include "llvm/MC/MCInstrInfo.h" 26#include "llvm/MC/MCRegisterInfo.h" 27#include "llvm/MC/MCSymbol.h" 28#include "llvm/Support/Casting.h" 29#include "llvm/Support/EndianStream.h" 30#include "llvm/Support/raw_ostream.h" 31 32using namespace llvm; 33 34#define DEBUG_TYPE "mccodeemitter" 35 36STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 37STATISTIC(MCNumFixups, "Number of MC fixups created"); 38 39namespace { 40class RISCVMCCodeEmitter : public MCCodeEmitter { 41 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete; 42 void operator=(const RISCVMCCodeEmitter &) = delete; 43 MCContext &Ctx; 44 MCInstrInfo const &MCII; 45 46public: 47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) 48 : Ctx(ctx), MCII(MCII) {} 49 50 ~RISCVMCCodeEmitter() override {} 51 52 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const override; 55 56 void expandFunctionCall(const MCInst &MI, raw_ostream &OS, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 void expandAddTPRel(const MCInst &MI, raw_ostream &OS, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 /// TableGen'erated function for getting the binary encoding for an 65 /// instruction. 66 uint64_t getBinaryCodeForInstr(const MCInst &MI, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 70 /// Return binary encoding of operand. If the machine operand requires 71 /// relocation, record the relocation and return zero. 72 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 76 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 80 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87}; 88} // end anonymous namespace 89 90MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 91 const MCRegisterInfo &MRI, 92 MCContext &Ctx) { 93 return new RISCVMCCodeEmitter(Ctx, MCII); 94} 95 96// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with 97// relocation types. We expand those pseudo-instructions while encoding them, 98// meaning AUIPC and JALR won't go through RISCV MC to MC compressed 99// instruction transformation. This is acceptable because AUIPC has no 16-bit 100// form and C_JALR has no immediate operand field. We let linker relaxation 101// deal with it. When linker relaxation is enabled, AUIPC and JALR have a 102// chance to relax to JAL. 103// If the C extension is enabled, JAL has a chance relax to C_JAL. 104void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, 105 SmallVectorImpl<MCFixup> &Fixups, 106 const MCSubtargetInfo &STI) const { 107 MCInst TmpInst; 108 MCOperand Func; 109 Register Ra; 110 if (MI.getOpcode() == RISCV::PseudoTAIL) { 111 Func = MI.getOperand(0); 112 Ra = RISCV::X6; 113 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 114 Func = MI.getOperand(1); 115 Ra = MI.getOperand(0).getReg(); 116 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 117 Func = MI.getOperand(0); 118 Ra = RISCV::X1; 119 } else if (MI.getOpcode() == RISCV::PseudoJump) { 120 Func = MI.getOperand(1); 121 Ra = MI.getOperand(0).getReg(); 122 } 123 uint32_t Binary; 124 125 assert(Func.isExpr() && "Expected expression"); 126 127 const MCExpr *CallExpr = Func.getExpr(); 128 129 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type. 130 TmpInst = MCInstBuilder(RISCV::AUIPC) 131 .addReg(Ra) 132 .addOperand(MCOperand::createExpr(CallExpr)); 133 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 134 support::endian::write(OS, Binary, support::little); 135 136 if (MI.getOpcode() == RISCV::PseudoTAIL || 137 MI.getOpcode() == RISCV::PseudoJump) 138 // Emit JALR X0, Ra, 0 139 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 140 else 141 // Emit JALR Ra, Ra, 0 142 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 143 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 144 support::endian::write(OS, Binary, support::little); 145} 146 147// Expand PseudoAddTPRel to a simple ADD with the correct relocation. 148void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const { 151 MCOperand DestReg = MI.getOperand(0); 152 MCOperand SrcReg = MI.getOperand(1); 153 MCOperand TPReg = MI.getOperand(2); 154 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && 155 "Expected thread pointer as second input to TP-relative add"); 156 157 MCOperand SrcSymbol = MI.getOperand(3); 158 assert(SrcSymbol.isExpr() && 159 "Expected expression as third input to TP-relative add"); 160 161 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr()); 162 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && 163 "Expected tprel_add relocation on TP-relative symbol"); 164 165 // Emit the correct tprel_add relocation for the symbol. 166 Fixups.push_back(MCFixup::create( 167 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); 168 169 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. 170 if (STI.getFeatureBits()[RISCV::FeatureRelax]) { 171 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 172 Fixups.push_back(MCFixup::create( 173 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); 174 } 175 176 // Emit a normal ADD instruction with the given operands. 177 MCInst TmpInst = MCInstBuilder(RISCV::ADD) 178 .addOperand(DestReg) 179 .addOperand(SrcReg) 180 .addOperand(TPReg); 181 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 182 support::endian::write(OS, Binary, support::little); 183} 184 185void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 186 SmallVectorImpl<MCFixup> &Fixups, 187 const MCSubtargetInfo &STI) const { 188 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 189 // Get byte count of instruction. 190 unsigned Size = Desc.getSize(); 191 192 // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded 193 // instructions for each pseudo, and must be updated when adding new pseudos 194 // or changing existing ones. 195 if (MI.getOpcode() == RISCV::PseudoCALLReg || 196 MI.getOpcode() == RISCV::PseudoCALL || 197 MI.getOpcode() == RISCV::PseudoTAIL || 198 MI.getOpcode() == RISCV::PseudoJump) { 199 expandFunctionCall(MI, OS, Fixups, STI); 200 MCNumEmitted += 2; 201 return; 202 } 203 204 if (MI.getOpcode() == RISCV::PseudoAddTPRel) { 205 expandAddTPRel(MI, OS, Fixups, STI); 206 MCNumEmitted += 1; 207 return; 208 } 209 210 switch (Size) { 211 default: 212 llvm_unreachable("Unhandled encodeInstruction length!"); 213 case 2: { 214 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 215 support::endian::write<uint16_t>(OS, Bits, support::little); 216 break; 217 } 218 case 4: { 219 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 220 support::endian::write(OS, Bits, support::little); 221 break; 222 } 223 } 224 225 ++MCNumEmitted; // Keep track of the # of mi's emitted. 226} 227 228unsigned 229RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, 230 SmallVectorImpl<MCFixup> &Fixups, 231 const MCSubtargetInfo &STI) const { 232 233 if (MO.isReg()) 234 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 235 236 if (MO.isImm()) 237 return static_cast<unsigned>(MO.getImm()); 238 239 llvm_unreachable("Unhandled expression!"); 240 return 0; 241} 242 243unsigned 244RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const { 247 const MCOperand &MO = MI.getOperand(OpNo); 248 249 if (MO.isImm()) { 250 unsigned Res = MO.getImm(); 251 assert((Res & 1) == 0 && "LSB is non-zero"); 252 return Res >> 1; 253 } 254 255 return getImmOpValue(MI, OpNo, Fixups, STI); 256} 257 258unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, 259 SmallVectorImpl<MCFixup> &Fixups, 260 const MCSubtargetInfo &STI) const { 261 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; 262 const MCOperand &MO = MI.getOperand(OpNo); 263 264 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); 265 unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask; 266 267 // If the destination is an immediate, there is nothing to do. 268 if (MO.isImm()) 269 return MO.getImm(); 270 271 assert(MO.isExpr() && 272 "getImmOpValue expects only expressions or immediates"); 273 const MCExpr *Expr = MO.getExpr(); 274 MCExpr::ExprKind Kind = Expr->getKind(); 275 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; 276 bool RelaxCandidate = false; 277 if (Kind == MCExpr::Target) { 278 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr); 279 280 switch (RVExpr->getKind()) { 281 case RISCVMCExpr::VK_RISCV_None: 282 case RISCVMCExpr::VK_RISCV_Invalid: 283 case RISCVMCExpr::VK_RISCV_32_PCREL: 284 llvm_unreachable("Unhandled fixup kind!"); 285 case RISCVMCExpr::VK_RISCV_TPREL_ADD: 286 // tprel_add is only used to indicate that a relocation should be emitted 287 // for an add instruction used in TP-relative addressing. It should not be 288 // expanded as if representing an actual instruction operand and so to 289 // encounter it here is an error. 290 llvm_unreachable( 291 "VK_RISCV_TPREL_ADD should not represent an instruction operand"); 292 case RISCVMCExpr::VK_RISCV_LO: 293 if (MIFrm == RISCVII::InstFormatI) 294 FixupKind = RISCV::fixup_riscv_lo12_i; 295 else if (MIFrm == RISCVII::InstFormatS) 296 FixupKind = RISCV::fixup_riscv_lo12_s; 297 else 298 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); 299 RelaxCandidate = true; 300 break; 301 case RISCVMCExpr::VK_RISCV_HI: 302 FixupKind = RISCV::fixup_riscv_hi20; 303 RelaxCandidate = true; 304 break; 305 case RISCVMCExpr::VK_RISCV_PCREL_LO: 306 if (MIFrm == RISCVII::InstFormatI) 307 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; 308 else if (MIFrm == RISCVII::InstFormatS) 309 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; 310 else 311 llvm_unreachable( 312 "VK_RISCV_PCREL_LO used with unexpected instruction format"); 313 RelaxCandidate = true; 314 break; 315 case RISCVMCExpr::VK_RISCV_PCREL_HI: 316 FixupKind = RISCV::fixup_riscv_pcrel_hi20; 317 RelaxCandidate = true; 318 break; 319 case RISCVMCExpr::VK_RISCV_GOT_HI: 320 FixupKind = RISCV::fixup_riscv_got_hi20; 321 break; 322 case RISCVMCExpr::VK_RISCV_TPREL_LO: 323 if (MIFrm == RISCVII::InstFormatI) 324 FixupKind = RISCV::fixup_riscv_tprel_lo12_i; 325 else if (MIFrm == RISCVII::InstFormatS) 326 FixupKind = RISCV::fixup_riscv_tprel_lo12_s; 327 else 328 llvm_unreachable( 329 "VK_RISCV_TPREL_LO used with unexpected instruction format"); 330 RelaxCandidate = true; 331 break; 332 case RISCVMCExpr::VK_RISCV_TPREL_HI: 333 FixupKind = RISCV::fixup_riscv_tprel_hi20; 334 RelaxCandidate = true; 335 break; 336 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: 337 FixupKind = RISCV::fixup_riscv_tls_got_hi20; 338 break; 339 case RISCVMCExpr::VK_RISCV_TLS_GD_HI: 340 FixupKind = RISCV::fixup_riscv_tls_gd_hi20; 341 break; 342 case RISCVMCExpr::VK_RISCV_CALL: 343 FixupKind = RISCV::fixup_riscv_call; 344 RelaxCandidate = true; 345 break; 346 case RISCVMCExpr::VK_RISCV_CALL_PLT: 347 FixupKind = RISCV::fixup_riscv_call_plt; 348 RelaxCandidate = true; 349 break; 350 } 351 } else if (Kind == MCExpr::SymbolRef && 352 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) { 353 if (Desc.getOpcode() == RISCV::JAL) { 354 FixupKind = RISCV::fixup_riscv_jal; 355 } else if (MIFrm == RISCVII::InstFormatB) { 356 FixupKind = RISCV::fixup_riscv_branch; 357 } else if (MIFrm == RISCVII::InstFormatCJ) { 358 FixupKind = RISCV::fixup_riscv_rvc_jump; 359 } else if (MIFrm == RISCVII::InstFormatCB) { 360 FixupKind = RISCV::fixup_riscv_rvc_branch; 361 } 362 } 363 364 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); 365 366 Fixups.push_back( 367 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); 368 ++MCNumFixups; 369 370 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is 371 // enabled and the current fixup will result in a relocation that may be 372 // relaxed. 373 if (EnableRelax && RelaxCandidate) { 374 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 375 Fixups.push_back( 376 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), 377 MI.getLoc())); 378 ++MCNumFixups; 379 } 380 381 return 0; 382} 383 384unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, 385 SmallVectorImpl<MCFixup> &Fixups, 386 const MCSubtargetInfo &STI) const { 387 MCOperand MO = MI.getOperand(OpNo); 388 assert(MO.isReg() && "Expected a register."); 389 390 switch (MO.getReg()) { 391 default: 392 llvm_unreachable("Invalid mask register."); 393 case RISCV::V0: 394 return 0; 395 case RISCV::NoRegister: 396 return 1; 397 } 398} 399 400#include "RISCVGenMCCodeEmitter.inc" 401