1//===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file provides RISCV-specific target descriptions. 10/// 11//===----------------------------------------------------------------------===// 12 13#include "RISCVMCTargetDesc.h" 14#include "RISCVELFStreamer.h" 15#include "RISCVInstPrinter.h" 16#include "RISCVMCAsmInfo.h" 17#include "RISCVTargetStreamer.h" 18#include "TargetInfo/RISCVTargetInfo.h" 19#include "Utils/RISCVBaseInfo.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/Register.h" 22#include "llvm/MC/MCAsmInfo.h" 23#include "llvm/MC/MCInstrAnalysis.h" 24#include "llvm/MC/MCInstrInfo.h" 25#include "llvm/MC/MCRegisterInfo.h" 26#include "llvm/MC/MCStreamer.h" 27#include "llvm/MC/MCSubtargetInfo.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/TargetRegistry.h" 30 31#define GET_INSTRINFO_MC_DESC 32#include "RISCVGenInstrInfo.inc" 33 34#define GET_REGINFO_MC_DESC 35#include "RISCVGenRegisterInfo.inc" 36 37#define GET_SUBTARGETINFO_MC_DESC 38#include "RISCVGenSubtargetInfo.inc" 39 40using namespace llvm; 41 42static MCInstrInfo *createRISCVMCInstrInfo() { 43 MCInstrInfo *X = new MCInstrInfo(); 44 InitRISCVMCInstrInfo(X); 45 return X; 46} 47 48static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { 49 MCRegisterInfo *X = new MCRegisterInfo(); 50 InitRISCVMCRegisterInfo(X, RISCV::X1); 51 return X; 52} 53 54static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, 55 const Triple &TT, 56 const MCTargetOptions &Options) { 57 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); 58 59 Register SP = MRI.getDwarfRegNum(RISCV::X2, true); 60 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); 61 MAI->addInitialFrameState(Inst); 62 63 return MAI; 64} 65 66static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, 67 StringRef CPU, StringRef FS) { 68 std::string CPUName = std::string(CPU); 69 if (CPUName.empty()) 70 CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; 71 return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS); 72} 73 74static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, 75 unsigned SyntaxVariant, 76 const MCAsmInfo &MAI, 77 const MCInstrInfo &MII, 78 const MCRegisterInfo &MRI) { 79 return new RISCVInstPrinter(MAI, MII, MRI); 80} 81 82static MCTargetStreamer * 83createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 84 const Triple &TT = STI.getTargetTriple(); 85 if (TT.isOSBinFormatELF()) 86 return new RISCVTargetELFStreamer(S, STI); 87 return nullptr; 88} 89 90static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, 91 formatted_raw_ostream &OS, 92 MCInstPrinter *InstPrint, 93 bool isVerboseAsm) { 94 return new RISCVTargetAsmStreamer(S, OS); 95} 96 97static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { 98 return new RISCVTargetStreamer(S); 99} 100 101namespace { 102 103class RISCVMCInstrAnalysis : public MCInstrAnalysis { 104public: 105 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) 106 : MCInstrAnalysis(Info) {} 107 108 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 109 uint64_t &Target) const override { 110 if (isConditionalBranch(Inst)) { 111 int64_t Imm; 112 if (Size == 2) 113 Imm = Inst.getOperand(1).getImm(); 114 else 115 Imm = Inst.getOperand(2).getImm(); 116 Target = Addr + Imm; 117 return true; 118 } 119 120 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { 121 Target = Addr + Inst.getOperand(0).getImm(); 122 return true; 123 } 124 125 if (Inst.getOpcode() == RISCV::JAL) { 126 Target = Addr + Inst.getOperand(1).getImm(); 127 return true; 128 } 129 130 return false; 131 } 132}; 133 134} // end anonymous namespace 135 136static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { 137 return new RISCVMCInstrAnalysis(Info); 138} 139 140extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { 141 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { 142 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); 143 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); 144 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); 145 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); 146 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); 147 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); 148 TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); 149 TargetRegistry::RegisterObjectTargetStreamer( 150 *T, createRISCVObjectTargetStreamer); 151 TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); 152 153 // Register the asm target streamer. 154 TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); 155 // Register the null target streamer. 156 TargetRegistry::RegisterNullTargetStreamer(*T, 157 createRISCVNullTargetStreamer); 158 } 159} 160