Searched refs:AArch64 (Results 1 - 25 of 68) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MacroFusion.cpp1 //===- AArch64MacroFusion.cpp - AArch64 Macro Fusion ----------------------===//
9 /// \file This file contains the AArch64 implementation of the DAG scheduling
25 if (SecondMI.getOpcode() != AArch64::Bcc)
33 case AArch64::ADDSWri:
34 case AArch64::ADDSWrr:
35 case AArch64::ADDSXri:
36 case AArch64::ADDSXrr:
37 case AArch64::ANDSWri:
38 case AArch64::ANDSWrr:
39 case AArch64
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H A DAArch64FalkorHWPFFix.cpp15 #include "AArch64.h"
247 case AArch64::LD1i64:
248 case AArch64::LD2i64:
255 case AArch64::LD1i8:
256 case AArch64::LD1i16:
257 case AArch64::LD1i32:
258 case AArch64::LD2i8:
259 case AArch64::LD2i16:
260 case AArch64::LD2i32:
261 case AArch64
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H A DAArch64DeadRegisterDefinitionsPass.cpp13 #include "AArch64.h"
32 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
79 case AArch64::LDADDB: case AArch64::LDADDH:
80 case AArch64::LDADDW: case AArch64::LDADDX:
81 case AArch64::LDADDLB: case AArch64::LDADDLH:
82 case AArch64::LDADDLW: case AArch64
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H A DAArch64CondBrTuning.cpp1 //===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
28 #include "AArch64.h"
44 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
120 case AArch64::CBZW:
121 case AArch64::CBZX:
124 case AArch64::CBNZW:
125 case AArch64
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H A DAArch64PBQPRegAlloc.cpp1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
8 // This file contains the AArch64 / Cortex-A57 specific register allocation
20 #include "AArch64.h"
37 return AArch64::FPR32RegClass.contains(reg) ||
38 AArch64::FPR64RegClass.contains(reg) ||
39 AArch64::FPR128RegClass.contains(reg);
47 case AArch64::S1:
48 case AArch64::S3:
49 case AArch64::S5:
50 case AArch64
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H A DAArch64InstrInfo.cpp1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
70 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP,
71 AArch64::CATCHRET),
83 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR)
110 case AArch64::TLSDESC_CALLSEQ:
114 case AArch64::JumpTableDest32:
115 case AArch64
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H A DAArch64StackTaggingPreRA.cpp1 //===-- AArch64StackTaggingPreRA.cpp --- Stack Tagging for AArch64 -----===//
11 #include "AArch64.h"
77 return "AArch64 Stack Tagging PreRA";
90 "AArch64 Stack Tagging PreRA Pass", false, false)
92 "AArch64 Stack Tagging PreRA Pass", false, false)
100 case AArch64::LDRBBui:
101 case AArch64::LDRHHui:
102 case AArch64::LDRWui:
103 case AArch64::LDRXui:
105 case AArch64
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H A DAArch64SIMDInstrOpt.cpp62 "AArch64 SIMD instructions optimization pass"
103 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
104 AArch64::STPQi, AArch64::FPR128RegClass),
105 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
106 AArch64
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H A DAArch64LoadStoreOptimizer.cpp1 //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
73 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
216 case AArch64::STRBBui:
217 case AArch64::STURBBi:
218 case AArch64::STRHHui:
219 case AArch64::STURHHi:
230 case AArch64::STGOffset:
231 case AArch64::STZGOffset:
232 case AArch64::ST2GOffset:
233 case AArch64
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H A DAArch64ExpandPseudoInsts.cpp46 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
117 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
135 case AArch64::ORRWri:
136 case AArch64::ORRXri:
139 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
142 case AArch64::MOVNWi:
143 case AArch64::MOVNXi:
144 case AArch64
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H A DAArch64CallingConvention.cpp1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
9 // This file contains the table-generated and custom routines for the AArch64
15 #include "AArch64.h"
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64
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H A DAArch64RedundantCopyElimination.cpp1 //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
52 #include "AArch64.h"
103 return "AArch64 Redundant Copy Elimination";
110 "AArch64 redundant copy elimination pass", false, false)
131 if (((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
133 ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
141 if (Opc != AArch64::Bcc)
176 case AArch64
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H A DAArch64AsmPrinter.cpp1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
10 // of machine-dependent LLVM code to the AArch64 assembly language.
14 #include "AArch64.h"
79 StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
301 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
304 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
313 MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
322 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
330 MCInstBuilder(AArch64::BL)
371 OutStreamer->EmitInstruction(MCInstBuilder(AArch64
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H A DAArch64CollectLOH.cpp1 //===---------- AArch64CollectLOH.cpp - AArch64 collect LOH pass --*- C++ -*-=//
100 #include "AArch64.h"
130 #define AARCH64_COLLECT_LOH_NAME "AArch64 Collect Linker Optimization Hint (LOH)"
180 case AArch64::ADRP:
182 case AArch64::ADDXri:
184 case AArch64::LDRXui:
185 case AArch64::LDRWui:
202 case AArch64::STRBBui:
203 case AArch64::STRHHui:
204 case AArch64
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H A DAArch64ISelDAGToDAG.cpp1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
9 // This file defines an instruction selector for the AArch64 target.
32 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
49 return "AArch64 Instruction Selection";
574 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
605 MLAOpc = AArch64::MLAv4i16_indexed;
608 MLAOpc = AArch64::MLAv8i16_indexed;
611 MLAOpc = AArch64::MLAv2i32_indexed;
614 MLAOpc = AArch64
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H A DAArch64ConditionalCompares.cpp1 //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
19 #include "AArch64.h"
99 // instructions. The AArch64 conditional compare instructions have an immediate
261 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
286 case AArch64::CBZW:
287 case AArch64::CBZX:
291 case AArch64::CBNZW:
292 case AArch64::CBNZX:
304 if (!I->readsRegister(AArch64
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H A DAArch64FrameLowering.cpp1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
9 // This file contains the AArch64 implementation of TargetFrameLowering class.
11 // On AArch64, stack frames are structured as follows:
165 cl::desc("enable use of redzone on AArch64"),
191 MI.getOpcode() == AArch64::ADDXri ||
192 MI.getOpcode() == AArch64::ADDSXri)
329 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, {Amount, MVT::i8},
336 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64
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H A DAArch64ConditionOptimizer.cpp1 //=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
60 #include "AArch64.h"
119 return "AArch64 Condition Optimizer";
128 "AArch64 CondOpt Pass", false, false)
131 "AArch64 CondOpt Pass", false, false)
152 if (I->getOpcode() != AArch64::Bcc)
157 if (SuccBB->isLiveIn(AArch64::NZCV))
165 if (I->readsRegister(AArch64::NZCV))
169 case AArch64::SUBSWri:
170 case AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64
652 namespace AArch64 { namespace in namespace:llvm
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
306 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
66 if (Opcode == AArch64::SYSxt)
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
81 bool Is64Bit = (Opcode == AArch64
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H A DAArch64MCTargetDesc.cpp1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
9 // This file provides AArch64 specific target descriptions.
65 {codeview::RegisterId::ARM64_W0, AArch64::W0},
66 {codeview::RegisterId::ARM64_W1, AArch64::W1},
67 {codeview::RegisterId::ARM64_W2, AArch64::W2},
68 {codeview::RegisterId::ARM64_W3, AArch64::W3},
69 {codeview::RegisterId::ARM64_W4, AArch64::W4},
70 {codeview::RegisterId::ARM64_W5, AArch64::W5},
71 {codeview::RegisterId::ARM64_W6, AArch64::W6},
72 {codeview::RegisterId::ARM64_W7, AArch64
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H A DAArch64WinCOFFObjectWriter.cpp1 //= AArch64WinCOFFObjectWriter.cpp - AArch64 Windows COFF Object Writer C++ =//
76 case AArch64::fixup_aarch64_add_imm12:
86 case AArch64::fixup_aarch64_ldst_imm12_scale1:
87 case AArch64::fixup_aarch64_ldst_imm12_scale2:
88 case AArch64::fixup_aarch64_ldst_imm12_scale4:
89 case AArch64::fixup_aarch64_ldst_imm12_scale8:
90 case AArch64::fixup_aarch64_ldst_imm12_scale16:
98 case AArch64::fixup_aarch64_pcrel_adr_imm21:
101 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
104 case AArch64
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H A DAArch64AsmBackend.cpp1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
44 return AArch64::NumTargetFixupKinds;
50 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
112 case AArch64::fixup_aarch64_tlsdesc_call:
122 case AArch64::fixup_aarch64_movw:
123 case AArch64::fixup_aarch64_pcrel_branch14:
124 case AArch64::fixup_aarch64_add_imm12:
125 case AArch64::fixup_aarch64_ldst_imm12_scale1:
126 case AArch64::fixup_aarch64_ldst_imm12_scale2:
127 case AArch64
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/
H A DAArch64TargetParser.cpp1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
9 // This file implements a target parser to recognise AArch64 hardware features
27 unsigned AArch64::getDefaultFPU(StringRef CPU, AArch64::ArchKind AK) {
38 unsigned AArch64::getDefaultExtensions(StringRef CPU, AArch64::ArchKind AK) {
48 .Default(AArch64::AEK_INVALID);
51 AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) {
55 return StringSwitch<AArch64
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