Lines Matching refs:AArch64
1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
66 if (Opcode == AArch64::SYSxt)
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
136 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
139 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
168 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
174 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
176 STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
178 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
188 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
211 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
212 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
214 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
224 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
236 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
243 Opcode == AArch64::MOVZXi ? 64 : 32)) {
250 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
265 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
266 (MI->getOperand(1).getReg() == AArch64::XZR ||
267 MI->getOperand(1).getReg() == AArch64::WZR) &&
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
279 if (Opcode == AArch64::CompilerBarrier) {
285 if (Opcode == AArch64::SPACE) {
293 if (Opcode == AArch64::TSB) {
304 (MI->getOperand(0).getReg() == AArch64::XZR ||
305 MI->getOperand(0).getReg() == AArch64::WZR)) {
313 case AArch64::TBXv8i8One:
314 case AArch64::TBXv8i8Two:
315 case AArch64::TBXv8i8Three:
316 case AArch64::TBXv8i8Four:
320 case AArch64::TBLv8i8One:
321 case AArch64::TBLv8i8Two:
322 case AArch64::TBLv8i8Three:
323 case AArch64::TBLv8i8Four:
327 case AArch64::TBXv16i8One:
328 case AArch64::TBXv16i8Two:
329 case AArch64::TBXv16i8Three:
330 case AArch64::TBXv16i8Four:
334 case AArch64::TBLv16i8One:
335 case AArch64::TBLv16i8Two:
336 case AArch64::TBLv16i8Three:
337 case AArch64::TBLv16i8Four:
356 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
357 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
358 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
359 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
360 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
361 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
362 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
363 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
364 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
365 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
366 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
367 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
368 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
369 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
370 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
371 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
372 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
373 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
374 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
375 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
376 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
377 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
378 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
379 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
380 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
381 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
382 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
383 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
384 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
385 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
386 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
387 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
388 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
389 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
390 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
391 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
392 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
393 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
394 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
395 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
396 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
397 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
398 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
399 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
400 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
401 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
402 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
403 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
404 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
405 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
406 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
407 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
408 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
409 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
410 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
411 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
412 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
413 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
414 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
415 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
416 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
417 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
418 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
419 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
420 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
421 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
422 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
423 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
424 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
425 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
426 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
427 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
428 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
429 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
430 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
431 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
432 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
433 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
434 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
435 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
436 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
437 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
438 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
439 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
440 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
441 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
442 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
443 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
444 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
445 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
446 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
447 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
448 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
449 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
450 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
451 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
452 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
453 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
454 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
455 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
456 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
457 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
458 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
459 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
460 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
461 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
462 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
463 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
464 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
465 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
466 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
467 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
468 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
469 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
470 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
471 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
472 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
473 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
474 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
475 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
476 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
477 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
478 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
479 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
480 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
481 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
482 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
483 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
484 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
485 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
486 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
487 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
488 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
489 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
490 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
491 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
492 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
493 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
494 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
495 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
496 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
497 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
498 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
499 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
500 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
501 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
502 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
503 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
504 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
505 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
506 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
507 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
508 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
509 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
510 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
511 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
512 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
513 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
514 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
515 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
516 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
517 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
518 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
519 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
520 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
521 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
522 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
523 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
524 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
525 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
526 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
527 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
528 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
529 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
530 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
531 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
532 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
533 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
534 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
535 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
536 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
537 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
538 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
539 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
540 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
541 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
542 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
543 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
544 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
545 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
546 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
547 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
548 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
549 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
550 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
551 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
552 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
553 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
554 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
555 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
556 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
557 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
558 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
559 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
560 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
561 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
562 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
563 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
564 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
565 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
566 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
567 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
568 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
569 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
570 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
571 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
572 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
573 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
574 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
575 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
576 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
577 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
578 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
579 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
580 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
581 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
582 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
583 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
584 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
585 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
586 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
587 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
588 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
589 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
590 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
591 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
592 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
593 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
594 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
595 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
596 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
597 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
598 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
599 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
600 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
601 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
602 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
603 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
604 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
605 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
606 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
607 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
608 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
609 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
610 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
611 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
612 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
613 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
614 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
615 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
616 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
617 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
618 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
619 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
620 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
621 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
622 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
623 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
624 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
625 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
626 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
627 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
628 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
629 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
630 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
631 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
632 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
633 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
634 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
635 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
636 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
637 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
638 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
639 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
640 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
641 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
642 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
643 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
644 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
645 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
646 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
647 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
648 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
649 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
650 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
651 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
652 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
653 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
654 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
655 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
656 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
657 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
658 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
659 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
660 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
661 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
662 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
663 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
664 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
665 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
666 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
667 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
668 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
669 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
670 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
671 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
672 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
673 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
674 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
675 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
676 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
677 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
678 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
679 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
680 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
681 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
682 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
683 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
684 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
685 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
686 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
687 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
688 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
689 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
690 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
691 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
692 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
693 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
694 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
695 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
717 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
723 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
746 if (Reg != AArch64::XZR)
766 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
908 if (Reg == AArch64::XZR)
922 O << getRegisterName(Reg, AArch64::vreg);
1003 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1005 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1165 case AArch64::Q0: Reg = AArch64::Q1; break;
1166 case AArch64::Q1: Reg = AArch64::Q2; break;
1167 case AArch64::Q2: Reg = AArch64::Q3; break;
1168 case AArch64::Q3: Reg = AArch64::Q4; break;
1169 case AArch64::Q4: Reg = AArch64::Q5; break;
1170 case AArch64::Q5: Reg = AArch64::Q6; break;
1171 case AArch64::Q6: Reg = AArch64::Q7; break;
1172 case AArch64::Q7: Reg = AArch64::Q8; break;
1173 case AArch64::Q8: Reg = AArch64::Q9; break;
1174 case AArch64::Q9: Reg = AArch64::Q10; break;
1175 case AArch64::Q10: Reg = AArch64::Q11; break;
1176 case AArch64::Q11: Reg = AArch64::Q12; break;
1177 case AArch64::Q12: Reg = AArch64::Q13; break;
1178 case AArch64::Q13: Reg = AArch64::Q14; break;
1179 case AArch64::Q14: Reg = AArch64::Q15; break;
1180 case AArch64::Q15: Reg = AArch64::Q16; break;
1181 case AArch64::Q16: Reg = AArch64::Q17; break;
1182 case AArch64::Q17: Reg = AArch64::Q18; break;
1183 case AArch64::Q18: Reg = AArch64::Q19; break;
1184 case AArch64::Q19: Reg = AArch64::Q20; break;
1185 case AArch64::Q20: Reg = AArch64::Q21; break;
1186 case AArch64::Q21: Reg = AArch64::Q22; break;
1187 case AArch64::Q22: Reg = AArch64::Q23; break;
1188 case AArch64::Q23: Reg = AArch64::Q24; break;
1189 case AArch64::Q24: Reg = AArch64::Q25; break;
1190 case AArch64::Q25: Reg = AArch64::Q26; break;
1191 case AArch64::Q26: Reg = AArch64::Q27; break;
1192 case AArch64::Q27: Reg = AArch64::Q28; break;
1193 case AArch64::Q28: Reg = AArch64::Q29; break;
1194 case AArch64::Q29: Reg = AArch64::Q30; break;
1195 case AArch64::Q30: Reg = AArch64::Q31; break;
1197 case AArch64::Q31:
1198 Reg = AArch64::Q0;
1200 case AArch64::Z0: Reg = AArch64::Z1; break;
1201 case AArch64::Z1: Reg = AArch64::Z2; break;
1202 case AArch64::Z2: Reg = AArch64::Z3; break;
1203 case AArch64::Z3: Reg = AArch64::Z4; break;
1204 case AArch64::Z4: Reg = AArch64::Z5; break;
1205 case AArch64::Z5: Reg = AArch64::Z6; break;
1206 case AArch64::Z6: Reg = AArch64::Z7; break;
1207 case AArch64::Z7: Reg = AArch64::Z8; break;
1208 case AArch64::Z8: Reg = AArch64::Z9; break;
1209 case AArch64::Z9: Reg = AArch64::Z10; break;
1210 case AArch64::Z10: Reg = AArch64::Z11; break;
1211 case AArch64::Z11: Reg = AArch64::Z12; break;
1212 case AArch64::Z12: Reg = AArch64::Z13; break;
1213 case AArch64::Z13: Reg = AArch64::Z14; break;
1214 case AArch64::Z14: Reg = AArch64::Z15; break;
1215 case AArch64::Z15: Reg = AArch64::Z16; break;
1216 case AArch64::Z16: Reg = AArch64::Z17; break;
1217 case AArch64::Z17: Reg = AArch64::Z18; break;
1218 case AArch64::Z18: Reg = AArch64::Z19; break;
1219 case AArch64::Z19: Reg = AArch64::Z20; break;
1220 case AArch64::Z20: Reg = AArch64::Z21; break;
1221 case AArch64::Z21: Reg = AArch64::Z22; break;
1222 case AArch64::Z22: Reg = AArch64::Z23; break;
1223 case AArch64::Z23: Reg = AArch64::Z24; break;
1224 case AArch64::Z24: Reg = AArch64::Z25; break;
1225 case AArch64::Z25: Reg = AArch64::Z26; break;
1226 case AArch64::Z26: Reg = AArch64::Z27; break;
1227 case AArch64::Z27: Reg = AArch64::Z28; break;
1228 case AArch64::Z28: Reg = AArch64::Z29; break;
1229 case AArch64::Z29: Reg = AArch64::Z30; break;
1230 case AArch64::Z30: Reg = AArch64::Z31; break;
1232 case AArch64::Z31:
1233 Reg = AArch64::Z0;
1249 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1250 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1268 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1269 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1270 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1272 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1273 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1274 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1276 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1277 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1278 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1282 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1284 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1286 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1291 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1293 MRI.getRegClass(AArch64::FPR128RegClassID);
1294 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1298 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1301 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1385 if (Opcode == AArch64::ISB) {
1388 } else if (Opcode == AArch64::TSB) {
1568 case 8: Base = AArch64::B0; break;
1569 case 16: Base = AArch64::H0; break;
1570 case 32: Base = AArch64::S0; break;
1571 case 64: Base = AArch64::D0; break;
1572 case 128: Base = AArch64::Q0; break;
1577 O << getRegisterName(Reg - AArch64::Z0 + Base);