Lines Matching refs:AArch64
1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
9 // This file contains the AArch64 implementation of TargetFrameLowering class.
11 // On AArch64, stack frames are structured as follows:
165 cl::desc("enable use of redzone on AArch64"),
191 MI.getOpcode() == AArch64::ADDXri ||
192 MI.getOpcode() == AArch64::ADDSXri)
329 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, {Amount, MVT::i8},
336 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP,
361 if (Info.getReg() == AArch64::LR)
410 return AArch64::X9;
424 if (LiveRegs.available(MRI, AArch64::X9))
425 return AArch64::X9;
427 for (unsigned Reg : AArch64::GPR64RegClass) {
431 return AArch64::NoRegister;
446 return findScratchNonCalleeSaveRegister(TmpMBB) != AArch64::NoRegister;
519 case AArch64::LDPDpost:
522 case AArch64::STPDpre: {
525 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP_X))
532 case AArch64::LDPXpost:
535 case AArch64::STPXpre: {
538 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
539 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR_X))
543 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP_X))
550 case AArch64::LDRDpost:
553 case AArch64::STRDpre: {
555 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg_X))
561 case AArch64::LDRXpost:
564 case AArch64::STRXpre: {
566 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg_X))
572 case AArch64::STPDi:
573 case AArch64::LDPDi: {
576 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP))
583 case AArch64::STPXi:
584 case AArch64::LDPXi: {
587 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
588 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR))
592 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP))
599 case AArch64::STRXui:
600 case AArch64::LDRXui: {
602 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg))
608 case AArch64::STRDui:
609 case AArch64::LDRDui: {
611 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg))
630 case AArch64::SEH_SaveFPLR:
631 case AArch64::SEH_SaveRegP:
632 case AArch64::SEH_SaveReg:
633 case AArch64::SEH_SaveFRegP:
634 case AArch64::SEH_SaveFReg:
651 while (MBBI->getOpcode() == AArch64::STRXpost ||
652 MBBI->getOpcode() == AArch64::LDRXpre ||
653 MBBI->getOpcode() == AArch64::CFI_INSTRUCTION) {
654 if (MBBI->getOpcode() != AArch64::CFI_INSTRUCTION)
655 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
663 case AArch64::STPXi:
664 NewOpc = AArch64::STPXpre;
667 case AArch64::STPDi:
668 NewOpc = AArch64::STPDpre;
671 case AArch64::STPQi:
672 NewOpc = AArch64::STPQpre;
675 case AArch64::STRXui:
676 NewOpc = AArch64::STRXpre;
678 case AArch64::STRDui:
679 NewOpc = AArch64::STRDpre;
681 case AArch64::STRQui:
682 NewOpc = AArch64::STRQpre;
684 case AArch64::LDPXi:
685 NewOpc = AArch64::LDPXpost;
688 case AArch64::LDPDi:
689 NewOpc = AArch64::LDPDpost;
692 case AArch64::LDPQi:
693 NewOpc = AArch64::LDPQpost;
696 case AArch64::LDRXui:
697 NewOpc = AArch64::LDRXpost;
699 case AArch64::LDRDui:
700 NewOpc = AArch64::LDRDpost;
702 case AArch64::LDRQui:
703 NewOpc = AArch64::LDRQpost;
714 MIB.addReg(AArch64::SP, RegState::Define);
725 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
756 if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre ||
757 Opc == AArch64::CFI_INSTRUCTION) {
758 if (Opc != AArch64::CFI_INSTRUCTION)
759 assert(MI.getOperand(0).getReg() != AArch64::SP);
765 case AArch64::STPXi:
766 case AArch64::STRXui:
767 case AArch64::STPDi:
768 case AArch64::STRDui:
769 case AArch64::LDPXi:
770 case AArch64::LDRXui:
771 case AArch64::LDPDi:
772 case AArch64::LDRDui:
775 case AArch64::STPQi:
776 case AArch64::STRQui:
777 case AArch64::LDPQi:
778 case AArch64::LDRQui:
786 assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
866 case AArch64::STR_ZXI:
867 case AArch64::STR_PXI:
868 case AArch64::LDR_ZXI:
869 case AArch64::LDR_PXI:
905 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
908 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
910 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIBSP))
954 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
971 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
988 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
1023 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP,
1042 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVZXi), AArch64::X15)
1046 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1049 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X15)
1050 .addReg(AArch64::X15)
1054 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1058 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), AArch64::X15)
1068 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
1070 .addReg(AArch64::X15, RegState::Implicit)
1071 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1072 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
1073 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
1077 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1082 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVaddrEXT))
1083 .addReg(AArch64::X16, RegState::Define)
1089 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1093 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR))
1094 .addReg(AArch64::X16, RegState::Kill)
1095 .addReg(AArch64::X15, RegState::Implicit | RegState::Define)
1096 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1097 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
1098 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
1102 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1108 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP)
1109 .addReg(AArch64::SP, RegState::Kill)
1110 .addReg(AArch64::X15, RegState::Kill)
1115 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1144 emitFrameOffset(MBB, CalleeSavesBegin, DL, AArch64::SP, AArch64::SP,
1149 emitFrameOffset(MBB, CalleeSavesEnd, DL, AArch64::SP, AArch64::SP,
1158 unsigned scratchSPReg = AArch64::SP;
1162 assert(scratchSPReg != AArch64::NoRegister);
1170 emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP,
1178 assert(scratchSPReg != AArch64::SP);
1191 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
1197 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1213 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
1217 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1225 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
1235 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), AArch64::FP)
1236 .addReg(AArch64::X1)
1238 MBB.addLiveIn(AArch64::X1);
1354 MBBI->getOpcode() == AArch64::RET_ReallyLR) {
1356 TII->get(ShouldSignWithAKey(MF) ? AArch64::RETAA : AArch64::RETAB))
1362 TII->get(ShouldSignWithAKey(MF) ? AArch64::AUTIASP : AArch64::AUTIBSP))
1371 case AArch64::CATCHRET:
1372 case AArch64::CLEANUPRET:
1396 IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
1397 RetOpcode == AArch64::TCRETURNri ||
1398 RetOpcode == AArch64::TCRETURNriBTI;
1511 BuildMI(MBB, LastPopI, DL, TII->get(AArch64::SEH_EpilogStart))
1520 emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
1525 TII->get(AArch64::SEH_EpilogEnd))
1562 emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::FP,
1568 emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::SP,
1573 emitFrameOffset(MBB, RestoreBegin, DL, AArch64::SP, AArch64::SP,
1576 emitFrameOffset(MBB, RestoreEnd, DL, AArch64::SP, AArch64::SP,
1601 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1608 TII->get(AArch64::SEH_EpilogEnd))
1624 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
1628 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1642 if (Prev->getOpcode() != AArch64::LDRXpre ||
1643 Prev->getOperand(0).getReg() == AArch64::SP)
1650 emitFrameOffset(MBB, FirstSPPopI, DL, AArch64::SP, AArch64::SP,
1655 BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd))
1704 return RegInfo->getLocalAddressRegister(MF) == AArch64::FP
1823 : (unsigned)AArch64::SP;
1844 FrameReg = AArch64::SP;
1883 if (Reg2 == AArch64::FP)
1904 return Reg2 == AArch64::LR;
1912 unsigned Reg1 = AArch64::NoRegister;
1913 unsigned Reg2 = AArch64::NoRegister;
1920 bool isPaired() const { return Reg2 != AArch64::NoRegister; }
1973 if (AArch64::GPR64RegClass.contains(RPI.Reg1))
1975 else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
1977 else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
1979 else if (AArch64::ZPRRegClass.contains(RPI.Reg1))
1981 else if (AArch64::PPRRegClass.contains(RPI.Reg1))
1991 if (AArch64::GPR64RegClass.contains(NextReg) &&
1997 if (AArch64::FPR64RegClass.contains(NextReg) &&
2002 if (AArch64::FPR128RegClass.contains(NextReg))
2013 if ((RPI.Reg1 == AArch64::LR || RPI.Reg2 == AArch64::LR) &&
2030 assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP ||
2031 RPI.Reg1 == AArch64::LR) &&
2035 assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg1 != AArch64::FP ||
2036 RPI.Reg2 == AArch64::LR) &&
2044 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
2102 BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost))
2103 .addReg(AArch64::X18, RegState::Define)
2104 .addReg(AArch64::LR)
2105 .addReg(AArch64::X18)
2110 BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
2125 BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
2131 MBB.addLiveIn(AArch64::X18);
2154 StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
2159 StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
2164 StrOpc = RPI.isPaired() ? AArch64::STPQi : AArch64::STRQui;
2169 StrOpc = AArch64::STR_ZXI;
2174 StrOpc = AArch64::STR_PXI;
2185 assert((!NeedsWinCFI || !(Reg1 == AArch64::LR && Reg2 == AArch64::FP)) &&
2208 .addReg(AArch64::SP)
2260 LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
2265 LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
2270 LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
2275 LdrOpc = AArch64::LDR_ZXI;
2280 LdrOpc = AArch64::LDR_PXI;
2308 .addReg(AArch64::SP)
2335 BuildMI(MBB, MI, DL, TII.get(AArch64::LDRXpre))
2336 .addReg(AArch64::X18, RegState::Define)
2337 .addReg(AArch64::LR, RegState::Define)
2338 .addReg(AArch64::X18)
2358 unsigned UnspilledCSGPR = AArch64::NoRegister;
2359 unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
2366 : (unsigned)AArch64::NoRegister;
2378 unsigned PairedReg = AArch64::NoRegister;
2379 if (AArch64::GPR64RegClass.contains(Reg) ||
2380 AArch64::FPR64RegClass.contains(Reg) ||
2381 AArch64::FPR128RegClass.contains(Reg))
2385 if (AArch64::GPR64RegClass.contains(Reg) &&
2396 if (produceCompactUnwindFrame(MF) && PairedReg != AArch64::NoRegister &&
2399 if (AArch64::GPR64RegClass.contains(PairedReg) &&
2412 if (AArch64::PPRRegClass.contains(Reg) ||
2413 AArch64::ZPRRegClass.contains(Reg))
2426 SavedRegs.set(AArch64::FP);
2427 SavedRegs.set(AArch64::LR);
2458 if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
2474 const TargetRegisterClass &RC = AArch64::GPR64RegClass;
2519 if (AArch64::ZPRRegClass.contains(CS.getReg()) ||
2520 AArch64::PPRRegClass.contains(CS.getReg())) {
2654 unsigned DstReg = RS->FindUnusedReg(&AArch64::GPR64commonRegClass);
2656 BuildMI(MBB, MBBI, DL, TII.get(AArch64::MOVi64imm), DstReg).addImm(-2);
2657 BuildMI(MBB, MBBI, DL, TII.get(AArch64::STURXi))
2663 /// For Win64 AArch64 EH, the offset to the Unwind object is from the SP before
2673 FrameReg = AArch64::SP;