Lines Matching refs:AArch64
46 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
117 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
135 case AArch64::ORRWri:
136 case AArch64::ORRXri:
139 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
142 case AArch64::MOVNWi:
143 case AArch64::MOVNXi:
144 case AArch64::MOVZWi:
145 case AArch64::MOVZXi: {
154 case AArch64::MOVKWi:
155 case AArch64::MOVKXi: {
205 BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
213 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
216 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
226 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
286 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
290 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
294 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
295 .addUse(AArch64::WZR)
296 .addUse(AArch64::WZR)
298 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
302 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
306 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
315 BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)
319 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
357 bool ZeroData = MI.getOpcode() == AArch64::STZGloop;
359 ZeroData ? AArch64::STZ2GPostIndex : AArch64::ST2GPostIndex;
374 BuildMI(LoopBB, DL, TII->get(AArch64::SUBXri))
379 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
416 case AArch64::ADDWrr:
417 case AArch64::SUBWrr:
418 case AArch64::ADDXrr:
419 case AArch64::SUBXrr:
420 case AArch64::ADDSWrr:
421 case AArch64::SUBSWrr:
422 case AArch64::ADDSXrr:
423 case AArch64::SUBSXrr:
424 case AArch64::ANDWrr:
425 case AArch64::ANDXrr:
426 case AArch64::BICWrr:
427 case AArch64::BICXrr:
428 case AArch64::ANDSWrr:
429 case AArch64::ANDSXrr:
430 case AArch64::BICSWrr:
431 case AArch64::BICSXrr:
432 case AArch64::EONWrr:
433 case AArch64::EONXrr:
434 case AArch64::EORWrr:
435 case AArch64::EORXrr:
436 case AArch64::ORNWrr:
437 case AArch64::ORNXrr:
438 case AArch64::ORRWrr:
439 case AArch64::ORRXrr: {
444 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break;
445 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
446 case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break;
447 case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break;
448 case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break;
449 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
450 case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break;
451 case AArch64::SUBSXrr: Opcode = AArch64::SUBSXrs; break;
452 case AArch64::ANDWrr: Opcode = AArch64::ANDWrs; break;
453 case AArch64::ANDXrr: Opcode = AArch64::ANDXrs; break;
454 case AArch64::BICWrr: Opcode = AArch64::BICWrs; break;
455 case AArch64::BICXrr: Opcode = AArch64::BICXrs; break;
456 case AArch64::ANDSWrr: Opcode = AArch64::ANDSWrs; break;
457 case AArch64::ANDSXrr: Opcode = AArch64::ANDSXrs; break;
458 case AArch64::BICSWrr: Opcode = AArch64::BICSWrs; break;
459 case AArch64::BICSXrr: Opcode = AArch64::BICSXrs; break;
460 case AArch64::EONWrr: Opcode = AArch64::EONWrs; break;
461 case AArch64::EONXrr: Opcode = AArch64::EONXrs; break;
462 case AArch64::EORWrr: Opcode = AArch64::EORWrs; break;
463 case AArch64::EORXrr: Opcode = AArch64::EORXrs; break;
464 case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break;
465 case AArch64::ORNXrr: Opcode = AArch64::ORNXrs; break;
466 case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
467 case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
480 case AArch64::LOADgot: {
489 TII->get(AArch64::LDRXl), DstReg);
505 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
510 unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32);
512 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui))
518 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui))
548 case AArch64::MOVaddr:
549 case AArch64::MOVaddrJT:
550 case AArch64::MOVaddrCP:
551 case AArch64::MOVaddrBA:
552 case AArch64::MOVaddrTLS:
553 case AArch64::MOVaddrEXT: {
557 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
571 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
578 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
588 case AArch64::ADDlowTLS:
590 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
598 case AArch64::MOVbaseTLS: {
611 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
617 case AArch64::MOVi32imm:
619 case AArch64::MOVi64imm:
621 case AArch64::RET_ReallyLR: {
628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
629 .addReg(AArch64::LR, RegState::Undef);
634 case AArch64::CMP_SWAP_8:
635 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB,
636 AArch64::SUBSWrx,
638 AArch64::WZR, NextMBBI);
639 case AArch64::CMP_SWAP_16:
640 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH,
641 AArch64::SUBSWrx,
643 AArch64::WZR, NextMBBI);
644 case AArch64::CMP_SWAP_32:
645 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW,
646 AArch64::SUBSWrs,
648 AArch64::WZR, NextMBBI);
649 case AArch64::CMP_SWAP_64:
651 AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs,
653 AArch64::XZR, NextMBBI);
654 case AArch64::CMP_SWAP_128:
657 case AArch64::AESMCrrTied:
658 case AArch64::AESIMCrrTied: {
661 TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
662 AArch64::AESIMCrr))
669 case AArch64::IRGstack: {
691 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG))
698 case AArch64::TAGPstack: {
701 TII->get(Offset >= 0 ? AArch64::ADDG : AArch64::SUBG))
709 case AArch64::STGloop:
710 case AArch64::STZGloop: