Searched refs:ZEXTLOAD (Results 1 - 25 of 34) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1018 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
1026 ZEXTLOAD enumerator in enum:llvm::ISD::LoadExtType
1029 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
H A DBasicTTIImpl.h734 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
H A DSelectionDAGNodes.h2627 /// Returns true if the specified node is a ZEXTLOAD.
2630 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
H A DTargetLowering.h2365 LType = ISD::ZEXTLOAD;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp663 case ISD::ZEXTLOAD: OS << ", zext"; break;
695 case ISD::ZEXTLOAD: OS << ", zext"; break;
H A DDAGCombiner.cpp4787 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4788 // ZEXTLOAD will match without needing to change the size of the value being
4803 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4806 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4915 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
4917 // ZEXTLOAD is already small enough.
4918 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5298 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5301 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
[all...]
H A DLegalizeDAG.cpp730 // load an i8. This trick is correct for ZEXTLOAD because the top 7
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
762 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
788 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
790 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
817 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
826 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
907 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
H A DLegalizeVectorOps.cpp811 case ISD::ZEXTLOAD:
H A DTargetLowering.cpp3239 // ZEXTLOAD / SEXTLOAD
3240 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
6788 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
6790 HiExtType = ISD::ZEXTLOAD;
6795 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
6810 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp76 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1468 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1623 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
H A DAMDGPUISelLowering.cpp111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
149 setLoadExtAction(ISD::ZEXTLOAD, V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
286 IntExt = ISD::ZEXTLOAD;
H A DHexagonISelLowering.cpp1445 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1505 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1524 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1527 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp248 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
256 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
263 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
447 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp293 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
327 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
2055 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
2066 ISD::ZEXTLOAD);
2097 case ISD::ZEXTLOAD:
2255 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
H A DSystemZISelDAGToDAG.cpp997 Load->getExtensionType() == ISD::ZEXTLOAD) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp315 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
491 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
2716 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
4407 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp95 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
336 LD->getExtensionType() == ISD::ZEXTLOAD))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp68 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1443 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1447 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
693 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
3103 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3125 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
8191 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
15238 LD->getExtensionType() == ISD::ZEXTLOAD))

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