Searched refs:SREM (Results 1 - 25 of 35) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp689 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
693 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
697 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
701 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
706 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
710 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
714 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
718 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
979 case ISD::SREM:
H A DARMISelLowering.cpp210 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::SREM, VT, Expand);
1133 setOperationAction(ISD::SREM, MVT::i32, Expand);
1140 setOperationAction(ISD::SREM, MVT::i64, Custom);
8992 // TODO: Support SREM
9325 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
9439 case ISD::SREM:
16194 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
16197 N->getOpcode() == ISD::SREM;
16212 N->getOpcode() == ISD::SREM ||
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2283 case ISD::SREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
253 if (ISD == ISD::SDIV || ISD == ISD::SREM) {
269 if (ISD == ISD::SREM) {
270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
393 { ISD::SREM, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1932 case ISD::SREM:
1953 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
2054 if (!selectBinaryOp(I, ISD::SREM))
2055 return selectDivRem(I, ISD::SREM);
H A DMipsSEISelLowering.cpp242 setOperationAction(ISD::SREM, MVT::i32, Legal);
289 setOperationAction(ISD::SREM, MVT::i64, Legal);
340 setOperationAction(ISD::SREM, Ty, Legal);
2058 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h701 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
H A DSelectionDAGDumper.cpp232 case ISD::SREM: return "srem";
H A DLegalizeDAG.cpp3276 case ISD::SREM: {
3278 bool isSigned = Node->getOpcode() == ISD::SREM;
4148 case ISD::SREM:
4324 case ISD::SREM:
4342 case ISD::SREM:
H A DLegalizeVectorTypes.cpp136 case ISD::SREM:
929 case ISD::SREM:
2742 case ISD::SREM:
H A DLegalizeVectorOps.cpp373 case ISD::SREM:
H A DFastISel.cpp1834 return selectBinaryOp(I, ISD::SREM);
H A DSelectionDAG.cpp3180 case ISD::SREM:
4819 case ISD::SREM:
4862 case ISD::SREM:
5195 case ISD::SREM:
5470 case ISD::SREM:
5492 case ISD::SREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp88 setOperationAction(ISD::SREM, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp138 setOperationAction(ISD::SREM, MVT::i8, Promote);
144 setOperationAction(ISD::SREM, MVT::i16, LibCall);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp150 setOperationAction(ISD::SREM, MVT::i8, Expand);
151 setOperationAction(ISD::SREM, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp791 case ISD::SREM:
1605 case SRem: return ISD::SREM;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp523 setTargetDAGCombine(ISD::SREM);
4543 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4552 bool IsSigned = N->getOpcode() == ISD::SREM;
4771 case ISD::SREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp110 setOperationAction(ISD::SREM, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4653 case ISD::SREM:
5171 if (!selectBinaryOp(I, ISD::SREM))
5172 return selectRem(I, ISD::SREM);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp177 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1428 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1496 setOperationAction(ISD::SREM, MVT::i32, Expand);
1503 setOperationAction(ISD::SREM, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp261 // PowerPC has no SREM/UREM instructions unless we are on P9
268 setOperationAction(ISD::SREM, MVT::i32, Custom);
270 setOperationAction(ISD::SREM, MVT::i64, Custom);
273 setOperationAction(ISD::SREM, MVT::i32, Expand);
275 setOperationAction(ISD::SREM, MVT::i64, Expand);
279 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
654 setOperationAction(ISD::SREM, VT, Expand);
9886 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
10519 case ISD::SREM:

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