/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiAluCode.h | 37 SRA = 0x37, enumerator in enum:llvm::LPAC::AluCode 96 case SRA: 114 .Case("sha", SRA) 138 case ISD::SRA: 139 return AluCode::SRA;
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H A D | LanaiMemAluCombiner.cpp | 224 return LPAC::SRA;
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/freebsd-11-stable/contrib/telnet/libtelnet/ |
H A D | auth-proto.h | 98 #ifdef SRA
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H A D | auth.c | 168 #ifdef SRA
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H A D | sra.c | 35 #ifdef SRA 143 printf("Trying SRA secure login:\r\n"); 153 /* server received an IS -- could be SRA KEY, USER, or PASS */ 169 printf("SRA user rejected for bad PKB\r\n"); 218 printf("SRA user accepted\r\n"); 229 printf("SRA user failed\r\n"); 236 printf("Unknown SRA option %d\r\n", data[-1]); 244 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */ 260 printf("SRA user rejected for bad PKB\r\n"); 302 printf("[ SRA logi [all...] |
/freebsd-11-stable/crypto/heimdal/appl/telnet/libtelnet/ |
H A D | auth-proto.h | 91 #ifdef SRA
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H A D | auth.c | 119 #ifdef SRA
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 338 { ISD::SRA, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, local 176 return SRA;
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H A D | SystemZShortenInst.cpp | 327 TwoOperandOpcode == SystemZ::SRA) {
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H A D | SystemZISelDAGToDAG.cpp | 907 case ISD::SRA: { 917 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { 1859 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; 1878 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 708 ShiftOp = ISD::SRA; 788 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; 1002 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); 1303 case ISD::SRA: 1908 case ISD::SRA: 2025 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2027 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 2030 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 2032 Hi = DAG.getNode(ISD::SRA, D [all...] |
H A D | LegalizeVectorOps.cpp | 17 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 107 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 386 case ISD::SRA: 819 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); 1056 // Make sure that the SRA and SHL instructions are available. 1057 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || 1069 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); 1126 return DAG.getNode(ISD::SRA, DL, VT,
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H A D | SelectionDAGBuilder.h | 711 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType 542 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 245 case LPAC::SRA:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 76 setOperationAction(ISD::SRA, MVT::i8, Custom); 79 setOperationAction(ISD::SRA, MVT::i16, Custom); 344 case ISD::SRA: return LowerShifts(Op, DAG); 985 case ISD::SRA: 989 Victim = (Opc == ISD::SRA) 1207 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 102 setOperationAction(ISD::SRA, MVT::i32, Legal); 192 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 81 setOperationAction(ISD::SRA, MVT::i8, Custom); 84 setOperationAction(ISD::SRA, MVT::i16, Custom); 303 case ISD::SRA: 313 case ISD::SRA: 688 case ISD::SRA:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 837 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; local 852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); 856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); 857 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
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H A D | AMDGPUISelLowering.cpp | 371 setOperationAction(ISD::SRA, VT, Expand); 488 setTargetDAGCombine(ISD::SRA); 1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq, 2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); 2219 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); 2220 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, 2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); 3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, 3139 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, 3251 Src.getOpcode() == ISD::SRA || [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 403 case ISD::SRA: 1681 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) 1744 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && 1745 "N must be a SHR/SRA operation to call this function"); 1800 // SRA requires a signed extraction 1802 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri; 1804 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri; 1818 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) 1877 case ISD::SRA: 2571 case ISD::SRA [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 107 setOperationAction(ISD::SRA, T, Custom); 159 setOperationAction(ISD::SRA, T, Custom); 1548 case ISD::SRA: 1574 case ISD::SRA:
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.cpp | 1870 for (Record *SRA : SRADefs) { 1871 if (SRA->getValueInit("SchedModel")->isComplete()) { 1872 Record *ModelDef = SRA->getValueAsDef("SchedModel"); 1873 addReadAdvance(SRA, getProcModel(ModelDef).Index);
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