Searched refs:SRA (Results 1 - 25 of 62) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h37 SRA = 0x37, enumerator in enum:llvm::LPAC::AluCode
96 case SRA:
114 .Case("sha", SRA)
138 case ISD::SRA:
139 return AluCode::SRA;
H A DLanaiMemAluCombiner.cpp224 return LPAC::SRA;
/freebsd-11-stable/contrib/telnet/libtelnet/
H A Dauth-proto.h98 #ifdef SRA
H A Dauth.c168 #ifdef SRA
H A Dsra.c35 #ifdef SRA
143 printf("Trying SRA secure login:\r\n");
153 /* server received an IS -- could be SRA KEY, USER, or PASS */
169 printf("SRA user rejected for bad PKB\r\n");
218 printf("SRA user accepted\r\n");
229 printf("SRA user failed\r\n");
236 printf("Unknown SRA option %d\r\n", data[-1]);
244 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */
260 printf("SRA user rejected for bad PKB\r\n");
302 printf("[ SRA logi
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/freebsd-11-stable/crypto/heimdal/appl/telnet/libtelnet/
H A Dauth-proto.h91 #ifdef SRA
H A Dauth.c119 #ifdef SRA
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp255 // normally expanded to the sequence SRA + SRL + ADD + SRA.
293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
304 { ISD::SRA, MVT::v2i64, 1 },
305 { ISD::SRA, MVT::v4i64, 1 },
306 { ISD::SRA, MVT::v8i64, 1 },
319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
338 { ISD::SRA, MV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, local
176 return SRA;
H A DSystemZShortenInst.cpp327 TwoOperandOpcode == SystemZ::SRA) {
H A DSystemZISelDAGToDAG.cpp907 case ISD::SRA: {
917 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
1859 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA;
1878 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
708 ShiftOp = ISD::SRA;
788 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1002 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
1303 case ISD::SRA:
1908 case ISD::SRA:
2025 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2027 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2030 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2032 Hi = DAG.getNode(ISD::SRA, D
[all...]
H A DLegalizeVectorOps.cpp17 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
107 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
386 case ISD::SRA:
819 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
1056 // Make sure that the SRA and SHL instructions are available.
1057 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
1069 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
1126 return DAG.getNode(ISD::SRA, DL, VT,
H A DSelectionDAGBuilder.h711 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
542 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp245 case LPAC::SRA:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp76 setOperationAction(ISD::SRA, MVT::i8, Custom);
79 setOperationAction(ISD::SRA, MVT::i16, Custom);
344 case ISD::SRA: return LowerShifts(Op, DAG);
985 case ISD::SRA:
989 Victim = (Opc == ISD::SRA)
1207 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp102 setOperationAction(ISD::SRA, MVT::i32, Legal);
192 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp81 setOperationAction(ISD::SRA, MVT::i8, Custom);
84 setOperationAction(ISD::SRA, MVT::i16, Custom);
303 case ISD::SRA:
313 case ISD::SRA:
688 case ISD::SRA:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp837 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; local
852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
857 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
H A DAMDGPUISelLowering.cpp371 setOperationAction(ISD::SRA, VT, Expand);
488 setTargetDAGCombine(ISD::SRA);
1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2219 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2220 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3139 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3251 Src.getOpcode() == ISD::SRA ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp403 case ISD::SRA:
1681 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1744 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1745 "N must be a SHR/SRA operation to call this function");
1800 // SRA requires a signed extraction
1802 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1804 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1818 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1877 case ISD::SRA:
2571 case ISD::SRA
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp107 setOperationAction(ISD::SRA, T, Custom);
159 setOperationAction(ISD::SRA, T, Custom);
1548 case ISD::SRA:
1574 case ISD::SRA:
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp1870 for (Record *SRA : SRADefs) {
1871 if (SRA->getValueInit("SchedModel")->isComplete()) {
1872 Record *ModelDef = SRA->getValueAsDef("SchedModel");
1873 addReadAdvance(SRA, getProcModel(ModelDef).Index);

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