/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1043 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 1061 SETULT, // 1 1 0 0 True if unordered or less than enumerator in enum:llvm::ISD::CondCode 1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 215 case FCmpInst::FCMP_ULT: return ISD::SETULT; 227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; 247 case ICmpInst::ICMP_ULT: return ISD::SETULT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 3061 case ISD::SETULT: { 3234 case ISD::SETULT: { 3390 case ISD::SETULT: { 3553 case ISD::SETULT: { 3802 case ISD::SETULT: 3829 case ISD::SETULT: 3885 case ISD::SETULT: return PPC::PRED_LT; 3917 case ISD::SETULT: return 0; 3938 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; 3946 case ISD::SETULT [all...] |
H A D | PPCISelLowering.cpp | 515 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 516 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 939 setCondCodeAction(ISD::SETULT, MVT::f128, Expand); 7640 case ISD::SETULT: 7676 case ISD::SETULT: 12345 case ISD::SETULT: 15906 case ISD::SETULT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 488 case ISD::SETULT: 694 SET_NEWCC(SETULT, JULT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertSkips.cpp | 234 case ISD::SETULT:
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H A D | R600ISelLowering.cpp | 136 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); 821 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); 822 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); 859 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); 860 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 371 case ISD::SETULT: 2939 if (Cond == ISD::CondCode::SETULT) { 3189 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 3374 case ISD::SETULT: 3397 case ISD::SETULT: 3599 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 3611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { 3666 // SETULT X, SINTMIN -> SETGT X, -1 3667 if (Cond == ISD::SETULT [all...] |
H A D | LegalizeIntegerTypes.cpp | 1394 case ISD::SETULT: 2157 Amt, NVBitsNode, ISD::SETULT); 2227 return std::make_pair(ISD::SETULT, ISD::UMIN); 2357 ISD::SETULT); 2369 ISD::SETULT); 2378 LoOps[0], LoOps[1], ISD::SETULT); 2451 Cond = ISD::SETULT; 3205 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); 3858 case ISD::SETULT: LowCC = ISD::SETULT; brea [all...] |
H A D | SelectionDAGDumper.cpp | 420 case ISD::SETULT: return "setult";
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H A D | LegalizeDAG.cpp | 1694 case ISD::SETULT: 3178 case ISD::UMIN: Pred = ISD::SETULT; break; 3456 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
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H A D | SelectionDAG.cpp | 393 case ISD::SETULT: 415 if (IsInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 435 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 438 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 2061 case ISD::SETULT: return getBoolConstant(C1.ult(C2), dl, VT, OpVT); 2121 case ISD::SETULT: return getBoolConstant(R==APFloat::cmpUnordered ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 49 case ISD::SETULT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 436 case ISD::SETULT: 530 CC = ISD::SETULT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 960 case ISD::SETULT: 1767 Op->getOperand(2), ISD::SETULT); 1773 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1856 Op->getOperand(2), ISD::SETULT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT, 828 case ISD::SETULT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 160 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, 384 case ISD::SETULT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 1083 case ISD::SETULT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 121 setCondCodeAction(ISD::SETULT, T, Expand);
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H A D | HexagonISelLowering.cpp | 1570 setCondCodeAction(ISD::SETULT, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 90 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1844 case ISD::SETULT: return ARMCC::LO; 1870 case ISD::SETULT: CondCode = ARMCC::LT; break; 4232 case ISD::SETULT: 4235 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 4249 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 4658 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT) 4664 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT) 4675 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || 6290 case ISD::SETULT: Invert = true; Opc = ARMCC::GE; break; 6331 case ISD::SETULT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1373 case ISD::SETULT: return SPCC::ICC_CS; 1397 case ISD::SETULT: return SPCC::FCC_UL;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1540 case ISD::SETULT: 1594 case ISD::SETULT: 1659 case ISD::SETULT: 2096 case ISD::SETULT: 2101 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2123 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 565 case ISD::SETULT:
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