/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1043 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 1059 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator in enum:llvm::ISD::CondCode 1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 213 case FCmpInst::FCMP_UGT: return ISD::SETUGT; 229 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; 249 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 3056 case ISD::SETUGT: 3229 case ISD::SETUGT: 3385 case ISD::SETUGT: 3548 case ISD::SETUGT: 3810 case ISD::SETUGT: 3837 case ISD::SETUGT: 3886 case ISD::SETUGT: return PPC::PRED_GT; 3918 case ISD::SETUGT: return 1; 3938 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; 3982 case ISD::SETULT: CC = ISD::SETUGT; Swa [all...] |
H A D | PPCISelLowering.cpp | 517 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 518 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 940 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand); 7649 case ISD::SETUGT: 7688 case ISD::SETUGT: 8167 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT); 12349 case ISD::SETUGT: 15903 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 381 case ISD::SETUGT: 2945 } else if (Cond == ISD::CondCode::SETUGT) { 3189 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 3370 case ISD::SETUGT: 3395 case ISD::SETUGT: 3579 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 3629 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { 3659 // SETUGT X, SINTMAX -> SETLT X, 0 3660 if (Cond == ISD::SETUGT && 3734 Cond == ISD::SETULE || Cond == ISD::SETUGT) { [all...] |
H A D | SelectionDAGDumper.cpp | 418 case ISD::SETUGT: return "setugt";
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H A D | LegalizeIntegerTypes.cpp | 1392 case ISD::SETUGT: 2223 return std::make_pair(ISD::SETUGT, ISD::UMAX); 2456 Cond = ISD::SETUGT; 3199 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT); 3860 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3928 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
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H A D | LegalizeDAG.cpp | 1692 case ISD::SETUGT: 3177 case ISD::UMAX: Pred = ISD::SETUGT; break; 3456 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
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H A D | SelectionDAG.cpp | 395 case ISD::SETUGT: 415 if (IsInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 435 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 439 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 2062 case ISD::SETUGT: return getBoolConstant(C1.ugt(C2), dl, VT, OpVT); 2124 case ISD::SETUGT: return getBoolConstant(R==APFloat::cmpGreaterThan ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertSkips.cpp | 228 case ISD::SETUGT:
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H A D | AMDGPUISelLowering.cpp | 1306 case ISD::SETUGT: { 2460 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
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H A D | R600ISelLowering.cpp | 135 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 688 SET_NEWCC(SETUGT, JUGT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 45 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 266 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 271 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 367 setCondCodeAction(ISD::SETUGT, Ty, Expand); 403 setCondCodeAction(ISD::SETUGT, Ty, Expand); 962 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 806 // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h) 820 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 159 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, 361 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 1080 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 520 case ISD::SETUGT: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 898 PickHi = DAG.getSetCC(dl, MVT::i1, IdxV, HalfV, ISD::SETUGT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 90 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1375 case ISD::SETUGT: return SPCC::ICC_GU; 1399 case ISD::SETUGT: return SPCC::FCC_UG;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1842 case ISD::SETUGT: return ARMCC::HI; 1867 case ISD::SETUGT: CondCode = ARMCC::HI; break; 4235 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 4247 case ISD::SETUGT: 4310 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) && 4657 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || 4676 CC == ISD::SETUGT) { 6289 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH; 6332 case ISD::SETUGT: Opc = ARMCC::HI; break; 14335 (CC == ISD::SETUGT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1536 case ISD::SETUGT: 1587 case ISD::SETUGT: 1661 case ISD::SETUGT: 2101 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2118 case ISD::SETUGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 561 case ISD::SETUGT:
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