Searched refs:SETEQ (Results 1 - 25 of 37) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp311 case ISD::SETEQ:
2856 (Cond != ISD::SETEQ && Cond != ISD::SETNE))
2940 NewCond = ISD::CondCode::SETEQ;
2942 NewCond = ISD::CondCode::SETEQ;
3009 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3082 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode");
3159 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3161 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3168 Cond = ISD::SETEQ;
3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ
[all...]
H A DLegalizeIntegerTypes.cpp1368 case ISD::SETEQ:
1878 N->getOperand(2), ISD::SETEQ);
2160 ISD::SETEQ);
2253 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
3198 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3204 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3211 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3217 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3283 ISD::SETEQ : ISD::SETNE);
3823 if (CCCode == ISD::SETEQ || CCCod
[all...]
H A DSelectionDAGDumper.cpp424 case ISD::SETEQ: return "seteq";
H A DSelectionDAGBuilder.cpp2094 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2244 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2331 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2366 CB.CC == ISD::SETEQ)
2369 CB.CC == ISD::SETEQ) {
2729 ISD::SETEQ);
6403 SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
10140 ISD::SETEQ);
10304 CC = ISD::SETEQ;
H A DLegalizeDAG.cpp1712 case ISD::SETEQ:
2852 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
3470 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3471 : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
H A DDAGCombiner.cpp2031 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
3765 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3858 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
3859 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
3908 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4005 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4562 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4581 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4619 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4629 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1042 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1067 SETEQ, // 1 X 0 0 1 True if equal enumerator in enum:llvm::ISD::CondCode
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2917 case ISD::SETEQ: {
3091 case ISD::SETEQ: {
3262 case ISD::SETEQ: {
3419 case ISD::SETEQ: {
3702 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3704 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3746 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3748 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3794 case ISD::SETEQ:
3821 case ISD::SETEQ
[all...]
H A DPPCISelLowering.cpp3047 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3082 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7632 case ISD::SETEQ:
7667 case ISD::SETEQ:
8725 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
12929 if (CC == ISD::SETNE || CC == ISD::SETEQ) {
14356 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
14360 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
14377 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
14385 if (CC == ISD::SETEQ) // Con
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1272 case ISD::SETEQ:
1754 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1776 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1810 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1814 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1884 ISD::SETEQ);
1898 ISD::SETEQ);
1935 Quotient, Quotient_A_One, ISD::SETEQ);
1939 Quotient_S_One, Div, ISD::SETEQ);
1951 Remainder, Remainder_S_Den, ISD::SETEQ);
[all...]
H A DSIInsertSkips.cpp196 case ISD::SETEQ:
H A DR600ISelLowering.cpp890 DAG.getCondCode(ISD::SETEQ));
900 DAG.getCondCode(ISD::SETEQ));
1989 case ISD::SETEQ: {
H A DSIISelLowering.cpp6099 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
7861 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
7862 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
9355 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ);
9427 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ);
9848 (CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
9852 (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
9859 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9873 if ((CF == CRHSVal && CC == ISD::SETEQ) ||
9878 (CT == CRHSVal && CC == ISD::SETEQ))
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp225 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ;
240 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
H A DTargetLoweringBase.cpp538 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
539 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
540 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
541 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
810 case ISD::SETEQ:
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1316 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1001 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1018 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1025 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1072 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
H A DX86ISelLowering.cpp4833 case ISD::SETEQ: return X86::COND_E;
4905 case ISD::SETEQ: return X86::COND_E;
9648 ISD::CondCode::SETEQ);
20670 X86CC = DAG.getTargetConstant(CC == ISD::SETEQ ? X86::COND_E : X86::COND_NE,
21146 X86CC = DAG.getTargetConstant(CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B,
21170 case ISD::SETEQ: SSECC = 0; break;
21197 case ISD::SETEQ:
21517 case ISD::SETEQ: CmpMode = 0x04; break;
21540 Cond = ISD::SETEQ;
21548 if (Cond == ISD::SETEQ
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp200 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
206 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
1052 case ISD::SETEQ:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp691 SET_NEWCC(SETEQ, JEQ);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp55 case ISD::SETEQ:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1526 case ISD::SETEQ:
1555 case ISD::SETEQ:
1688 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1692 (CC == ISD::SETEQ || CC == ISD::SETNE);
1822 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1823 // See emitComparison() on why we can only do this for SETEQ and SETNE.
2154 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
4978 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5004 if (CC == ISD::SETEQ) {
5464 if ((CC == ISD::SETEQ || C
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp954 case ISD::SETEQ:
1719 Op->getOperand(2), ISD::SETEQ);
1725 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp536 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
553 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
1837 case ISD::SETEQ: return ARMCC::EQ;
1855 case ISD::SETEQ:
3702 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3704 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
5177 CC = ISD::SETEQ;
5275 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5307 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
6245 (SetCCOpcode == ISD::SETEQ || SetCCOpcod
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp426 case ISD::SETEQ:

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