Searched refs:BRCOND (Results 1 - 25 of 28) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h698 /// BRCOND - Conditional branch. The first operand is the chain, the
702 BRCOND, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h52 BRCOND, enumerator in enum:llvm::AVRISD::NodeType
H A DAVRISelLowering.cpp100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
263 NODE(BRCOND);
630 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h42 BRCOND, // Conditional branch instruction; "b.cond".
H A DAArch64ISelLowering.cpp222 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1241 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
4992 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
5057 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
5071 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
5074 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
12593 case AArch64ISD::BRCOND:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp74 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h71 BRCOND, // Conditional branch.
H A DARMISelLowering.cpp753 setTargetDAGCombine(ISD::BRCOND);
1315 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1554 case ARMISD::BRCOND: return "ARMISD::BRCOND";
5190 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5240 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5294 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5302 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5321 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5325 Res = DAG.getNode(ARMISD::BRCOND, d
[all...]
H A DARMISelDAGToDAG.cpp3500 case ARMISD::BRCOND: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp358 case ISD::BRCOND: return "brcond";
H A DSelectionDAGBuilder.cpp2420 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2483 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2611 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2699 Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp,
2758 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
10156 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
H A DDAGCombiner.cpp1601 case ISD::BRCOND: return visitBRCOND(N);
8107 // itself may not be optimized further. Look for it and add the BRCOND into
8111 if (Use->getOpcode() == ISD::BRCOND)
8116 if (Use->getOpcode() == ISD::BRCOND)
9038 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND;
13550 return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, NewN1, N2);
H A DLegalizeDAG.cpp3576 case ISD::BRCOND:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h114 BRCOND,
H A DX86ISelLowering.cpp311 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
20687 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
22907 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22938 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain,
22983 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
22999 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
23030 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp237 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
4038 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4456 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, argument
4458 SDLoc DL(BRCOND);
4460 SDNode *Intr = BRCOND.getOperand(1).getNode();
4461 SDValue Target = BRCOND.getOperand(2);
4472 BR = findUser(BRCOND, ISD::BR);
4486 return BRCOND;
4500 Ops.push_back(BRCOND.getOperand(0));
4513 BRCOND
[all...]
H A DAMDGPUISelDAGToDAG.cpp901 case ISD::BRCOND:
2030 assert(N->getOpcode() == ISD::BRCOND);
H A DR600ISelLowering.cpp152 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
499 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp92 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp356 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1222 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
H A DMipsSEISelLowering.cpp260 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1534 // Sparc doesn't have BRCOND either, it has BR_CC.
1535 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp385 // PowerPC does not have BRCOND which requires SetCC
387 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1180 setTargetDAGCombine(ISD::BRCOND);
14315 case ISD::BRCOND: {

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