/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 698 /// BRCOND - Conditional branch. The first operand is the chain, the 702 BRCOND, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.h | 52 BRCOND, enumerator in enum:llvm::AVRISD::NodeType
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H A D | AVRISelLowering.cpp | 100 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 263 NODE(BRCOND); 630 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 42 BRCOND, // Conditional branch instruction; "b.cond".
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H A D | AArch64ISelLowering.cpp | 222 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1241 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND"; 4992 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, 5057 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, 5071 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); 5074 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, 12593 case AArch64ISD::BRCOND:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 74 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 71 BRCOND, // Conditional branch.
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H A D | ARMISelLowering.cpp | 753 setTargetDAGCombine(ISD::BRCOND); 1315 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 1554 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 5190 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 5240 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, 5294 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, 5302 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 5321 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); 5325 Res = DAG.getNode(ARMISD::BRCOND, d [all...] |
H A D | ARMISelDAGToDAG.cpp | 3500 case ARMISD::BRCOND: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 358 case ISD::BRCOND: return "brcond";
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H A D | SelectionDAGBuilder.cpp | 2420 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2483 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2611 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2699 Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp, 2758 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, 10156 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
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H A D | DAGCombiner.cpp | 1601 case ISD::BRCOND: return visitBRCOND(N); 8107 // itself may not be optimized further. Look for it and add the BRCOND into 8111 if (Use->getOpcode() == ISD::BRCOND) 8116 if (Use->getOpcode() == ISD::BRCOND) 9038 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; 13550 return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, NewN1, N2);
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H A D | LegalizeDAG.cpp | 3576 case ISD::BRCOND:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 114 BRCOND,
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H A D | X86ISelLowering.cpp | 311 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 20687 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && 22907 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 22938 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain, 22983 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 22999 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 23030 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 237 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 4038 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 4456 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, argument 4458 SDLoc DL(BRCOND); 4460 SDNode *Intr = BRCOND.getOperand(1).getNode(); 4461 SDValue Target = BRCOND.getOperand(2); 4472 BR = findUser(BRCOND, ISD::BR); 4486 return BRCOND; 4500 Ops.push_back(BRCOND.getOperand(0)); 4513 BRCOND [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 901 case ISD::BRCOND: 2030 assert(N->getOpcode() == ISD::BRCOND);
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H A D | R600ISelLowering.cpp | 152 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 499 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 92 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 356 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 1222 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
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H A D | MipsSEISelLowering.cpp | 260 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1534 // Sparc doesn't have BRCOND either, it has BR_CC. 1535 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 385 // PowerPC does not have BRCOND which requires SetCC 387 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1180 setTargetDAGCombine(ISD::BRCOND); 14315 case ISD::BRCOND: {
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