1//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the interfaces that ARM uses to lower LLVM code into a 10// selection DAG. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17#include "MCTargetDesc/ARMBaseInfo.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/ADT/StringRef.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/ISDOpcodes.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/SelectionDAGNodes.h" 24#include "llvm/CodeGen/TargetLowering.h" 25#include "llvm/CodeGen/ValueTypes.h" 26#include "llvm/IR/Attributes.h" 27#include "llvm/IR/CallingConv.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/IRBuilder.h" 30#include "llvm/IR/InlineAsm.h" 31#include "llvm/Support/CodeGen.h" 32#include "llvm/Support/MachineValueType.h" 33#include <utility> 34 35namespace llvm { 36 37class ARMSubtarget; 38class DataLayout; 39class FastISel; 40class FunctionLoweringInfo; 41class GlobalValue; 42class InstrItineraryData; 43class Instruction; 44class MachineBasicBlock; 45class MachineInstr; 46class SelectionDAG; 47class TargetLibraryInfo; 48class TargetMachine; 49class TargetRegisterInfo; 50class VectorType; 51 52 namespace ARMISD { 53 54 // ARM Specific DAG Nodes 55 enum NodeType : unsigned { 56 // Start the numbering where the builtin ops and target ops leave off. 57 FIRST_NUMBER = ISD::BUILTIN_OP_END, 58 59 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 60 // TargetExternalSymbol, and TargetGlobalAddress. 61 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 62 // PIC mode. 63 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 64 65 // Add pseudo op to model memcpy for struct byval. 66 COPY_STRUCT_BYVAL, 67 68 CALL, // Function call. 69 CALL_PRED, // Function call that's predicable. 70 CALL_NOLINK, // Function call with branch not branch-and-link. 71 BRCOND, // Conditional branch. 72 BR_JT, // Jumptable branch. 73 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 74 RET_FLAG, // Return with a flag operand. 75 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 76 77 PIC_ADD, // Add with a PC operand and a PIC label. 78 79 ASRL, // MVE long arithmetic shift right. 80 LSRL, // MVE long shift right. 81 LSLL, // MVE long shift left. 82 83 CMP, // ARM compare instructions. 84 CMN, // ARM CMN instructions. 85 CMPZ, // ARM compare that sets only Z flag. 86 CMPFP, // ARM VFP compare instruction, sets FPSCR. 87 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 88 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 89 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets FPSCR. 90 FMSTAT, // ARM fmstat instruction. 91 92 CMOV, // ARM conditional move instructions. 93 SUBS, // Flag-setting subtraction. 94 95 SSAT, // Signed saturation 96 USAT, // Unsigned saturation 97 98 BCC_i64, 99 100 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 101 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 102 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 103 104 ADDC, // Add with carry 105 ADDE, // Add using carry 106 SUBC, // Sub with carry 107 SUBE, // Sub using carry 108 LSLS, // Shift left producing carry 109 110 VMOVRRD, // double to two gprs. 111 VMOVDRR, // Two gprs to double. 112 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 113 114 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 115 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 116 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 117 118 TC_RETURN, // Tail call return pseudo. 119 120 THREAD_POINTER, 121 122 DYN_ALLOC, // Dynamic allocation on the stack. 123 124 MEMBARRIER_MCR, // Memory barrier (MCR) 125 126 PRELOAD, // Preload 127 128 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 129 WIN__DBZCHK, // Windows' divide by zero check 130 131 WLS, // Low-overhead loops, While Loop Start 132 LOOP_DEC, // Really a part of LE, performs the sub 133 LE, // Low-overhead loops, Loop End 134 135 PREDICATE_CAST, // Predicate cast for MVE i1 types 136 137 VCMP, // Vector compare. 138 VCMPZ, // Vector compare to zero. 139 VTST, // Vector test bits. 140 141 // Vector shift by vector 142 VSHLs, // ...left/right by signed 143 VSHLu, // ...left/right by unsigned 144 145 // Vector shift by immediate: 146 VSHLIMM, // ...left 147 VSHRsIMM, // ...right (signed) 148 VSHRuIMM, // ...right (unsigned) 149 150 // Vector rounding shift by immediate: 151 VRSHRsIMM, // ...right (signed) 152 VRSHRuIMM, // ...right (unsigned) 153 VRSHRNIMM, // ...right narrow 154 155 // Vector saturating shift by immediate: 156 VQSHLsIMM, // ...left (signed) 157 VQSHLuIMM, // ...left (unsigned) 158 VQSHLsuIMM, // ...left (signed to unsigned) 159 VQSHRNsIMM, // ...right narrow (signed) 160 VQSHRNuIMM, // ...right narrow (unsigned) 161 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 162 163 // Vector saturating rounding shift by immediate: 164 VQRSHRNsIMM, // ...right narrow (signed) 165 VQRSHRNuIMM, // ...right narrow (unsigned) 166 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 167 168 // Vector shift and insert: 169 VSLIIMM, // ...left 170 VSRIIMM, // ...right 171 172 // Vector get lane (VMOV scalar to ARM core register) 173 // (These are used for 8- and 16-bit element types only.) 174 VGETLANEu, // zero-extend vector extract element 175 VGETLANEs, // sign-extend vector extract element 176 177 // Vector move immediate and move negated immediate: 178 VMOVIMM, 179 VMVNIMM, 180 181 // Vector move f32 immediate: 182 VMOVFPIMM, 183 184 // Move H <-> R, clearing top 16 bits 185 VMOVrh, 186 VMOVhr, 187 188 // Vector duplicate: 189 VDUP, 190 VDUPLANE, 191 192 // Vector shuffles: 193 VEXT, // extract 194 VREV64, // reverse elements within 64-bit doublewords 195 VREV32, // reverse elements within 32-bit words 196 VREV16, // reverse elements within 16-bit halfwords 197 VZIP, // zip (interleave) 198 VUZP, // unzip (deinterleave) 199 VTRN, // transpose 200 VTBL1, // 1-register shuffle with mask 201 VTBL2, // 2-register shuffle with mask 202 VMOVN, // MVE vmovn 203 204 // Vector multiply long: 205 VMULLs, // ...signed 206 VMULLu, // ...unsigned 207 208 SMULWB, // Signed multiply word by half word, bottom 209 SMULWT, // Signed multiply word by half word, top 210 UMLAL, // 64bit Unsigned Accumulate Multiply 211 SMLAL, // 64bit Signed Accumulate Multiply 212 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 213 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 214 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 215 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 216 SMLALTT, // 64-bit signed accumulate multiply top, top 16 217 SMLALD, // Signed multiply accumulate long dual 218 SMLALDX, // Signed multiply accumulate long dual exchange 219 SMLSLD, // Signed multiply subtract long dual 220 SMLSLDX, // Signed multiply subtract long dual exchange 221 SMMLAR, // Signed multiply long, round and add 222 SMMLSR, // Signed multiply long, subtract and round 223 224 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b stands for. 225 QADD8b, 226 QSUB8b, 227 QADD16b, 228 QSUB16b, 229 230 // Operands of the standard BUILD_VECTOR node are not legalized, which 231 // is fine if BUILD_VECTORs are always lowered to shuffles or other 232 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 233 // operands need to be legalized. Define an ARM-specific version of 234 // BUILD_VECTOR for this purpose. 235 BUILD_VECTOR, 236 237 // Bit-field insert 238 BFI, 239 240 // Vector OR with immediate 241 VORRIMM, 242 // Vector AND with NOT of immediate 243 VBICIMM, 244 245 // Vector bitwise select 246 VBSL, 247 248 // Pseudo-instruction representing a memory copy using ldm/stm 249 // instructions. 250 MEMCPY, 251 252 // V8.1MMainline condition select 253 CSINV, // Conditional select invert. 254 CSNEG, // Conditional select negate. 255 CSINC, // Conditional select increment. 256 257 // Vector load N-element structure to all lanes: 258 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 259 VLD2DUP, 260 VLD3DUP, 261 VLD4DUP, 262 263 // NEON loads with post-increment base updates: 264 VLD1_UPD, 265 VLD2_UPD, 266 VLD3_UPD, 267 VLD4_UPD, 268 VLD2LN_UPD, 269 VLD3LN_UPD, 270 VLD4LN_UPD, 271 VLD1DUP_UPD, 272 VLD2DUP_UPD, 273 VLD3DUP_UPD, 274 VLD4DUP_UPD, 275 276 // NEON stores with post-increment base updates: 277 VST1_UPD, 278 VST2_UPD, 279 VST3_UPD, 280 VST4_UPD, 281 VST2LN_UPD, 282 VST3LN_UPD, 283 VST4LN_UPD 284 }; 285 286 } // end namespace ARMISD 287 288 /// Define some predicates that are used for node matching. 289 namespace ARM { 290 291 bool isBitFieldInvertedMask(unsigned v); 292 293 } // end namespace ARM 294 295 //===--------------------------------------------------------------------===// 296 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 297 298 class ARMTargetLowering : public TargetLowering { 299 public: 300 explicit ARMTargetLowering(const TargetMachine &TM, 301 const ARMSubtarget &STI); 302 303 unsigned getJumpTableEncoding() const override; 304 bool useSoftFloat() const override; 305 306 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 307 308 /// ReplaceNodeResults - Replace the results of node with an illegal result 309 /// type with new values built out of custom code. 310 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 311 SelectionDAG &DAG) const override; 312 313 const char *getTargetNodeName(unsigned Opcode) const override; 314 315 bool isSelectSupported(SelectSupportKind Kind) const override { 316 // ARM does not support scalar condition selects on vectors. 317 return (Kind != ScalarCondVectorVal); 318 } 319 320 bool isReadOnly(const GlobalValue *GV) const; 321 322 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 323 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 324 EVT VT) const override; 325 326 MachineBasicBlock * 327 EmitInstrWithCustomInserter(MachineInstr &MI, 328 MachineBasicBlock *MBB) const override; 329 330 void AdjustInstrPostInstrSelection(MachineInstr &MI, 331 SDNode *Node) const override; 332 333 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 334 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 335 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 336 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 337 338 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 339 340 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 341 /// unaligned memory accesses of the specified type. Returns whether it 342 /// is "fast" by reference in the second argument. 343 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 344 unsigned Align, 345 MachineMemOperand::Flags Flags, 346 bool *Fast) const override; 347 348 EVT getOptimalMemOpType(uint64_t Size, 349 unsigned DstAlign, unsigned SrcAlign, 350 bool IsMemset, bool ZeroMemset, 351 bool MemcpyStrSrc, 352 const AttributeList &FuncAttributes) const override; 353 354 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 355 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 356 bool isZExtFree(SDValue Val, EVT VT2) const override; 357 bool shouldSinkOperands(Instruction *I, 358 SmallVectorImpl<Use *> &Ops) const override; 359 360 bool isFNegFree(EVT VT) const override; 361 362 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 363 364 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 365 366 367 /// isLegalAddressingMode - Return true if the addressing mode represented 368 /// by AM is legal for this target, for a load/store of the specified type. 369 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 370 Type *Ty, unsigned AS, 371 Instruction *I = nullptr) const override; 372 373 /// getScalingFactorCost - Return the cost of the scaling used in 374 /// addressing mode represented by AM. 375 /// If the AM is supported, the return value must be >= 0. 376 /// If the AM is not supported, the return value must be negative. 377 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 378 unsigned AS) const override; 379 380 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 381 382 /// Returns true if the addressing mode representing by AM is legal 383 /// for the Thumb1 target, for a load/store of the specified type. 384 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 385 386 /// isLegalICmpImmediate - Return true if the specified immediate is legal 387 /// icmp immediate, that is the target has icmp instructions which can 388 /// compare a register against the immediate without having to materialize 389 /// the immediate into a register. 390 bool isLegalICmpImmediate(int64_t Imm) const override; 391 392 /// isLegalAddImmediate - Return true if the specified immediate is legal 393 /// add immediate, that is the target has add instructions which can 394 /// add a register and the immediate without having to materialize 395 /// the immediate into a register. 396 bool isLegalAddImmediate(int64_t Imm) const override; 397 398 /// getPreIndexedAddressParts - returns true by value, base pointer and 399 /// offset pointer and addressing mode by reference if the node's address 400 /// can be legally represented as pre-indexed load / store address. 401 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 402 ISD::MemIndexedMode &AM, 403 SelectionDAG &DAG) const override; 404 405 /// getPostIndexedAddressParts - returns true by value, base pointer and 406 /// offset pointer and addressing mode by reference if this node can be 407 /// combined with a load / store to form a post-indexed load / store. 408 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 409 SDValue &Offset, ISD::MemIndexedMode &AM, 410 SelectionDAG &DAG) const override; 411 412 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 413 const APInt &DemandedElts, 414 const SelectionDAG &DAG, 415 unsigned Depth) const override; 416 417 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, 418 TargetLoweringOpt &TLO) const override; 419 420 421 bool ExpandInlineAsm(CallInst *CI) const override; 422 423 ConstraintType getConstraintType(StringRef Constraint) const override; 424 425 /// Examine constraint string and operand type and determine a weight value. 426 /// The operand object must already have been set up with the operand type. 427 ConstraintWeight getSingleConstraintMatchWeight( 428 AsmOperandInfo &info, const char *constraint) const override; 429 430 std::pair<unsigned, const TargetRegisterClass *> 431 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 432 StringRef Constraint, MVT VT) const override; 433 434 const char *LowerXConstraint(EVT ConstraintVT) const override; 435 436 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 437 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 438 /// true it means one of the asm constraint of the inline asm instruction 439 /// being processed is 'm'. 440 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 441 std::vector<SDValue> &Ops, 442 SelectionDAG &DAG) const override; 443 444 unsigned 445 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 446 if (ConstraintCode == "Q") 447 return InlineAsm::Constraint_Q; 448 else if (ConstraintCode == "o") 449 return InlineAsm::Constraint_o; 450 else if (ConstraintCode.size() == 2) { 451 if (ConstraintCode[0] == 'U') { 452 switch(ConstraintCode[1]) { 453 default: 454 break; 455 case 'm': 456 return InlineAsm::Constraint_Um; 457 case 'n': 458 return InlineAsm::Constraint_Un; 459 case 'q': 460 return InlineAsm::Constraint_Uq; 461 case 's': 462 return InlineAsm::Constraint_Us; 463 case 't': 464 return InlineAsm::Constraint_Ut; 465 case 'v': 466 return InlineAsm::Constraint_Uv; 467 case 'y': 468 return InlineAsm::Constraint_Uy; 469 } 470 } 471 } 472 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 473 } 474 475 const ARMSubtarget* getSubtarget() const { 476 return Subtarget; 477 } 478 479 /// getRegClassFor - Return the register class that should be used for the 480 /// specified value type. 481 const TargetRegisterClass * 482 getRegClassFor(MVT VT, bool isDivergent = false) const override; 483 484 /// Returns true if a cast between SrcAS and DestAS is a noop. 485 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 486 // Addrspacecasts are always noops. 487 return true; 488 } 489 490 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 491 unsigned &PrefAlign) const override; 492 493 /// createFastISel - This method returns a target specific FastISel object, 494 /// or null if the target does not support "fast" ISel. 495 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 496 const TargetLibraryInfo *libInfo) const override; 497 498 Sched::Preference getSchedulingPreference(SDNode *N) const override; 499 500 bool 501 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 502 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 503 504 /// isFPImmLegal - Returns true if the target can instruction select the 505 /// specified FP immediate natively. If false, the legalizer will 506 /// materialize the FP immediate as a load from a constant pool. 507 bool isFPImmLegal(const APFloat &Imm, EVT VT, 508 bool ForCodeSize = false) const override; 509 510 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 511 const CallInst &I, 512 MachineFunction &MF, 513 unsigned Intrinsic) const override; 514 515 /// Returns true if it is beneficial to convert a load of a constant 516 /// to just the constant itself. 517 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 518 Type *Ty) const override; 519 520 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 521 /// with this index. 522 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 523 unsigned Index) const override; 524 525 /// Returns true if an argument of type Ty needs to be passed in a 526 /// contiguous block of registers in calling convention CallConv. 527 bool functionArgumentNeedsConsecutiveRegisters( 528 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; 529 530 /// If a physical register, this returns the register that receives the 531 /// exception address on entry to an EH pad. 532 unsigned 533 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 534 535 /// If a physical register, this returns the register that receives the 536 /// exception typeid on entry to a landing pad. 537 unsigned 538 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 539 540 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; 541 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 542 AtomicOrdering Ord) const override; 543 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 544 Value *Addr, AtomicOrdering Ord) const override; 545 546 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 547 548 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 549 AtomicOrdering Ord) const override; 550 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 551 AtomicOrdering Ord) const override; 552 553 unsigned getMaxSupportedInterleaveFactor() const override; 554 555 bool lowerInterleavedLoad(LoadInst *LI, 556 ArrayRef<ShuffleVectorInst *> Shuffles, 557 ArrayRef<unsigned> Indices, 558 unsigned Factor) const override; 559 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 560 unsigned Factor) const override; 561 562 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 563 TargetLoweringBase::AtomicExpansionKind 564 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 565 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 566 TargetLoweringBase::AtomicExpansionKind 567 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 568 TargetLoweringBase::AtomicExpansionKind 569 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 570 571 bool useLoadStackGuardNode() const override; 572 573 void insertSSPDeclarations(Module &M) const override; 574 Value *getSDagStackGuard(const Module &M) const override; 575 Function *getSSPStackGuardCheck(const Module &M) const override; 576 577 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 578 unsigned &Cost) const override; 579 580 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 581 const SelectionDAG &DAG) const override { 582 // Do not merge to larger than i32. 583 return (MemVT.getSizeInBits() <= 32); 584 } 585 586 bool isCheapToSpeculateCttz() const override; 587 bool isCheapToSpeculateCtlz() const override; 588 589 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 590 return VT.isScalarInteger(); 591 } 592 593 bool supportSwiftError() const override { 594 return true; 595 } 596 597 bool hasStandaloneRem(EVT VT) const override { 598 return HasStandaloneRem; 599 } 600 601 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; 602 603 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 604 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 605 606 /// Returns true if \p VecTy is a legal interleaved access type. This 607 /// function checks the vector element type and the overall width of the 608 /// vector. 609 bool isLegalInterleavedAccessType(unsigned Factor, VectorType *VecTy, 610 const DataLayout &DL) const; 611 612 bool alignLoopsWithOptSize() const override; 613 614 /// Returns the number of interleaved accesses that will be generated when 615 /// lowering accesses of the given type. 616 unsigned getNumInterleavedAccesses(VectorType *VecTy, 617 const DataLayout &DL) const; 618 619 void finalizeLowering(MachineFunction &MF) const override; 620 621 /// Return the correct alignment for the current calling convention. 622 Align getABIAlignmentForCallingConv(Type *ArgTy, 623 DataLayout DL) const override; 624 625 bool isDesirableToCommuteWithShift(const SDNode *N, 626 CombineLevel Level) const override; 627 628 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 629 CombineLevel Level) const override; 630 631 bool preferIncOfAddToSubOfNot(EVT VT) const override; 632 633 protected: 634 std::pair<const TargetRegisterClass *, uint8_t> 635 findRepresentativeClass(const TargetRegisterInfo *TRI, 636 MVT VT) const override; 637 638 private: 639 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 640 /// make the right decision when generating code for different targets. 641 const ARMSubtarget *Subtarget; 642 643 const TargetRegisterInfo *RegInfo; 644 645 const InstrItineraryData *Itins; 646 647 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 648 unsigned ARMPCLabelIndex; 649 650 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 651 // check. 652 bool InsertFencesForAtomic; 653 654 bool HasStandaloneRem = true; 655 656 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 657 void addDRTypeForNEON(MVT VT); 658 void addQRTypeForNEON(MVT VT); 659 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 660 661 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 662 663 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 664 SDValue &Arg, RegsToPassVector &RegsToPass, 665 CCValAssign &VA, CCValAssign &NextVA, 666 SDValue &StackPtr, 667 SmallVectorImpl<SDValue> &MemOpChains, 668 ISD::ArgFlagsTy Flags) const; 669 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 670 SDValue &Root, SelectionDAG &DAG, 671 const SDLoc &dl) const; 672 673 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 674 bool isVarArg) const; 675 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 676 bool isVarArg) const; 677 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 678 const SDLoc &dl, SelectionDAG &DAG, 679 const CCValAssign &VA, 680 ISD::ArgFlagsTy Flags) const; 681 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 682 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 683 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 684 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 685 const ARMSubtarget *Subtarget) const; 686 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 687 const ARMSubtarget *Subtarget) const; 688 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 689 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 690 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 691 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 692 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 693 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 694 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 695 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 696 SelectionDAG &DAG) const; 697 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 698 SelectionDAG &DAG, 699 TLSModel::Model model) const; 700 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 701 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 702 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 703 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 704 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 705 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 706 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 707 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 708 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 709 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 710 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 711 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 712 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 713 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 714 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 715 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 716 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 717 const ARMSubtarget *ST) const; 718 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 719 const ARMSubtarget *ST) const; 720 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 721 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 722 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 723 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 724 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 725 SmallVectorImpl<SDValue> &Results) const; 726 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 727 SDValue &Chain) const; 728 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 729 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 730 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 731 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 732 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 733 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 734 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 735 void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, 736 SelectionDAG &DAG) const; 737 738 Register getRegisterByName(const char* RegName, LLT VT, 739 const MachineFunction &MF) const override; 740 741 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 742 SmallVectorImpl<SDNode *> &Created) const override; 743 744 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 745 EVT VT) const override; 746 747 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 748 749 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 750 CallingConv::ID CallConv, bool isVarArg, 751 const SmallVectorImpl<ISD::InputArg> &Ins, 752 const SDLoc &dl, SelectionDAG &DAG, 753 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 754 SDValue ThisVal) const; 755 756 bool supportSplitCSR(MachineFunction *MF) const override { 757 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 758 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 759 } 760 761 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 762 void insertCopiesSplitCSR( 763 MachineBasicBlock *Entry, 764 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 765 766 SDValue 767 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 768 const SmallVectorImpl<ISD::InputArg> &Ins, 769 const SDLoc &dl, SelectionDAG &DAG, 770 SmallVectorImpl<SDValue> &InVals) const override; 771 772 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 773 SDValue &Chain, const Value *OrigArg, 774 unsigned InRegsParamRecordIdx, int ArgOffset, 775 unsigned ArgSize) const; 776 777 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 778 const SDLoc &dl, SDValue &Chain, 779 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 780 bool ForceMutable = false) const; 781 782 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 783 SmallVectorImpl<SDValue> &InVals) const override; 784 785 /// HandleByVal - Target-specific cleanup for ByVal support. 786 void HandleByVal(CCState *, unsigned &, unsigned) const override; 787 788 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 789 /// for tail call optimization. Targets which want to do tail call 790 /// optimization should implement this function. 791 bool IsEligibleForTailCallOptimization( 792 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 793 bool isCalleeStructRet, bool isCallerStructRet, 794 const SmallVectorImpl<ISD::OutputArg> &Outs, 795 const SmallVectorImpl<SDValue> &OutVals, 796 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, 797 const bool isIndirect) const; 798 799 bool CanLowerReturn(CallingConv::ID CallConv, 800 MachineFunction &MF, bool isVarArg, 801 const SmallVectorImpl<ISD::OutputArg> &Outs, 802 LLVMContext &Context) const override; 803 804 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 805 const SmallVectorImpl<ISD::OutputArg> &Outs, 806 const SmallVectorImpl<SDValue> &OutVals, 807 const SDLoc &dl, SelectionDAG &DAG) const override; 808 809 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 810 811 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 812 813 bool shouldConsiderGEPOffsetSplit() const override { return true; } 814 815 bool isUnsupportedFloatingType(EVT VT) const; 816 817 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 818 SDValue ARMcc, SDValue CCR, SDValue Cmp, 819 SelectionDAG &DAG) const; 820 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 821 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 822 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 823 const SDLoc &dl, bool Signaling = false) const; 824 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 825 826 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 827 828 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 829 MachineBasicBlock *DispatchBB, int FI) const; 830 831 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 832 833 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 834 835 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 836 MachineBasicBlock *MBB) const; 837 838 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 839 MachineBasicBlock *MBB) const; 840 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 841 MachineBasicBlock *MBB) const; 842 void addMVEVectorTypes(bool HasMVEFP); 843 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 844 void setAllExpand(MVT VT); 845 }; 846 847 enum VMOVModImmType { 848 VMOVModImm, 849 VMVNModImm, 850 MVEVMVNModImm, 851 OtherModImm 852 }; 853 854 namespace ARM { 855 856 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 857 const TargetLibraryInfo *libInfo); 858 859 } // end namespace ARM 860 861} // end namespace llvm 862 863#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 864