Searched refs:ARM (Results 1 - 25 of 121) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC:
29 case ARM::tADDi3:
30 case ARM::tADDi8:
31 case ARM::tADDrr:
32 case ARM::tAND:
33 case ARM::tASRri:
34 case ARM
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H A DARMInstrInfo.cpp1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
9 // This file contains the ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
37 NopInst.setOpcode(ARM::HINT);
42 NopInst.setOpcode(ARM::MOVr);
43 NopInst.addOperand(MCOperand::createReg(ARM::R0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
55 case ARM::LDR_PRE_IMM:
56 case ARM::LDR_PRE_REG:
57 case ARM
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H A DARMTargetTransformInfo.h1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
11 /// ARM target machine. It uses the target's detailed information to
20 #include "ARM.h"
55 // fail if the callee uses ARM only instructions, e.g. in inline asm.
57 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
58 ARM::FeatureFP16, ARM
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H A DARMExpandPseudoInsts.cpp16 #include "ARM.h"
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM
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H A DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
75 cl::desc("Enable ARM 2-addr to 3-addr conv"));
89 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91 { ARM
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H A DThumb2SizeReduction.cpp9 #include "ARM.h"
83 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM
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H A DARMRegisterBankInfo.cpp9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM { namespace in namespace:llvm
138 // (ARM::RegBanks) is unique in the compiler. At some point, it
144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
146 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
157 assert(RBGPR.covers(*TRI.getRegClass(ARM
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H A DARMBaseInstrInfo.h1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
481 return MachineOperand::CreateReg(ARM::CPSR,
488 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
513 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
514 Opc == ARM::MVE_VPTv16s8 || Opc == ARM
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H A DThumb2InstrInfo.cpp46 NopInst.setOpcode(ARM::tHINT);
88 if (MBBI->getOpcode() == ARM::t2IT) {
126 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
148 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
149 BuildMI(MBB, I, DL, get(ARM::t2STRi12))
158 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
164 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
168 AddDReg(MIB, SrcReg, ARM
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H A DARMCallingConv.cpp1 //=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===//
9 // This file contains the custom routines for the ARM Calling Convention that
14 #include "ARM.h"
24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
68 static const MCPhysReg LoRegList[] = { ARM
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H A DARMMacroFusion.cpp1 //===- ARMMacroFusion.cpp - ARM Macro Fusion ----------------------===//
9 /// \file This file contains the ARM implementation of the DAG scheduling
27 case ARM::AESMC :
28 return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESE;
30 case ARM::AESIMC:
31 return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESD;
41 if ((FirstMI == nullptr || FirstMI->getOpcode() == ARM::MOVi16) &&
42 SecondMI.getOpcode() == ARM::MOVTi16)
H A DARMLoadStoreOptimizer.cpp1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
14 #include "ARM.h"
91 cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
93 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
218 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
222 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
223 Opcode == ARM
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H A DThumb1FrameLowering.cpp57 // stack frame. ARM (especially Thumb) has small immediate offset to
79 if (ScratchReg == ARM::NoRegister)
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM
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H A DARMFrameLowering.cpp1 //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
9 // This file contains the ARM implementation of TargetFrameLowering class.
72 cl::desc("Align ARM NEON spills in prolog and epilog"));
127 // stack frame. ARM (especially Thumb) has small immediate offset to
156 if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
157 MI.getOpcode() == ARM::LDR_POST_REG ||
158 MI.getOpcode() == ARM::t2LDR_POST) &&
160 MI.getOperand(1).getReg() == ARM::SP)
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM
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H A DARMISelDAGToDAG.cpp1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
9 // This file defines an instruction selector for the ARM target.
13 #include "ARM.h"
48 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
69 StringRef getPassName() const override { return "ARM Instruction Selection"; }
108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
187 /// Indexed (pre/post inc/dec) load matching code for ARM.
277 /// Try to select SBFX/UBFX instructions for ARM.
457 /// least on current ARM implementation
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H A DARMAsmPrinter.cpp1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
15 #include "ARM.h"
174 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
209 if(ARM::GPRPairRegClass.contains(Reg)) {
212 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
283 if (!ARM::DPRRegClass.contains(*SR))
285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
310 if (ARM::GPRPairRegClass.contains(RegBegin)) {
312 Register Reg0 = TRI->getSubReg(RegBegin, ARM
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H A DThumb1InstrInfo.cpp27 NopInst.setOpcode(ARM::tMOVr);
28 NopInst.addOperand(MCOperand::createReg(ARM::R8));
29 NopInst.addOperand(MCOperand::createReg(ARM::R8));
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
49 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
50 || !ARM::tGPRRegClass.contains(DestReg))
51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
63 ->addRegisterDead(ARM
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp110 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {}
112 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {}
123 if (STI.hasFeature(ARM::HasV8Ops)) {
124 if (STI.hasFeature(ARM::FeatureRClass))
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps))
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps))
131 else if (STI.hasFeature(ARM::HasV7Ops)) {
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
135 } else if (STI.hasFeature(ARM
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H A DARMAsmBackend.cpp1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
60 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
114 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
193 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
194 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
199 case ARM::tBcc:
200 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
201 case ARM::tLDRpci:
202 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
203 case ARM
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H A DARMUnwindOpAsm.cpp1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
9 // This file implements the unwind opcode assembler for ARM exception handling
52 assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX &&
54 EmitByte(ARM::EHABI::EHT_COMPACT | PI);
60 EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH);
85 EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
89 EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
96 EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
100 EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
115 ? ARM
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H A DARMWinCOFFObjectWriter.cpp1 //===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==//
74 case ARM::fixup_t2_condbranch:
76 case ARM::fixup_t2_uncondbranch:
77 case ARM::fixup_arm_thumb_bl:
79 case ARM::fixup_arm_thumb_blx:
81 case ARM::fixup_t2_movw_lo16:
82 case ARM::fixup_t2_movt_hi16:
88 return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
H A DARMELFObjectWriter.cpp1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
102 case ARM::fixup_arm_blx:
103 case ARM::fixup_arm_uncondbl:
112 case ARM::fixup_arm_condbl:
113 case ARM::fixup_arm_condbranch:
114 case ARM::fixup_arm_uncondbranch:
116 case ARM::fixup_t2_condbranch:
118 case ARM::fixup_t2_uncondbranch:
120 case ARM::fixup_arm_movt_hi16:
122 case ARM
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
129 /// ARM disassembler for all ARM platforms.
586 case ARM::HVC: {
596 case ARM::t2ADDri:
597 case ARM::t2ADDri12:
598 case ARM::t2ADDrr:
599 case ARM::t2ADDrs:
600 case ARM::t2SUBri:
601 case ARM
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/
H A DARMTargetParser.cpp1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
9 // This file implements a target parser to recognise ARM hardware features
27 ARM::ArchKind ARM::parseArch(StringRef Arch) {
38 unsigned ARM::parseArchVersion(StringRef Arch) {
89 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
135 StringRef ARM::getArchSynonym(StringRef Arch) {
160 bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
224 ARM
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
87 "Warn in ARM, reject in Thumb"),
89 "Accept in ARM, reject in Thumb"),
91 "Warn in ARM, emit implicit ITs in Thumb")));
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
179 FPReg = ARM::SP;
245 ITInst.setOpcode(ARM::t2IT);
302 return MRI->getSubReg(QReg, ARM::dsub_0);
449 return getSTI().getFeatureBits()[ARM::ModeThumb];
453 return isThumb() && !getSTI().getFeatureBits()[ARM
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