1234353Sdim//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 2195340Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6195340Sed// 7195340Sed//===----------------------------------------------------------------------===// 8195340Sed// 9195340Sed// This file contains the Thumb-1 implementation of the TargetInstrInfo class. 10195340Sed// 11195340Sed//===----------------------------------------------------------------------===// 12195340Sed 13321369Sdim#include "Thumb1InstrInfo.h" 14280031Sdim#include "ARMSubtarget.h" 15195340Sed#include "llvm/CodeGen/MachineFrameInfo.h" 16195340Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 17249423Sdim#include "llvm/CodeGen/MachineMemOperand.h" 18234353Sdim#include "llvm/MC/MCInst.h" 19195340Sed 20195340Sedusing namespace llvm; 21195340Sed 22198892SrdivackyThumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 23288943Sdim : ARMBaseInstrInfo(STI), RI() {} 24195340Sed 25321369Sdim/// Return the noop instruction to use for a noop. 26321369Sdimvoid Thumb1InstrInfo::getNoop(MCInst &NopInst) const { 27234353Sdim NopInst.setOpcode(ARM::tMOVr); 28288943Sdim NopInst.addOperand(MCOperand::createReg(ARM::R8)); 29288943Sdim NopInst.addOperand(MCOperand::createReg(ARM::R8)); 30288943Sdim NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); 31288943Sdim NopInst.addOperand(MCOperand::createReg(0)); 32234353Sdim} 33234353Sdim 34198090Srdivackyunsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 35198090Srdivacky return 0; 36198090Srdivacky} 37195340Sed 38210299Sedvoid Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 39309124Sdim MachineBasicBlock::iterator I, 40360784Sdim const DebugLoc &DL, MCRegister DestReg, 41360784Sdim MCRegister SrcReg, bool KillSrc) const { 42280031Sdim // Need to check the arch. 43280031Sdim MachineFunction &MF = *MBB.getParent(); 44288943Sdim const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>(); 45280031Sdim 46210299Sed assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 47210299Sed "Thumb1 can only copy GPR registers"); 48280031Sdim 49280031Sdim if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) 50280031Sdim || !ARM::tGPRRegClass.contains(DestReg)) 51321369Sdim BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 52321369Sdim .addReg(SrcReg, getKillRegState(KillSrc)) 53321369Sdim .add(predOps(ARMCC::AL)); 54280031Sdim else { 55321369Sdim // FIXME: Can also use 'mov hi, $src; mov $dst, hi', 56321369Sdim // with hi as either r10 or r11. 57280031Sdim 58321369Sdim const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); 59321369Sdim if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) 60321369Sdim == MachineBasicBlock::LQR_Dead) { 61321369Sdim BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) 62321369Sdim .addReg(SrcReg, getKillRegState(KillSrc)) 63321369Sdim ->addRegisterDead(ARM::CPSR, RegInfo); 64321369Sdim return; 65321369Sdim } 66321369Sdim 67280031Sdim // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it 68321369Sdim BuildMI(MBB, I, DL, get(ARM::tPUSH)) 69321369Sdim .add(predOps(ARMCC::AL)) 70321369Sdim .addReg(SrcReg, getKillRegState(KillSrc)); 71321369Sdim BuildMI(MBB, I, DL, get(ARM::tPOP)) 72321369Sdim .add(predOps(ARMCC::AL)) 73321369Sdim .addReg(DestReg, getDefRegState(true)); 74280031Sdim } 75195340Sed} 76195340Sed 77195340Sedvoid Thumb1InstrInfo:: 78195340SedstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 79195340Sed unsigned SrcReg, bool isKill, int FI, 80208599Srdivacky const TargetRegisterClass *RC, 81208599Srdivacky const TargetRegisterInfo *TRI) const { 82239462Sdim assert((RC == &ARM::tGPRRegClass || 83360784Sdim (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && 84360784Sdim "Unknown regclass!"); 85195340Sed 86239462Sdim if (RC == &ARM::tGPRRegClass || 87360784Sdim (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { 88208599Srdivacky DebugLoc DL; 89208599Srdivacky if (I != MBB.end()) DL = I->getDebugLoc(); 90208599Srdivacky 91198892Srdivacky MachineFunction &MF = *MBB.getParent(); 92314564Sdim MachineFrameInfo &MFI = MF.getFrameInfo(); 93296417Sdim MachineMemOperand *MMO = MF.getMachineMemOperand( 94296417Sdim MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, 95296417Sdim MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 96321369Sdim BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 97321369Sdim .addReg(SrcReg, getKillRegState(isKill)) 98321369Sdim .addFrameIndex(FI) 99321369Sdim .addImm(0) 100321369Sdim .addMemOperand(MMO) 101321369Sdim .add(predOps(ARMCC::AL)); 102195340Sed } 103195340Sed} 104195340Sed 105195340Sedvoid Thumb1InstrInfo:: 106195340SedloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 107195340Sed unsigned DestReg, int FI, 108208599Srdivacky const TargetRegisterClass *RC, 109208599Srdivacky const TargetRegisterInfo *TRI) const { 110360784Sdim assert( 111360784Sdim (RC->hasSuperClassEq(&ARM::tGPRRegClass) || 112360784Sdim (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && 113360784Sdim "Unknown regclass!"); 114195340Sed 115341825Sdim if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || 116360784Sdim (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { 117208599Srdivacky DebugLoc DL; 118208599Srdivacky if (I != MBB.end()) DL = I->getDebugLoc(); 119208599Srdivacky 120198892Srdivacky MachineFunction &MF = *MBB.getParent(); 121314564Sdim MachineFrameInfo &MFI = MF.getFrameInfo(); 122296417Sdim MachineMemOperand *MMO = MF.getMachineMemOperand( 123296417Sdim MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, 124296417Sdim MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 125321369Sdim BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 126321369Sdim .addFrameIndex(FI) 127321369Sdim .addImm(0) 128321369Sdim .addMemOperand(MMO) 129321369Sdim .add(predOps(ARMCC::AL)); 130195340Sed } 131195340Sed} 132280031Sdim 133309124Sdimvoid Thumb1InstrInfo::expandLoadStackGuard( 134309124Sdim MachineBasicBlock::iterator MI) const { 135309124Sdim MachineFunction &MF = *MI->getParent()->getParent(); 136309124Sdim const TargetMachine &TM = MF.getTarget(); 137309124Sdim if (TM.isPositionIndependent()) 138309124Sdim expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi); 139280031Sdim else 140309124Sdim expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); 141280031Sdim} 142328817Sdim 143328817Sdimbool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const { 144328817Sdim // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR 145328817Sdim // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS 146328817Sdim // even if they have glue. 147328817Sdim // FIXME. Actually implement the cross-copy where it is possible (post v6) 148328817Sdim // because these copies entail more spilling. 149328817Sdim unsigned Opcode = N->getMachineOpcode(); 150328817Sdim if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS) 151328817Sdim return true; 152328817Sdim 153328817Sdim return false; 154328817Sdim} 155