Lines Matching refs:ARM
1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
9 // This file defines an instruction selector for the ARM target.
13 #include "ARM.h"
48 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
69 StringRef getPassName() const override { return "ARM Instruction Selection"; }
108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
187 /// Indexed (pre/post inc/dec) load matching code for ARM.
277 /// Try to select SBFX/UBFX instructions for ARM.
457 /// least on current ARM implementations) which should be avoidded.
479 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
1534 Opcode = ARM::LDR_PRE_IMM;
1538 Opcode = ARM::LDR_POST_IMM;
1542 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1549 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1550 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1555 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1561 Opcode = ARM::LDRB_PRE_IMM;
1565 Opcode = ARM::LDRB_POST_IMM;
1568 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1574 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1620 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32,
1642 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1646 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1648 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1653 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1655 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1731 Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post;
1733 Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post;
1737 Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post;
1739 Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post;
1743 Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post;
1745 Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post;
1750 Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post;
1755 Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post;
1758 Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post;
1779 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
1780 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
1781 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
1790 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32);
1791 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1792 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
1802 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1803 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1813 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1814 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1824 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32);
1825 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1826 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1827 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32);
1828 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32);
1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1840 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1841 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1842 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32);
1843 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
1855 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1857 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);
1858 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
1890 case ARM::VLD1d8wb_fixed : return true;
1891 case ARM::VLD1d16wb_fixed : return true;
1892 case ARM::VLD1d64Qwb_fixed : return true;
1893 case ARM::VLD1d32wb_fixed : return true;
1894 case ARM::VLD1d64wb_fixed : return true;
1895 case ARM::VLD1d64TPseudoWB_fixed : return true;
1896 case ARM::VLD1d64QPseudoWB_fixed : return true;
1897 case ARM::VLD1q8wb_fixed : return true;
1898 case ARM::VLD1q16wb_fixed : return true;
1899 case ARM::VLD1q32wb_fixed : return true;
1900 case ARM::VLD1q64wb_fixed : return true;
1901 case ARM::VLD1DUPd8wb_fixed : return true;
1902 case ARM::VLD1DUPd16wb_fixed : return true;
1903 case ARM::VLD1DUPd32wb_fixed : return true;
1904 case ARM::VLD1DUPq8wb_fixed : return true;
1905 case ARM::VLD1DUPq16wb_fixed : return true;
1906 case ARM::VLD1DUPq32wb_fixed : return true;
1907 case ARM::VLD2d8wb_fixed : return true;
1908 case ARM::VLD2d16wb_fixed : return true;
1909 case ARM::VLD2d32wb_fixed : return true;
1910 case ARM::VLD2q8PseudoWB_fixed : return true;
1911 case ARM::VLD2q16PseudoWB_fixed : return true;
1912 case ARM::VLD2q32PseudoWB_fixed : return true;
1913 case ARM::VLD2DUPd8wb_fixed : return true;
1914 case ARM::VLD2DUPd16wb_fixed : return true;
1915 case ARM::VLD2DUPd32wb_fixed : return true;
1923 case ARM::VST1d8wb_fixed : return true;
1924 case ARM::VST1d16wb_fixed : return true;
1925 case ARM::VST1d32wb_fixed : return true;
1926 case ARM::VST1d64wb_fixed : return true;
1927 case ARM::VST1q8wb_fixed : return true;
1928 case ARM::VST1q16wb_fixed : return true;
1929 case ARM::VST1q32wb_fixed : return true;
1930 case ARM::VST1q64wb_fixed : return true;
1931 case ARM::VST1d64TPseudoWB_fixed : return true;
1932 case ARM::VST1d64QPseudoWB_fixed : return true;
1933 case ARM::VST2d8wb_fixed : return true;
1934 case ARM::VST2d16wb_fixed : return true;
1935 case ARM::VST2d32wb_fixed : return true;
1936 case ARM::VST2q8PseudoWB_fixed : return true;
1937 case ARM::VST2q16PseudoWB_fixed : return true;
1938 case ARM::VST2q32PseudoWB_fixed : return true;
1949 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1950 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1951 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1952 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1953 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1954 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1955 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1956 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1957 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1958 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1959 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1960 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1961 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register;
1962 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register;
1963 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register;
1964 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register;
1965 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register;
1966 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register;
1968 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1969 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1970 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1971 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1972 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1973 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1974 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1975 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1976 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1977 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1979 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1980 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1981 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1982 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1983 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1984 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1986 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1987 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1988 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1989 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1990 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1991 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1993 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1994 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1995 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
2134 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
2135 ARM::qsub_3 == ARM::qsub_0 + 3,
2137 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
2412 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
2413 ARM::qsub_3 == ARM::qsub_0 + 3,
2415 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2682 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, Data));
2806 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");
2807 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2824 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2825 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2856 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2864 // ARM models shift instructions as MOVsi with shifter operand.
2871 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2963 /// ARM instruction selection detects the latter and matches it to
2964 /// ARM::ABS or ARM::t2ABS machine node.
2987 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
3000 Opcode = ARM::CMP_SWAP_8;
3002 Opcode = ARM::CMP_SWAP_16;
3004 Opcode = ARM::CMP_SWAP_32;
3064 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;
3070 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
3079 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
3083 NewN = EmitShift(ARM::tLSRri, X, Range->second);
3088 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
3095 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
3096 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),
3133 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP &&
3136 CurDAG->getRegister(ARM::SP, MVT::i32),
3142 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops);
3186 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
3196 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
3227 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
3232 ARM::t2ADDri : ARM::ADDri);
3265 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
3270 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
3284 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
3289 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
3326 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3329 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
3336 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
3351 ? ARM::t2MOVTi16
3352 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
3381 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL;
3395 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
3403 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl,
3414 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
3422 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl,
3451 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
3483 ARM::t2WhileLoopStart : ARM::t2LoopEnd;
3494 CurDAG->getMachineNode(ARM::t2LoopDec, dl,
3514 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
3540 CurDAG->getMachineNode(ARM::t2LoopDec, dl,
3547 CurDAG->getMachineNode(ARM::t2LoopEnd, dl, MVT::Other, EndArgs);
3609 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
3611 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8;
3612 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
3664 case MVT::v8i8: Opc = ARM::VZIPd8; break;
3666 case MVT::v4i16: Opc = ARM::VZIPd16; break;
3669 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3670 case MVT::v16i8: Opc = ARM::VZIPq8; break;
3672 case MVT::v8i16: Opc = ARM::VZIPq16; break;
3674 case MVT::v4i32: Opc = ARM::VZIPq32; break;
3687 case MVT::v8i8: Opc = ARM::VUZPd8; break;
3689 case MVT::v4i16: Opc = ARM::VUZPd16; break;
3692 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3693 case MVT::v16i8: Opc = ARM::VUZPq8; break;
3695 case MVT::v8i16: Opc = ARM::VUZPq16; break;
3697 case MVT::v4i32: Opc = ARM::VUZPq32; break;
3710 case MVT::v8i8: Opc = ARM::VTRNd8; break;
3712 case MVT::v4i16: Opc = ARM::VTRNd16; break;
3714 case MVT::v2i32: Opc = ARM::VTRNd32; break;
3715 case MVT::v16i8: Opc = ARM::VTRNq8; break;
3717 case MVT::v8i16: Opc = ARM::VTRNq16; break;
3719 case MVT::v4i32: Opc = ARM::VTRNq32; break;
3751 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16,
3752 ARM::VLD1DUPd32 };
3753 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16,
3754 ARM::VLD1DUPq32 };
3760 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
3761 ARM::VLD2DUPd32 };
3767 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
3768 ARM::VLD3DUPd16Pseudo,
3769 ARM::VLD3DUPd32Pseudo };
3775 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
3776 ARM::VLD4DUPd16Pseudo,
3777 ARM::VLD4DUPd32Pseudo };
3783 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed,
3784 ARM::VLD1DUPd16wb_fixed,
3785 ARM::VLD1DUPd32wb_fixed };
3786 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed,
3787 ARM::VLD1DUPq16wb_fixed,
3788 ARM::VLD1DUPq32wb_fixed };
3794 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
3795 ARM::VLD2DUPd16wb_fixed,
3796 ARM::VLD2DUPd32wb_fixed };
3802 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
3803 ARM::VLD3DUPd16Pseudo_UPD,
3804 ARM::VLD3DUPd32Pseudo_UPD };
3810 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
3811 ARM::VLD4DUPd16Pseudo_UPD,
3812 ARM::VLD4DUPd32Pseudo_UPD };
3818 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
3819 ARM::VLD1d16wb_fixed,
3820 ARM::VLD1d32wb_fixed,
3821 ARM::VLD1d64wb_fixed };
3822 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
3823 ARM::VLD1q16wb_fixed,
3824 ARM::VLD1q32wb_fixed,
3825 ARM::VLD1q64wb_fixed };
3831 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
3832 ARM::VLD2d16wb_fixed,
3833 ARM::VLD2d32wb_fixed,
3834 ARM::VLD1q64wb_fixed};
3835 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
3836 ARM::VLD2q16PseudoWB_fixed,
3837 ARM::VLD2q32PseudoWB_fixed };
3843 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
3844 ARM::VLD3d16Pseudo_UPD,
3845 ARM::VLD3d32Pseudo_UPD,
3846 ARM::VLD1d64TPseudoWB_fixed};
3847 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3848 ARM::VLD3q16Pseudo_UPD,
3849 ARM::VLD3q32Pseudo_UPD };
3850 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
3851 ARM::VLD3q16oddPseudo_UPD,
3852 ARM::VLD3q32oddPseudo_UPD };
3858 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
3859 ARM::VLD4d16Pseudo_UPD,
3860 ARM::VLD4d32Pseudo_UPD,
3861 ARM::VLD1d64QPseudoWB_fixed};
3862 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3863 ARM::VLD4q16Pseudo_UPD,
3864 ARM::VLD4q32Pseudo_UPD };
3865 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
3866 ARM::VLD4q16oddPseudo_UPD,
3867 ARM::VLD4q32oddPseudo_UPD };
3873 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
3874 ARM::VLD2LNd16Pseudo_UPD,
3875 ARM::VLD2LNd32Pseudo_UPD };
3876 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
3877 ARM::VLD2LNq32Pseudo_UPD };
3883 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
3884 ARM::VLD3LNd16Pseudo_UPD,
3885 ARM::VLD3LNd32Pseudo_UPD };
3886 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
3887 ARM::VLD3LNq32Pseudo_UPD };
3893 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
3894 ARM::VLD4LNd16Pseudo_UPD,
3895 ARM::VLD4LNd32Pseudo_UPD };
3896 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
3897 ARM::VLD4LNq32Pseudo_UPD };
3903 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
3904 ARM::VST1d16wb_fixed,
3905 ARM::VST1d32wb_fixed,
3906 ARM::VST1d64wb_fixed };
3907 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
3908 ARM::VST1q16wb_fixed,
3909 ARM::VST1q32wb_fixed,
3910 ARM::VST1q64wb_fixed };
3916 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
3917 ARM::VST2d16wb_fixed,
3918 ARM::VST2d32wb_fixed,
3919 ARM::VST1q64wb_fixed};
3920 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
3921 ARM::VST2q16PseudoWB_fixed,
3922 ARM::VST2q32PseudoWB_fixed };
3928 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
3929 ARM::VST3d16Pseudo_UPD,
3930 ARM::VST3d32Pseudo_UPD,
3931 ARM::VST1d64TPseudoWB_fixed};
3932 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3933 ARM::VST3q16Pseudo_UPD,
3934 ARM::VST3q32Pseudo_UPD };
3935 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
3936 ARM::VST3q16oddPseudo_UPD,
3937 ARM::VST3q32oddPseudo_UPD };
3943 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
3944 ARM::VST4d16Pseudo_UPD,
3945 ARM::VST4d32Pseudo_UPD,
3946 ARM::VST1d64QPseudoWB_fixed};
3947 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3948 ARM::VST4q16Pseudo_UPD,
3949 ARM::VST4q32Pseudo_UPD };
3950 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
3951 ARM::VST4q16oddPseudo_UPD,
3952 ARM::VST4q32oddPseudo_UPD };
3958 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
3959 ARM::VST2LNd16Pseudo_UPD,
3960 ARM::VST2LNd32Pseudo_UPD };
3961 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3962 ARM::VST2LNq32Pseudo_UPD };
3968 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
3969 ARM::VST3LNd16Pseudo_UPD,
3970 ARM::VST3LNd32Pseudo_UPD };
3971 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3972 ARM::VST3LNq32Pseudo_UPD };
3978 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3979 ARM::VST4LNd16Pseudo_UPD,
3980 ARM::VST4LNd32Pseudo_UPD };
3981 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3982 ARM::VST4LNq32Pseudo_UPD };
4001 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2);
4003 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2);
4010 // The mrrc2 instruction in ARM doesn't allow predicates, the top 4 bits of the encoded
4013 if (Opc != ARM::MRRC2) {
4034 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
4035 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
4062 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
4075 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
4113 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
4114 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
4126 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
4127 ARM::VLD1d32, ARM::VLD1d64 };
4128 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
4129 ARM::VLD1q32, ARM::VLD1q64};
4135 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
4136 ARM::VLD1q32, ARM::VLD1q64 };
4137 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo,
4138 ARM::VLD1d16QPseudo,
4139 ARM::VLD1d32QPseudo,
4140 ARM::VLD1d64QPseudo };
4146 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo,
4147 ARM::VLD1d16TPseudo,
4148 ARM::VLD1d32TPseudo,
4149 ARM::VLD1d64TPseudo };
4150 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD,
4151 ARM::VLD1q16LowTPseudo_UPD,
4152 ARM::VLD1q32LowTPseudo_UPD,
4153 ARM::VLD1q64LowTPseudo_UPD };
4154 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo,
4155 ARM::VLD1q16HighTPseudo,
4156 ARM::VLD1q32HighTPseudo,
4157 ARM::VLD1q64HighTPseudo };
4163 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo,
4164 ARM::VLD1d16QPseudo,
4165 ARM::VLD1d32QPseudo,
4166 ARM::VLD1d64QPseudo };
4167 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD,
4168 ARM::VLD1q16LowQPseudo_UPD,
4169 ARM::VLD1q32LowQPseudo_UPD,
4170 ARM::VLD1q64LowQPseudo_UPD };
4171 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo,
4172 ARM::VLD1q16HighQPseudo,
4173 ARM::VLD1q32HighQPseudo,
4174 ARM::VLD1q64HighQPseudo };
4180 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
4181 ARM::VLD2d32, ARM::VLD1q64 };
4182 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
4183 ARM::VLD2q32Pseudo };
4189 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
4190 ARM::VLD3d16Pseudo,
4191 ARM::VLD3d32Pseudo,
4192 ARM::VLD1d64TPseudo };
4193 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
4194 ARM::VLD3q16Pseudo_UPD,
4195 ARM::VLD3q32Pseudo_UPD };
4196 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
4197 ARM::VLD3q16oddPseudo,
4198 ARM::VLD3q32oddPseudo };
4204 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
4205 ARM::VLD4d16Pseudo,
4206 ARM::VLD4d32Pseudo,
4207 ARM::VLD1d64QPseudo };
4208 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
4209 ARM::VLD4q16Pseudo_UPD,
4210 ARM::VLD4q32Pseudo_UPD };
4211 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
4212 ARM::VLD4q16oddPseudo,
4213 ARM::VLD4q32oddPseudo };
4219 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
4220 ARM::VLD2DUPd32, ARM::VLD1q64 };
4221 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo,
4222 ARM::VLD2DUPq16EvenPseudo,
4223 ARM::VLD2DUPq32EvenPseudo };
4224 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo,
4225 ARM::VLD2DUPq16OddPseudo,
4226 ARM::VLD2DUPq32OddPseudo };
4233 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo,
4234 ARM::VLD3DUPd16Pseudo,
4235 ARM::VLD3DUPd32Pseudo,
4236 ARM::VLD1d64TPseudo };
4237 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo,
4238 ARM::VLD3DUPq16EvenPseudo,
4239 ARM::VLD3DUPq32EvenPseudo };
4240 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo,
4241 ARM::VLD3DUPq16OddPseudo,
4242 ARM::VLD3DUPq32OddPseudo };
4249 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo,
4250 ARM::VLD4DUPd16Pseudo,
4251 ARM::VLD4DUPd32Pseudo,
4252 ARM::VLD1d64QPseudo };
4253 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo,
4254 ARM::VLD4DUPq16EvenPseudo,
4255 ARM::VLD4DUPq32EvenPseudo };
4256 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo,
4257 ARM::VLD4DUPq16OddPseudo,
4258 ARM::VLD4DUPq32OddPseudo };
4265 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
4266 ARM::VLD2LNd16Pseudo,
4267 ARM::VLD2LNd32Pseudo };
4268 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
4269 ARM::VLD2LNq32Pseudo };
4275 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
4276 ARM::VLD3LNd16Pseudo,
4277 ARM::VLD3LNd32Pseudo };
4278 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
4279 ARM::VLD3LNq32Pseudo };
4285 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
4286 ARM::VLD4LNd16Pseudo,
4287 ARM::VLD4LNd32Pseudo };
4288 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
4289 ARM::VLD4LNq32Pseudo };
4295 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
4296 ARM::VST1d32, ARM::VST1d64 };
4297 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
4298 ARM::VST1q32, ARM::VST1q64 };
4304 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
4305 ARM::VST1q32, ARM::VST1q64 };
4306 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo,
4307 ARM::VST1d16QPseudo,
4308 ARM::VST1d32QPseudo,
4309 ARM::VST1d64QPseudo };
4315 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo,
4316 ARM::VST1d16TPseudo,
4317 ARM::VST1d32TPseudo,
4318 ARM::VST1d64TPseudo };
4319 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD,
4320 ARM::VST1q16LowTPseudo_UPD,
4321 ARM::VST1q32LowTPseudo_UPD,
4322 ARM::VST1q64LowTPseudo_UPD };
4323 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo,
4324 ARM::VST1q16HighTPseudo,
4325 ARM::VST1q32HighTPseudo,
4326 ARM::VST1q64HighTPseudo };
4332 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo,
4333 ARM::VST1d16QPseudo,
4334 ARM::VST1d32QPseudo,
4335 ARM::VST1d64QPseudo };
4336 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD,
4337 ARM::VST1q16LowQPseudo_UPD,
4338 ARM::VST1q32LowQPseudo_UPD,
4339 ARM::VST1q64LowQPseudo_UPD };
4340 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo,
4341 ARM::VST1q16HighQPseudo,
4342 ARM::VST1q32HighQPseudo,
4343 ARM::VST1q64HighQPseudo };
4349 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
4350 ARM::VST2d32, ARM::VST1q64 };
4351 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
4352 ARM::VST2q32Pseudo };
4358 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
4359 ARM::VST3d16Pseudo,
4360 ARM::VST3d32Pseudo,
4361 ARM::VST1d64TPseudo };
4362 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
4363 ARM::VST3q16Pseudo_UPD,
4364 ARM::VST3q32Pseudo_UPD };
4365 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
4366 ARM::VST3q16oddPseudo,
4367 ARM::VST3q32oddPseudo };
4373 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
4374 ARM::VST4d16Pseudo,
4375 ARM::VST4d32Pseudo,
4376 ARM::VST1d64QPseudo };
4377 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
4378 ARM::VST4q16Pseudo_UPD,
4379 ARM::VST4q32Pseudo_UPD };
4380 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
4381 ARM::VST4q16oddPseudo,
4382 ARM::VST4q32oddPseudo };
4388 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
4389 ARM::VST2LNd16Pseudo,
4390 ARM::VST2LNd32Pseudo };
4391 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
4392 ARM::VST2LNq32Pseudo };
4398 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
4399 ARM::VST3LNd16Pseudo,
4400 ARM::VST3LNd32Pseudo };
4401 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
4402 ARM::VST3LNq32Pseudo };
4408 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
4409 ARM::VST4LNd16Pseudo,
4410 ARM::VST4LNd32Pseudo };
4411 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
4412 ARM::VST4LNq32Pseudo };
4419 static const uint16_t Opcodes[] = {ARM::MVE_VLDRWU32_qi_pre,
4420 ARM::MVE_VLDRDU64_qi_pre};
4427 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, ARM::MVE_VLD21_8};
4428 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16,
4429 ARM::MVE_VLD21_16};
4430 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32,
4431 ARM::MVE_VLD21_32};
4438 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8,
4439 ARM::MVE_VLD42_8, ARM::MVE_VLD43_8};
4440 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16,
4441 ARM::MVE_VLD42_16,
4442 ARM::MVE_VLD43_16};
4443 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32,
4444 ARM::MVE_VLD42_32,
4445 ARM::MVE_VLD43_32};
4461 SelectMVE_LongShift(N, ARM::MVE_URSHRL, true, false);
4464 SelectMVE_LongShift(N, ARM::MVE_UQSHLL, true, false);
4467 SelectMVE_LongShift(N, ARM::MVE_SRSHRL, true, false);
4470 SelectMVE_LongShift(N, ARM::MVE_SQSHLL, true, false);
4473 SelectMVE_LongShift(N, ARM::MVE_UQRSHLL, false, true);
4476 SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true);
4479 SelectMVE_LongShift(N, ARM::MVE_LSLLr, false, false);
4482 SelectMVE_LongShift(N, ARM::MVE_ASRLr, false, false);
4487 SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true,
4494 ARM::MVE_VMLALDAVu16, ARM::MVE_VMLALDAVu32,
4495 ARM::MVE_VMLALDAVau16, ARM::MVE_VMLALDAVau32,
4498 ARM::MVE_VMLALDAVs16, ARM::MVE_VMLALDAVs32,
4499 ARM::MVE_VMLALDAVas16, ARM::MVE_VMLALDAVas32,
4500 ARM::MVE_VMLALDAVxs16, ARM::MVE_VMLALDAVxs32,
4501 ARM::MVE_VMLALDAVaxs16, ARM::MVE_VMLALDAVaxs32,
4502 ARM::MVE_VMLSLDAVs16, ARM::MVE_VMLSLDAVs32,
4503 ARM::MVE_VMLSLDAVas16, ARM::MVE_VMLSLDAVas32,
4504 ARM::MVE_VMLSLDAVxs16, ARM::MVE_VMLSLDAVxs32,
4505 ARM::MVE_VMLSLDAVaxs16, ARM::MVE_VMLSLDAVaxs32,
4515 ARM::MVE_VRMLALDAVHu32, ARM::MVE_VRMLALDAVHau32,
4518 ARM::MVE_VRMLALDAVHs32, ARM::MVE_VRMLALDAVHas32,
4519 ARM::MVE_VRMLALDAVHxs32, ARM::MVE_VRMLALDAVHaxs32,
4520 ARM::MVE_VRMLSLDAVHs32, ARM::MVE_VRMLSLDAVHas32,
4521 ARM::MVE_VRMLSLDAVHxs32, ARM::MVE_VRMLSLDAVHaxs32,
4660 // Lower the read_register intrinsic to ARM specific DAG nodes
4680 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC;
4685 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC;
4704 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
4713 .Case("fpscr", ARM::VMRS)
4714 .Case("fpexc", ARM::VMRS_FPEXC)
4715 .Case("fpsid", ARM::VMRS_FPSID)
4716 .Case("mvfr0", ARM::VMRS_MVFR0)
4717 .Case("mvfr1", ARM::VMRS_MVFR1)
4718 .Case("mvfr2", ARM::VMRS_MVFR2)
4719 .Case("fpinst", ARM::VMRS_FPINST)
4720 .Case("fpinst2", ARM::VMRS_FPINST2)
4727 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8Base())
4749 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
4758 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS,
4767 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL,
4775 // Lower the write_register intrinsic to ARM specific DAG nodes
4794 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
4799 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR;
4819 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
4828 .Case("fpscr", ARM::VMSR)
4829 .Case("fpexc", ARM::VMSR_FPEXC)
4830 .Case("fpsid", ARM::VMSR_FPSID)
4831 .Case("fpinst", ARM::VMSR_FPINST)
4832 .Case("fpinst2", ARM::VMSR_FPINST2)
4859 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
4871 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
4886 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
4951 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
4968 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
4977 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
4979 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
5004 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
5020 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
5060 // Require the address to be in a register. That is safe for all ARM
5070 /// ARM-specific DAG, ready for instruction scheduling.