Lines Matching refs:ARM
16 #include "ARM.h"
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
164 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
165 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
166 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
167 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
168 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
169 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
170 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
171 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
172 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
173 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
174 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
175 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
176 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
177 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
178 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
179 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
180 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
181 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
182 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
183 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
184 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
185 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
186 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
187 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
189 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
190 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
191 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
192 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
193 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
194 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
196 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
197 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
198 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
199 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
200 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
201 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
202 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
203 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
204 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
205 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
207 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
208 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
209 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
210 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
211 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
212 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
213 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
215 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
217 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
218 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
219 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
220 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
221 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
222 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
223 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
224 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
225 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
226 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
227 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
228 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
230 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
231 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
232 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
233 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
234 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
235 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
236 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
237 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
238 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
239 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
241 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
242 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
243 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
244 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
245 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
246 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
248 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
249 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
250 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
251 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
252 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
253 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
254 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
255 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
256 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
258 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
259 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
260 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
261 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
262 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
263 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
264 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
265 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
266 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
267 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
268 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
269 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
271 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
272 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
273 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
274 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
275 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
276 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
277 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
278 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
279 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
280 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
282 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
283 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
284 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
285 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
286 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
287 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
289 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
290 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
291 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
292 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
293 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
294 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
295 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
296 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
297 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
299 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
300 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
301 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
302 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
303 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
304 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
306 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
307 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
308 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
309 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
310 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
311 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
312 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
313 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
314 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
315 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
316 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
317 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
318 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
319 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
320 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
321 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
322 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
323 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
324 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
325 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
326 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
327 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
328 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
329 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
330 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
331 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
332 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
333 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
335 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
336 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
337 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
338 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
339 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
340 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
341 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
342 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
343 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
344 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
346 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
347 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
348 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
349 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
350 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
351 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
352 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
353 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
354 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
356 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
357 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
358 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
359 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
360 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
361 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
362 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
363 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
364 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
365 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
367 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
368 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
369 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
370 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
371 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
372 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
374 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
375 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
376 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
377 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
378 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
379 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
380 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
381 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
382 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
384 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
385 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
386 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
387 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
388 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
389 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
390 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
391 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
392 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
393 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
395 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
396 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
397 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
398 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
399 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
400 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
402 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
403 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
404 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
405 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
406 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
407 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
408 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
409 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
410 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
439 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
440 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
441 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
442 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
444 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
445 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
446 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
447 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
449 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
450 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
451 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
452 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
454 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
455 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
456 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
457 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
460 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
461 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
462 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
463 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
485 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
486 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
487 TableEntry->RealOpc == ARM::VLD2DUPd32x2) {
490 SubRegIndex = ARM::dsub_0;
493 SubRegIndex = ARM::dsub_1;
496 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
497 &ARM::DPairSpcRegClass);
528 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
529 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
530 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
531 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
532 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
533 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
534 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
535 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) {
548 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 &&
549 TableEntry->RealOpc != ARM::VLD2DUPd16x2 &&
550 TableEntry->RealOpc != ARM::VLD2DUPd32x2) {
609 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
610 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
611 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
612 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
613 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
614 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
615 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
616 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
834 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
841 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
842 // FIXME Windows CE supports older ARM CPUs
843 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
846 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
847 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
870 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
871 LO16Opc = ARM::t2MOVi16;
872 HI16Opc = ARM::t2MOVTi16;
874 LO16Opc = ARM::MOVi16;
875 HI16Opc = ARM::MOVTi16;
970 if (LdrexOp == ARM::t2LDREX)
974 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
979 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
983 .addReg(ARM::CPSR, RegState::Kill);
994 if (StrexOp == ARM::t2STREX)
998 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1006 .addReg(ARM::CPSR, RegState::Kill);
1032 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1065 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1066 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1067 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1083 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1089 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1100 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1104 .addReg(ARM::CPSR, RegState::Kill);
1112 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1118 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1126 .addReg(ARM::CPSR, RegState::Kill);
1162 case ARM::TCRETURNdi:
1163 case ARM::TCRETURNri: {
1177 if (RetOpcode == ARM::TCRETURNdi) {
1180 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1181 : ARM::TAILJMPd;
1195 } else if (RetOpcode == ARM::TCRETURNri) {
1197 STI->isThumb() ? ARM::tTAILJMPr
1198 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
1216 case ARM::VMOVHcc:
1217 case ARM::VMOVScc:
1218 case ARM::VMOVDcc: {
1219 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
1230 case ARM::t2MOVCCr:
1231 case ARM::MOVCCr: {
1232 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1244 case ARM::MOVCCsi: {
1245 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1257 case ARM::MOVCCsr: {
1258 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1271 case ARM::t2MOVCCi16:
1272 case ARM::MOVCCi16: {
1273 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1283 case ARM::t2MOVCCi:
1284 case ARM::MOVCCi: {
1285 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1297 case ARM::t2MVNCCi:
1298 case ARM::MVNCCi: {
1299 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1311 case ARM::t2MOVCClsl:
1312 case ARM::t2MOVCClsr:
1313 case ARM::t2MOVCCasr:
1314 case ARM::t2MOVCCror: {
1317 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1318 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1319 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1320 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1334 case ARM::Int_eh_sjlj_dispatchsetup: {
1349 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1352 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1355 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1369 ARM::t2BICri : ARM::BICri;
1370 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1371 .addReg(ARM::R6, RegState::Kill)
1382 case ARM::MOVsrl_flag:
1383 case ARM::MOVsra_flag: {
1385 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1389 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1391 .addReg(ARM::CPSR, RegState::Define);
1395 case ARM::RRX: {
1398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1408 case ARM::tTPsoft:
1409 case ARM::TPsoft: {
1410 const bool Thumb = Opcode == ARM::tTPsoft;
1422 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1429 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1435 TII->get(Thumb ? ARM::tBL : ARM::BL));
1447 case ARM::tLDRpci_pic:
1448 case ARM::t2LDRpci_pic: {
1449 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1450 ? ARM::tLDRpci : ARM::t2LDRpci;
1459 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1468 case ARM::LDRLIT_ga_abs:
1469 case ARM::LDRLIT_ga_pcrel:
1470 case ARM::LDRLIT_ga_pcrel_ldr:
1471 case ARM::tLDRLIT_ga_abs:
1472 case ARM::tLDRLIT_ga_pcrel: {
1479 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1481 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1482 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1485 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1486 : ARM::tPICADD;
1526 case ARM::MOV_ga_pcrel:
1527 case ARM::MOV_ga_pcrel_ldr:
1528 case ARM::t2MOV_ga_pcrel: {
1536 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1537 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1538 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1542 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1543 : ARM::tPICADD;
1560 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1568 case ARM::MOVi32imm:
1569 case ARM::MOVCCi32imm:
1570 case ARM::t2MOVi32imm:
1571 case ARM::t2MOVCCi32imm:
1575 case ARM::SUBS_PC_LR: {
1577 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1578 .addReg(ARM::LR)
1582 .addReg(ARM::CPSR, RegState::Undef);
1587 case ARM::VLDMQIA: {
1588 unsigned NewOpc = ARM::VLDMDIA;
1605 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1606 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1618 case ARM::VSTMQIA: {
1619 unsigned NewOpc = ARM::VSTMDIA;
1637 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1638 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1651 case ARM::VLD2q8Pseudo:
1652 case ARM::VLD2q16Pseudo:
1653 case ARM::VLD2q32Pseudo:
1654 case ARM::VLD2q8PseudoWB_fixed:
1655 case ARM::VLD2q16PseudoWB_fixed:
1656 case ARM::VLD2q32PseudoWB_fixed:
1657 case ARM::VLD2q8PseudoWB_register:
1658 case ARM::VLD2q16PseudoWB_register:
1659 case ARM::VLD2q32PseudoWB_register:
1660 case ARM::VLD3d8Pseudo:
1661 case ARM::VLD3d16Pseudo:
1662 case ARM::VLD3d32Pseudo:
1663 case ARM::VLD1d8TPseudo:
1664 case ARM::VLD1d16TPseudo:
1665 case ARM::VLD1d32TPseudo:
1666 case ARM::VLD1d64TPseudo:
1667 case ARM::VLD1d64TPseudoWB_fixed:
1668 case ARM::VLD1d64TPseudoWB_register:
1669 case ARM::VLD3d8Pseudo_UPD:
1670 case ARM::VLD3d16Pseudo_UPD:
1671 case ARM::VLD3d32Pseudo_UPD:
1672 case ARM::VLD3q8Pseudo_UPD:
1673 case ARM::VLD3q16Pseudo_UPD:
1674 case ARM::VLD3q32Pseudo_UPD:
1675 case ARM::VLD3q8oddPseudo:
1676 case ARM::VLD3q16oddPseudo:
1677 case ARM::VLD3q32oddPseudo:
1678 case ARM::VLD3q8oddPseudo_UPD:
1679 case ARM::VLD3q16oddPseudo_UPD:
1680 case ARM::VLD3q32oddPseudo_UPD:
1681 case ARM::VLD4d8Pseudo:
1682 case ARM::VLD4d16Pseudo:
1683 case ARM::VLD4d32Pseudo:
1684 case ARM::VLD1d8QPseudo:
1685 case ARM::VLD1d16QPseudo:
1686 case ARM::VLD1d32QPseudo:
1687 case ARM::VLD1d64QPseudo:
1688 case ARM::VLD1d64QPseudoWB_fixed:
1689 case ARM::VLD1d64QPseudoWB_register:
1690 case ARM::VLD1q8HighQPseudo:
1691 case ARM::VLD1q8LowQPseudo_UPD:
1692 case ARM::VLD1q8HighTPseudo:
1693 case ARM::VLD1q8LowTPseudo_UPD:
1694 case ARM::VLD1q16HighQPseudo:
1695 case ARM::VLD1q16LowQPseudo_UPD:
1696 case ARM::VLD1q16HighTPseudo:
1697 case ARM::VLD1q16LowTPseudo_UPD:
1698 case ARM::VLD1q32HighQPseudo:
1699 case ARM::VLD1q32LowQPseudo_UPD:
1700 case ARM::VLD1q32HighTPseudo:
1701 case ARM::VLD1q32LowTPseudo_UPD:
1702 case ARM::VLD1q64HighQPseudo:
1703 case ARM::VLD1q64LowQPseudo_UPD:
1704 case ARM::VLD1q64HighTPseudo:
1705 case ARM::VLD1q64LowTPseudo_UPD:
1706 case ARM::VLD4d8Pseudo_UPD:
1707 case ARM::VLD4d16Pseudo_UPD:
1708 case ARM::VLD4d32Pseudo_UPD:
1709 case ARM::VLD4q8Pseudo_UPD:
1710 case ARM::VLD4q16Pseudo_UPD:
1711 case ARM::VLD4q32Pseudo_UPD:
1712 case ARM::VLD4q8oddPseudo:
1713 case ARM::VLD4q16oddPseudo:
1714 case ARM::VLD4q32oddPseudo:
1715 case ARM::VLD4q8oddPseudo_UPD:
1716 case ARM::VLD4q16oddPseudo_UPD:
1717 case ARM::VLD4q32oddPseudo_UPD:
1718 case ARM::VLD3DUPd8Pseudo:
1719 case ARM::VLD3DUPd16Pseudo:
1720 case ARM::VLD3DUPd32Pseudo:
1721 case ARM::VLD3DUPd8Pseudo_UPD:
1722 case ARM::VLD3DUPd16Pseudo_UPD:
1723 case ARM::VLD3DUPd32Pseudo_UPD:
1724 case ARM::VLD4DUPd8Pseudo:
1725 case ARM::VLD4DUPd16Pseudo:
1726 case ARM::VLD4DUPd32Pseudo:
1727 case ARM::VLD4DUPd8Pseudo_UPD:
1728 case ARM::VLD4DUPd16Pseudo_UPD:
1729 case ARM::VLD4DUPd32Pseudo_UPD:
1730 case ARM::VLD2DUPq8EvenPseudo:
1731 case ARM::VLD2DUPq8OddPseudo:
1732 case ARM::VLD2DUPq16EvenPseudo:
1733 case ARM::VLD2DUPq16OddPseudo:
1734 case ARM::VLD2DUPq32EvenPseudo:
1735 case ARM::VLD2DUPq32OddPseudo:
1736 case ARM::VLD3DUPq8EvenPseudo:
1737 case ARM::VLD3DUPq8OddPseudo:
1738 case ARM::VLD3DUPq16EvenPseudo:
1739 case ARM::VLD3DUPq16OddPseudo:
1740 case ARM::VLD3DUPq32EvenPseudo:
1741 case ARM::VLD3DUPq32OddPseudo:
1742 case ARM::VLD4DUPq8EvenPseudo:
1743 case ARM::VLD4DUPq8OddPseudo:
1744 case ARM::VLD4DUPq16EvenPseudo:
1745 case ARM::VLD4DUPq16OddPseudo:
1746 case ARM::VLD4DUPq32EvenPseudo:
1747 case ARM::VLD4DUPq32OddPseudo:
1751 case ARM::VST2q8Pseudo:
1752 case ARM::VST2q16Pseudo:
1753 case ARM::VST2q32Pseudo:
1754 case ARM::VST2q8PseudoWB_fixed:
1755 case ARM::VST2q16PseudoWB_fixed:
1756 case ARM::VST2q32PseudoWB_fixed:
1757 case ARM::VST2q8PseudoWB_register:
1758 case ARM::VST2q16PseudoWB_register:
1759 case ARM::VST2q32PseudoWB_register:
1760 case ARM::VST3d8Pseudo:
1761 case ARM::VST3d16Pseudo:
1762 case ARM::VST3d32Pseudo:
1763 case ARM::VST1d8TPseudo:
1764 case ARM::VST1d16TPseudo:
1765 case ARM::VST1d32TPseudo:
1766 case ARM::VST1d64TPseudo:
1767 case ARM::VST3d8Pseudo_UPD:
1768 case ARM::VST3d16Pseudo_UPD:
1769 case ARM::VST3d32Pseudo_UPD:
1770 case ARM::VST1d64TPseudoWB_fixed:
1771 case ARM::VST1d64TPseudoWB_register:
1772 case ARM::VST3q8Pseudo_UPD:
1773 case ARM::VST3q16Pseudo_UPD:
1774 case ARM::VST3q32Pseudo_UPD:
1775 case ARM::VST3q8oddPseudo:
1776 case ARM::VST3q16oddPseudo:
1777 case ARM::VST3q32oddPseudo:
1778 case ARM::VST3q8oddPseudo_UPD:
1779 case ARM::VST3q16oddPseudo_UPD:
1780 case ARM::VST3q32oddPseudo_UPD:
1781 case ARM::VST4d8Pseudo:
1782 case ARM::VST4d16Pseudo:
1783 case ARM::VST4d32Pseudo:
1784 case ARM::VST1d8QPseudo:
1785 case ARM::VST1d16QPseudo:
1786 case ARM::VST1d32QPseudo:
1787 case ARM::VST1d64QPseudo:
1788 case ARM::VST4d8Pseudo_UPD:
1789 case ARM::VST4d16Pseudo_UPD:
1790 case ARM::VST4d32Pseudo_UPD:
1791 case ARM::VST1d64QPseudoWB_fixed:
1792 case ARM::VST1d64QPseudoWB_register:
1793 case ARM::VST1q8HighQPseudo:
1794 case ARM::VST1q8LowQPseudo_UPD:
1795 case ARM::VST1q8HighTPseudo:
1796 case ARM::VST1q8LowTPseudo_UPD:
1797 case ARM::VST1q16HighQPseudo:
1798 case ARM::VST1q16LowQPseudo_UPD:
1799 case ARM::VST1q16HighTPseudo:
1800 case ARM::VST1q16LowTPseudo_UPD:
1801 case ARM::VST1q32HighQPseudo:
1802 case ARM::VST1q32LowQPseudo_UPD:
1803 case ARM::VST1q32HighTPseudo:
1804 case ARM::VST1q32LowTPseudo_UPD:
1805 case ARM::VST1q64HighQPseudo:
1806 case ARM::VST1q64LowQPseudo_UPD:
1807 case ARM::VST1q64HighTPseudo:
1808 case ARM::VST1q64LowTPseudo_UPD:
1809 case ARM::VST4q8Pseudo_UPD:
1810 case ARM::VST4q16Pseudo_UPD:
1811 case ARM::VST4q32Pseudo_UPD:
1812 case ARM::VST4q8oddPseudo:
1813 case ARM::VST4q16oddPseudo:
1814 case ARM::VST4q32oddPseudo:
1815 case ARM::VST4q8oddPseudo_UPD:
1816 case ARM::VST4q16oddPseudo_UPD:
1817 case ARM::VST4q32oddPseudo_UPD:
1821 case ARM::VLD1LNq8Pseudo:
1822 case ARM::VLD1LNq16Pseudo:
1823 case ARM::VLD1LNq32Pseudo:
1824 case ARM::VLD1LNq8Pseudo_UPD:
1825 case ARM::VLD1LNq16Pseudo_UPD:
1826 case ARM::VLD1LNq32Pseudo_UPD:
1827 case ARM::VLD2LNd8Pseudo:
1828 case ARM::VLD2LNd16Pseudo:
1829 case ARM::VLD2LNd32Pseudo:
1830 case ARM::VLD2LNq16Pseudo:
1831 case ARM::VLD2LNq32Pseudo:
1832 case ARM::VLD2LNd8Pseudo_UPD:
1833 case ARM::VLD2LNd16Pseudo_UPD:
1834 case ARM::VLD2LNd32Pseudo_UPD:
1835 case ARM::VLD2LNq16Pseudo_UPD:
1836 case ARM::VLD2LNq32Pseudo_UPD:
1837 case ARM::VLD3LNd8Pseudo:
1838 case ARM::VLD3LNd16Pseudo:
1839 case ARM::VLD3LNd32Pseudo:
1840 case ARM::VLD3LNq16Pseudo:
1841 case ARM::VLD3LNq32Pseudo:
1842 case ARM::VLD3LNd8Pseudo_UPD:
1843 case ARM::VLD3LNd16Pseudo_UPD:
1844 case ARM::VLD3LNd32Pseudo_UPD:
1845 case ARM::VLD3LNq16Pseudo_UPD:
1846 case ARM::VLD3LNq32Pseudo_UPD:
1847 case ARM::VLD4LNd8Pseudo:
1848 case ARM::VLD4LNd16Pseudo:
1849 case ARM::VLD4LNd32Pseudo:
1850 case ARM::VLD4LNq16Pseudo:
1851 case ARM::VLD4LNq32Pseudo:
1852 case ARM::VLD4LNd8Pseudo_UPD:
1853 case ARM::VLD4LNd16Pseudo_UPD:
1854 case ARM::VLD4LNd32Pseudo_UPD:
1855 case ARM::VLD4LNq16Pseudo_UPD:
1856 case ARM::VLD4LNq32Pseudo_UPD:
1857 case ARM::VST1LNq8Pseudo:
1858 case ARM::VST1LNq16Pseudo:
1859 case ARM::VST1LNq32Pseudo:
1860 case ARM::VST1LNq8Pseudo_UPD:
1861 case ARM::VST1LNq16Pseudo_UPD:
1862 case ARM::VST1LNq32Pseudo_UPD:
1863 case ARM::VST2LNd8Pseudo:
1864 case ARM::VST2LNd16Pseudo:
1865 case ARM::VST2LNd32Pseudo:
1866 case ARM::VST2LNq16Pseudo:
1867 case ARM::VST2LNq32Pseudo:
1868 case ARM::VST2LNd8Pseudo_UPD:
1869 case ARM::VST2LNd16Pseudo_UPD:
1870 case ARM::VST2LNd32Pseudo_UPD:
1871 case ARM::VST2LNq16Pseudo_UPD:
1872 case ARM::VST2LNq32Pseudo_UPD:
1873 case ARM::VST3LNd8Pseudo:
1874 case ARM::VST3LNd16Pseudo:
1875 case ARM::VST3LNd32Pseudo:
1876 case ARM::VST3LNq16Pseudo:
1877 case ARM::VST3LNq32Pseudo:
1878 case ARM::VST3LNd8Pseudo_UPD:
1879 case ARM::VST3LNd16Pseudo_UPD:
1880 case ARM::VST3LNd32Pseudo_UPD:
1881 case ARM::VST3LNq16Pseudo_UPD:
1882 case ARM::VST3LNq32Pseudo_UPD:
1883 case ARM::VST4LNd8Pseudo:
1884 case ARM::VST4LNd16Pseudo:
1885 case ARM::VST4LNd32Pseudo:
1886 case ARM::VST4LNq16Pseudo:
1887 case ARM::VST4LNq32Pseudo:
1888 case ARM::VST4LNd8Pseudo_UPD:
1889 case ARM::VST4LNd16Pseudo_UPD:
1890 case ARM::VST4LNd32Pseudo_UPD:
1891 case ARM::VST4LNq16Pseudo_UPD:
1892 case ARM::VST4LNq32Pseudo_UPD:
1896 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1897 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1898 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1899 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1901 case ARM::CMP_SWAP_8:
1903 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1904 ARM::tUXTB, NextMBBI);
1906 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1907 ARM::UXTB, NextMBBI);
1908 case ARM::CMP_SWAP_16:
1910 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1911 ARM::tUXTH, NextMBBI);
1913 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1914 ARM::UXTH, NextMBBI);
1915 case ARM::CMP_SWAP_32:
1917 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1920 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1922 case ARM::CMP_SWAP_64:
1925 case ARM::tBL_PUSHLR:
1926 case ARM::BL_PUSHLR: {
1927 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
1929 assert(Reg == ARM::LR && "expect LR register!");
1933 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
1938 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
1941 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
1942 .addReg(ARM::SP, RegState::Define)
1943 .addReg(ARM::SP)
1948 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
1977 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
1984 MF.verify(this, "After expanding ARM pseudo instructions.");