1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include "ARMBaseInstrInfo.h" 10#include "MCTargetDesc/ARMAddressingModes.h" 11#include "MCTargetDesc/ARMBaseInfo.h" 12#include "MCTargetDesc/ARMMCTargetDesc.h" 13#include "TargetInfo/ARMTargetInfo.h" 14#include "Utils/ARMBaseInfo.h" 15#include "llvm/MC/MCContext.h" 16#include "llvm/MC/MCDisassembler/MCDisassembler.h" 17#include "llvm/MC/MCFixedLenDisassembler.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCInstrDesc.h" 20#include "llvm/MC/MCSubtargetInfo.h" 21#include "llvm/MC/SubtargetFeature.h" 22#include "llvm/Support/Compiler.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/MathExtras.h" 25#include "llvm/Support/TargetRegistry.h" 26#include "llvm/Support/raw_ostream.h" 27#include <algorithm> 28#include <cassert> 29#include <cstdint> 30#include <vector> 31 32using namespace llvm; 33 34#define DEBUG_TYPE "arm-disassembler" 35 36using DecodeStatus = MCDisassembler::DecodeStatus; 37 38namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129/// ARM disassembler for all ARM platforms. 130class ARMDisassembler : public MCDisassembler { 131public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156}; 157 158} // end anonymous namespace 159 160static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173} 174 175// Forward declare these because the autogenerated code will reference them. 176// Definitions are further down. 177static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 186 unsigned RegNo, uint64_t Address, 187 const void *Decoder); 188static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194static DecodeStatus DecodeGPRwithZRnospRegisterClass( 195 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 196static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 201 uint64_t Address, const void *Decoder); 202static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, 206 const void *Decoder); 207static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 218 unsigned RegNo, 219 uint64_t Address, 220 const void *Decoder); 221static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, const void *Decoder); 231static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 232 unsigned RegNo, uint64_t Address, 233 const void *Decoder); 234 235static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 246static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 251 unsigned Insn, 252 uint64_t Address, 253 const void *Decoder); 254static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 264 unsigned Insn, 265 uint64_t Adddress, 266 const void *Decoder); 267static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 288 uint64_t Address, const void *Decoder); 289static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 294 uint64_t Address, const void *Decoder); 295static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 318 uint64_t Address, const void *Decoder); 319static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 320 uint64_t Address, const void *Decoder); 321static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339template<int shift> 340static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 381 uint64_t Address, const void *Decoder); 382static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 383 uint64_t Address, const void *Decoder); 384static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 385 uint64_t Address, const void *Decoder); 386static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 387 uint64_t Address, const void *Decoder); 388static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 391 uint64_t Address, const void *Decoder); 392static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 393 unsigned Val, 394 uint64_t Address, 395 const void *Decoder); 396 397static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 398 uint64_t Address, const void *Decoder); 399static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 408 uint64_t Address, const void *Decoder); 409static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 410 uint64_t Address, const void *Decoder); 411static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 412 uint64_t Address, const void *Decoder); 413static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 418 uint64_t Address, const void* Decoder); 419static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void* Decoder); 421static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void* Decoder); 423static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void* Decoder); 425static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 428 uint64_t Address, const void *Decoder); 429static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 430 uint64_t Address, const void *Decoder); 431static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 432 uint64_t Address, 433 const void *Decoder); 434static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 435 uint64_t Address, const void *Decoder); 436static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438template<int shift> 439static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443template<int shift> 444static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446template<int shift, int WriteBack> 447static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 450 uint64_t Address, const void *Decoder); 451static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 452 uint64_t Address, const void *Decoder); 453static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 454 uint64_t Address, const void *Decoder); 455static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 456 uint64_t Address, const void *Decoder); 457static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 458 uint64_t Address, const void *Decoder); 459static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 468 uint64_t Address, const void *Decoder); 469static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 470 uint64_t Address, const void *Decoder); 471static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 472 uint64_t Address, const void *Decoder); 473static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 474 uint64_t Address, const void *Decoder); 475static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 476 uint64_t Address, const void *Decoder); 477static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 478 uint64_t Address, const void *Decoder); 479static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 480 uint64_t Address, const void *Decoder); 481static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, const void *Decoder); 483 484static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 491template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 492static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 493 uint64_t Address, const void *Decoder); 494static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 495 uint64_t Address, 496 const void *Decoder); 497static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const void *Decoder); 500static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 501 const void *Decoder); 502static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, const void *Decoder); 509static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, const void *Decoder); 511static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const void *Decoder); 514static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const void *Decoder); 517static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 521 unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524template<bool Writeback> 525static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const void *Decoder); 528template<int shift> 529static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 530 uint64_t Address, const void *Decoder); 531template<int shift> 532static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534template<int shift> 535static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 536 uint64_t Address, const void *Decoder); 537template<unsigned MinLog, unsigned MaxLog> 538static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const void *Decoder); 541template <int shift> 542static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 543 uint64_t Address, 544 const void *Decoder); 545template<unsigned start> 546static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const void *Decoder); 549static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 550 uint64_t Address, 551 const void *Decoder); 552static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 553 uint64_t Address, 554 const void *Decoder); 555static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 556 uint64_t Address, const void *Decoder); 557typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 558 uint64_t Address, const void *Decoder); 559template<bool scalar, OperandDecoder predicate_decoder> 560static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 561 uint64_t Address, const void *Decoder); 562static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 563 uint64_t Address, const void *Decoder); 564static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 565 uint64_t Address, const void *Decoder); 566static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const void *Decoder); 569static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 570 uint64_t Address, const void *Decoder); 571 572#include "ARMGenDisassemblerTables.inc" 573 574static MCDisassembler *createARMDisassembler(const Target &T, 575 const MCSubtargetInfo &STI, 576 MCContext &Ctx) { 577 return new ARMDisassembler(STI, Ctx); 578} 579 580// Post-decoding checks 581static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 582 uint64_t Address, raw_ostream &CS, 583 uint32_t Insn, 584 DecodeStatus Result) { 585 switch (MI.getOpcode()) { 586 case ARM::HVC: { 587 // HVC is undefined if condition = 0xf otherwise upredictable 588 // if condition != 0xe 589 uint32_t Cond = (Insn >> 28) & 0xF; 590 if (Cond == 0xF) 591 return MCDisassembler::Fail; 592 if (Cond != 0xE) 593 return MCDisassembler::SoftFail; 594 return Result; 595 } 596 case ARM::t2ADDri: 597 case ARM::t2ADDri12: 598 case ARM::t2ADDrr: 599 case ARM::t2ADDrs: 600 case ARM::t2SUBri: 601 case ARM::t2SUBri12: 602 case ARM::t2SUBrr: 603 case ARM::t2SUBrs: 604 if (MI.getOperand(0).getReg() == ARM::SP && 605 MI.getOperand(1).getReg() != ARM::SP) 606 return MCDisassembler::SoftFail; 607 return Result; 608 default: return Result; 609 } 610} 611 612DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 613 ArrayRef<uint8_t> Bytes, 614 uint64_t Address, 615 raw_ostream &CS) const { 616 if (STI.getFeatureBits()[ARM::ModeThumb]) 617 return getThumbInstruction(MI, Size, Bytes, Address, CS); 618 return getARMInstruction(MI, Size, Bytes, Address, CS); 619} 620 621DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 622 ArrayRef<uint8_t> Bytes, 623 uint64_t Address, 624 raw_ostream &CS) const { 625 CommentStream = &CS; 626 627 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 628 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 629 "mode!"); 630 631 // We want to read exactly 4 bytes of data. 632 if (Bytes.size() < 4) { 633 Size = 0; 634 return MCDisassembler::Fail; 635 } 636 637 // Encoded as a small-endian 32-bit word in the stream. 638 uint32_t Insn = 639 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 640 641 // Calling the auto-generated decoder function. 642 DecodeStatus Result = 643 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 644 if (Result != MCDisassembler::Fail) { 645 Size = 4; 646 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 647 } 648 649 struct DecodeTable { 650 const uint8_t *P; 651 bool DecodePred; 652 }; 653 654 const DecodeTable Tables[] = { 655 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 656 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 657 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 658 {DecoderTablev8Crypto32, false}, 659 }; 660 661 for (auto Table : Tables) { 662 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 663 if (Result != MCDisassembler::Fail) { 664 Size = 4; 665 // Add a fake predicate operand, because we share these instruction 666 // definitions with Thumb2 where these instructions are predicable. 667 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 668 return MCDisassembler::Fail; 669 return Result; 670 } 671 } 672 673 Result = 674 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 675 if (Result != MCDisassembler::Fail) { 676 Size = 4; 677 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 678 } 679 680 Size = 4; 681 return MCDisassembler::Fail; 682} 683 684namespace llvm { 685 686extern const MCInstrDesc ARMInsts[]; 687 688} // end namespace llvm 689 690/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 691/// immediate Value in the MCInst. The immediate Value has had any PC 692/// adjustment made by the caller. If the instruction is a branch instruction 693/// then isBranch is true, else false. If the getOpInfo() function was set as 694/// part of the setupForSymbolicDisassembly() call then that function is called 695/// to get any symbolic information at the Address for this instruction. If 696/// that returns non-zero then the symbolic information it returns is used to 697/// create an MCExpr and that is added as an operand to the MCInst. If 698/// getOpInfo() returns zero and isBranch is true then a symbol look up for 699/// Value is done and if a symbol is found an MCExpr is created with that, else 700/// an MCExpr with Value is created. This function returns true if it adds an 701/// operand to the MCInst and false otherwise. 702static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 703 bool isBranch, uint64_t InstSize, 704 MCInst &MI, const void *Decoder) { 705 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 706 // FIXME: Does it make sense for value to be negative? 707 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 708 /* Offset */ 0, InstSize); 709} 710 711/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 712/// referenced by a load instruction with the base register that is the Pc. 713/// These can often be values in a literal pool near the Address of the 714/// instruction. The Address of the instruction and its immediate Value are 715/// used as a possible literal pool entry. The SymbolLookUp call back will 716/// return the name of a symbol referenced by the literal pool's entry if 717/// the referenced address is that of a symbol. Or it will return a pointer to 718/// a literal 'C' string if the referenced address of the literal pool's entry 719/// is an address into a section with 'C' string literals. 720static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 721 const void *Decoder) { 722 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 723 Dis->tryAddingPcLoadReferenceComment(Value, Address); 724} 725 726// Thumb1 instructions don't have explicit S bits. Rather, they 727// implicitly set CPSR. Since it's not represented in the encoding, the 728// auto-generated decoder won't inject the CPSR operand. We need to fix 729// that as a post-pass. 730static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 731 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 732 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 733 MCInst::iterator I = MI.begin(); 734 for (unsigned i = 0; i < NumOps; ++i, ++I) { 735 if (I == MI.end()) break; 736 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 737 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 739 return; 740 } 741 } 742 743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 744} 745 746static bool isVectorPredicable(unsigned Opcode) { 747 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 748 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 749 for (unsigned i = 0; i < NumOps; ++i) { 750 if (ARM::isVpred(OpInfo[i].OperandType)) 751 return true; 752 } 753 return false; 754} 755 756// Most Thumb instructions don't have explicit predicates in the 757// encoding, but rather get their predicates from IT context. We need 758// to fix up the predicate operands using this context information as a 759// post-pass. 760MCDisassembler::DecodeStatus 761ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 762 MCDisassembler::DecodeStatus S = Success; 763 764 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 765 766 // A few instructions actually have predicates encoded in them. Don't 767 // try to overwrite it if we're seeing one of those. 768 switch (MI.getOpcode()) { 769 case ARM::tBcc: 770 case ARM::t2Bcc: 771 case ARM::tCBZ: 772 case ARM::tCBNZ: 773 case ARM::tCPS: 774 case ARM::t2CPS3p: 775 case ARM::t2CPS2p: 776 case ARM::t2CPS1p: 777 case ARM::t2CSEL: 778 case ARM::t2CSINC: 779 case ARM::t2CSINV: 780 case ARM::t2CSNEG: 781 case ARM::tMOVSr: 782 case ARM::tSETEND: 783 // Some instructions (mostly conditional branches) are not 784 // allowed in IT blocks. 785 if (ITBlock.instrInITBlock()) 786 S = SoftFail; 787 else 788 return Success; 789 break; 790 case ARM::t2HINT: 791 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 792 S = SoftFail; 793 break; 794 case ARM::tB: 795 case ARM::t2B: 796 case ARM::t2TBB: 797 case ARM::t2TBH: 798 // Some instructions (mostly unconditional branches) can 799 // only appears at the end of, or outside of, an IT. 800 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 801 S = SoftFail; 802 break; 803 default: 804 break; 805 } 806 807 // Warn on non-VPT predicable instruction in a VPT block and a VPT 808 // predicable instruction in an IT block 809 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 810 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 811 S = SoftFail; 812 813 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 814 // assume a predicate of AL. 815 unsigned CC = ARMCC::AL; 816 unsigned VCC = ARMVCC::None; 817 if (ITBlock.instrInITBlock()) { 818 CC = ITBlock.getITCC(); 819 ITBlock.advanceITState(); 820 } else if (VPTBlock.instrInVPTBlock()) { 821 VCC = VPTBlock.getVPTPred(); 822 VPTBlock.advanceVPTState(); 823 } 824 825 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 826 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 827 828 MCInst::iterator CCI = MI.begin(); 829 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 830 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 831 } 832 833 if (ARMInsts[MI.getOpcode()].isPredicable()) { 834 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 835 ++CCI; 836 if (CC == ARMCC::AL) 837 MI.insert(CCI, MCOperand::createReg(0)); 838 else 839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 840 } else if (CC != ARMCC::AL) { 841 Check(S, SoftFail); 842 } 843 844 MCInst::iterator VCCI = MI.begin(); 845 unsigned VCCPos; 846 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 847 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 848 } 849 850 if (isVectorPredicable(MI.getOpcode())) { 851 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 852 ++VCCI; 853 if (VCC == ARMVCC::None) 854 MI.insert(VCCI, MCOperand::createReg(0)); 855 else 856 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 857 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 858 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 859 VCCPos + 2, MCOI::TIED_TO); 860 assert(TiedOp >= 0 && 861 "Inactive register in vpred_r is not tied to an output!"); 862 MI.insert(VCCI, MI.getOperand(TiedOp)); 863 } 864 } else if (VCC != ARMVCC::None) { 865 Check(S, SoftFail); 866 } 867 868 return S; 869} 870 871// Thumb VFP instructions are a special case. Because we share their 872// encodings between ARM and Thumb modes, and they are predicable in ARM 873// mode, the auto-generated decoder will give them an (incorrect) 874// predicate operand. We need to rewrite these operands based on the IT 875// context as a post-pass. 876void ARMDisassembler::UpdateThumbVFPPredicate( 877 DecodeStatus &S, MCInst &MI) const { 878 unsigned CC; 879 CC = ITBlock.getITCC(); 880 if (CC == 0xF) 881 CC = ARMCC::AL; 882 if (ITBlock.instrInITBlock()) 883 ITBlock.advanceITState(); 884 else if (VPTBlock.instrInVPTBlock()) { 885 CC = VPTBlock.getVPTPred(); 886 VPTBlock.advanceVPTState(); 887 } 888 889 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 890 MCInst::iterator I = MI.begin(); 891 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 892 for (unsigned i = 0; i < NumOps; ++i, ++I) { 893 if (OpInfo[i].isPredicate() ) { 894 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 895 Check(S, SoftFail); 896 I->setImm(CC); 897 ++I; 898 if (CC == ARMCC::AL) 899 I->setReg(0); 900 else 901 I->setReg(ARM::CPSR); 902 return; 903 } 904 } 905} 906 907DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 908 ArrayRef<uint8_t> Bytes, 909 uint64_t Address, 910 raw_ostream &CS) const { 911 CommentStream = &CS; 912 913 assert(STI.getFeatureBits()[ARM::ModeThumb] && 914 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 915 916 // We want to read exactly 2 bytes of data. 917 if (Bytes.size() < 2) { 918 Size = 0; 919 return MCDisassembler::Fail; 920 } 921 922 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 923 DecodeStatus Result = 924 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 925 if (Result != MCDisassembler::Fail) { 926 Size = 2; 927 Check(Result, AddThumbPredicate(MI)); 928 return Result; 929 } 930 931 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 932 STI); 933 if (Result) { 934 Size = 2; 935 bool InITBlock = ITBlock.instrInITBlock(); 936 Check(Result, AddThumbPredicate(MI)); 937 AddThumb1SBit(MI, InITBlock); 938 return Result; 939 } 940 941 Result = 942 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 943 if (Result != MCDisassembler::Fail) { 944 Size = 2; 945 946 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 947 // the Thumb predicate. 948 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 949 Result = MCDisassembler::SoftFail; 950 951 Check(Result, AddThumbPredicate(MI)); 952 953 // If we find an IT instruction, we need to parse its condition 954 // code and mask operands so that we can apply them correctly 955 // to the subsequent instructions. 956 if (MI.getOpcode() == ARM::t2IT) { 957 unsigned Firstcond = MI.getOperand(0).getImm(); 958 unsigned Mask = MI.getOperand(1).getImm(); 959 ITBlock.setITState(Firstcond, Mask); 960 961 // An IT instruction that would give a 'NV' predicate is unpredictable. 962 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 963 CS << "unpredictable IT predicate sequence"; 964 } 965 966 return Result; 967 } 968 969 // We want to read exactly 4 bytes of data. 970 if (Bytes.size() < 4) { 971 Size = 0; 972 return MCDisassembler::Fail; 973 } 974 975 uint32_t Insn32 = 976 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 977 978 Result = 979 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 980 if (Result != MCDisassembler::Fail) { 981 Size = 4; 982 983 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 984 // the VPT predicate. 985 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 986 Result = MCDisassembler::SoftFail; 987 988 Check(Result, AddThumbPredicate(MI)); 989 990 if (isVPTOpcode(MI.getOpcode())) { 991 unsigned Mask = MI.getOperand(0).getImm(); 992 VPTBlock.setVPTState(Mask); 993 } 994 995 return Result; 996 } 997 998 Result = 999 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1000 if (Result != MCDisassembler::Fail) { 1001 Size = 4; 1002 bool InITBlock = ITBlock.instrInITBlock(); 1003 Check(Result, AddThumbPredicate(MI)); 1004 AddThumb1SBit(MI, InITBlock); 1005 return Result; 1006 } 1007 1008 Result = 1009 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1010 if (Result != MCDisassembler::Fail) { 1011 Size = 4; 1012 Check(Result, AddThumbPredicate(MI)); 1013 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1014 } 1015 1016 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1017 Result = 1018 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1019 if (Result != MCDisassembler::Fail) { 1020 Size = 4; 1021 UpdateThumbVFPPredicate(Result, MI); 1022 return Result; 1023 } 1024 } 1025 1026 Result = 1027 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1028 if (Result != MCDisassembler::Fail) { 1029 Size = 4; 1030 return Result; 1031 } 1032 1033 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1034 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1035 STI); 1036 if (Result != MCDisassembler::Fail) { 1037 Size = 4; 1038 Check(Result, AddThumbPredicate(MI)); 1039 return Result; 1040 } 1041 } 1042 1043 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1044 uint32_t NEONLdStInsn = Insn32; 1045 NEONLdStInsn &= 0xF0FFFFFF; 1046 NEONLdStInsn |= 0x04000000; 1047 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1048 Address, this, STI); 1049 if (Result != MCDisassembler::Fail) { 1050 Size = 4; 1051 Check(Result, AddThumbPredicate(MI)); 1052 return Result; 1053 } 1054 } 1055 1056 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1057 uint32_t NEONDataInsn = Insn32; 1058 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1059 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1060 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1061 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1062 Address, this, STI); 1063 if (Result != MCDisassembler::Fail) { 1064 Size = 4; 1065 Check(Result, AddThumbPredicate(MI)); 1066 return Result; 1067 } 1068 1069 uint32_t NEONCryptoInsn = Insn32; 1070 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1071 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1072 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1073 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1074 Address, this, STI); 1075 if (Result != MCDisassembler::Fail) { 1076 Size = 4; 1077 return Result; 1078 } 1079 1080 uint32_t NEONv8Insn = Insn32; 1081 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1082 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1083 this, STI); 1084 if (Result != MCDisassembler::Fail) { 1085 Size = 4; 1086 return Result; 1087 } 1088 } 1089 1090 Result = 1091 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1092 if (Result != MCDisassembler::Fail) { 1093 Size = 4; 1094 Check(Result, AddThumbPredicate(MI)); 1095 return Result; 1096 } 1097 1098 Size = 0; 1099 return MCDisassembler::Fail; 1100} 1101 1102extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1103 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1104 createARMDisassembler); 1105 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1106 createARMDisassembler); 1107 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1108 createARMDisassembler); 1109 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1110 createARMDisassembler); 1111} 1112 1113static const uint16_t GPRDecoderTable[] = { 1114 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1115 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1116 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1118}; 1119 1120static const uint16_t CLRMGPRDecoderTable[] = { 1121 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1122 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1123 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1124 ARM::R12, 0, ARM::LR, ARM::APSR 1125}; 1126 1127static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1128 uint64_t Address, const void *Decoder) { 1129 if (RegNo > 15) 1130 return MCDisassembler::Fail; 1131 1132 unsigned Register = GPRDecoderTable[RegNo]; 1133 Inst.addOperand(MCOperand::createReg(Register)); 1134 return MCDisassembler::Success; 1135} 1136 1137static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1138 uint64_t Address, 1139 const void *Decoder) { 1140 if (RegNo > 15) 1141 return MCDisassembler::Fail; 1142 1143 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1144 if (Register == 0) 1145 return MCDisassembler::Fail; 1146 1147 Inst.addOperand(MCOperand::createReg(Register)); 1148 return MCDisassembler::Success; 1149} 1150 1151static DecodeStatus 1152DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1153 uint64_t Address, const void *Decoder) { 1154 DecodeStatus S = MCDisassembler::Success; 1155 1156 if (RegNo == 15) 1157 S = MCDisassembler::SoftFail; 1158 1159 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1160 1161 return S; 1162} 1163 1164static DecodeStatus 1165DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1166 uint64_t Address, const void *Decoder) { 1167 DecodeStatus S = MCDisassembler::Success; 1168 1169 if (RegNo == 15) 1170 { 1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1172 return MCDisassembler::Success; 1173 } 1174 1175 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1176 return S; 1177} 1178 1179static DecodeStatus 1180DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1181 uint64_t Address, const void *Decoder) { 1182 DecodeStatus S = MCDisassembler::Success; 1183 1184 if (RegNo == 15) 1185 { 1186 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1187 return MCDisassembler::Success; 1188 } 1189 1190 if (RegNo == 13) 1191 Check(S, MCDisassembler::SoftFail); 1192 1193 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1194 return S; 1195} 1196 1197static DecodeStatus 1198DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1199 uint64_t Address, const void *Decoder) { 1200 DecodeStatus S = MCDisassembler::Success; 1201 if (RegNo == 13) 1202 return MCDisassembler::Fail; 1203 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1204 return S; 1205} 1206 1207static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1208 uint64_t Address, const void *Decoder) { 1209 if (RegNo > 7) 1210 return MCDisassembler::Fail; 1211 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1212} 1213 1214static const uint16_t GPRPairDecoderTable[] = { 1215 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1216 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1217}; 1218 1219static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1220 uint64_t Address, const void *Decoder) { 1221 DecodeStatus S = MCDisassembler::Success; 1222 1223 if (RegNo > 13) 1224 return MCDisassembler::Fail; 1225 1226 if ((RegNo & 1) || RegNo == 0xe) 1227 S = MCDisassembler::SoftFail; 1228 1229 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1230 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1231 return S; 1232} 1233 1234static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1235 uint64_t Address, 1236 const void *Decoder) { 1237 if (RegNo != 13) 1238 return MCDisassembler::Fail; 1239 1240 unsigned Register = GPRDecoderTable[RegNo]; 1241 Inst.addOperand(MCOperand::createReg(Register)); 1242 return MCDisassembler::Success; 1243} 1244 1245static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1246 uint64_t Address, const void *Decoder) { 1247 unsigned Register = 0; 1248 switch (RegNo) { 1249 case 0: 1250 Register = ARM::R0; 1251 break; 1252 case 1: 1253 Register = ARM::R1; 1254 break; 1255 case 2: 1256 Register = ARM::R2; 1257 break; 1258 case 3: 1259 Register = ARM::R3; 1260 break; 1261 case 9: 1262 Register = ARM::R9; 1263 break; 1264 case 12: 1265 Register = ARM::R12; 1266 break; 1267 default: 1268 return MCDisassembler::Fail; 1269 } 1270 1271 Inst.addOperand(MCOperand::createReg(Register)); 1272 return MCDisassembler::Success; 1273} 1274 1275static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1276 uint64_t Address, const void *Decoder) { 1277 DecodeStatus S = MCDisassembler::Success; 1278 1279 const FeatureBitset &featureBits = 1280 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1281 1282 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1283 S = MCDisassembler::SoftFail; 1284 1285 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1286 return S; 1287} 1288 1289static const uint16_t SPRDecoderTable[] = { 1290 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1291 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1292 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1293 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1294 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1295 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1296 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1297 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1298}; 1299 1300static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1301 uint64_t Address, const void *Decoder) { 1302 if (RegNo > 31) 1303 return MCDisassembler::Fail; 1304 1305 unsigned Register = SPRDecoderTable[RegNo]; 1306 Inst.addOperand(MCOperand::createReg(Register)); 1307 return MCDisassembler::Success; 1308} 1309 1310static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1311 uint64_t Address, const void *Decoder) { 1312 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1313} 1314 1315static const uint16_t DPRDecoderTable[] = { 1316 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1318 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1319 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1320 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1321 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1322 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1323 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1324}; 1325 1326static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1327 uint64_t Address, const void *Decoder) { 1328 const FeatureBitset &featureBits = 1329 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1330 1331 bool hasD32 = featureBits[ARM::FeatureD32]; 1332 1333 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1334 return MCDisassembler::Fail; 1335 1336 unsigned Register = DPRDecoderTable[RegNo]; 1337 Inst.addOperand(MCOperand::createReg(Register)); 1338 return MCDisassembler::Success; 1339} 1340 1341static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1342 uint64_t Address, const void *Decoder) { 1343 if (RegNo > 7) 1344 return MCDisassembler::Fail; 1345 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1346} 1347 1348static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1349 uint64_t Address, const void *Decoder) { 1350 if (RegNo > 15) 1351 return MCDisassembler::Fail; 1352 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1353} 1354 1355static DecodeStatus 1356DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1357 uint64_t Address, const void *Decoder) { 1358 if (RegNo > 15) 1359 return MCDisassembler::Fail; 1360 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1361} 1362 1363static const uint16_t QPRDecoderTable[] = { 1364 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1365 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1366 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1367 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1368}; 1369 1370static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1371 uint64_t Address, const void *Decoder) { 1372 if (RegNo > 31 || (RegNo & 1) != 0) 1373 return MCDisassembler::Fail; 1374 RegNo >>= 1; 1375 1376 unsigned Register = QPRDecoderTable[RegNo]; 1377 Inst.addOperand(MCOperand::createReg(Register)); 1378 return MCDisassembler::Success; 1379} 1380 1381static const uint16_t DPairDecoderTable[] = { 1382 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1384 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1385 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1386 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1387 ARM::Q15 1388}; 1389 1390static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1391 uint64_t Address, const void *Decoder) { 1392 if (RegNo > 30) 1393 return MCDisassembler::Fail; 1394 1395 unsigned Register = DPairDecoderTable[RegNo]; 1396 Inst.addOperand(MCOperand::createReg(Register)); 1397 return MCDisassembler::Success; 1398} 1399 1400static const uint16_t DPairSpacedDecoderTable[] = { 1401 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1402 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1403 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1404 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1405 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1406 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1407 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1408 ARM::D28_D30, ARM::D29_D31 1409}; 1410 1411static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1412 unsigned RegNo, 1413 uint64_t Address, 1414 const void *Decoder) { 1415 if (RegNo > 29) 1416 return MCDisassembler::Fail; 1417 1418 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1419 Inst.addOperand(MCOperand::createReg(Register)); 1420 return MCDisassembler::Success; 1421} 1422 1423static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1424 uint64_t Address, const void *Decoder) { 1425 DecodeStatus S = MCDisassembler::Success; 1426 if (Val == 0xF) return MCDisassembler::Fail; 1427 // AL predicate is not allowed on Thumb1 branches. 1428 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1429 return MCDisassembler::Fail; 1430 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1431 Check(S, MCDisassembler::SoftFail); 1432 Inst.addOperand(MCOperand::createImm(Val)); 1433 if (Val == ARMCC::AL) { 1434 Inst.addOperand(MCOperand::createReg(0)); 1435 } else 1436 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1437 return S; 1438} 1439 1440static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1441 uint64_t Address, const void *Decoder) { 1442 if (Val) 1443 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1444 else 1445 Inst.addOperand(MCOperand::createReg(0)); 1446 return MCDisassembler::Success; 1447} 1448 1449static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1450 uint64_t Address, const void *Decoder) { 1451 DecodeStatus S = MCDisassembler::Success; 1452 1453 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1454 unsigned type = fieldFromInstruction(Val, 5, 2); 1455 unsigned imm = fieldFromInstruction(Val, 7, 5); 1456 1457 // Register-immediate 1458 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1459 return MCDisassembler::Fail; 1460 1461 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1462 switch (type) { 1463 case 0: 1464 Shift = ARM_AM::lsl; 1465 break; 1466 case 1: 1467 Shift = ARM_AM::lsr; 1468 break; 1469 case 2: 1470 Shift = ARM_AM::asr; 1471 break; 1472 case 3: 1473 Shift = ARM_AM::ror; 1474 break; 1475 } 1476 1477 if (Shift == ARM_AM::ror && imm == 0) 1478 Shift = ARM_AM::rrx; 1479 1480 unsigned Op = Shift | (imm << 3); 1481 Inst.addOperand(MCOperand::createImm(Op)); 1482 1483 return S; 1484} 1485 1486static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1487 uint64_t Address, const void *Decoder) { 1488 DecodeStatus S = MCDisassembler::Success; 1489 1490 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1491 unsigned type = fieldFromInstruction(Val, 5, 2); 1492 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1493 1494 // Register-register 1495 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1496 return MCDisassembler::Fail; 1497 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1498 return MCDisassembler::Fail; 1499 1500 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1501 switch (type) { 1502 case 0: 1503 Shift = ARM_AM::lsl; 1504 break; 1505 case 1: 1506 Shift = ARM_AM::lsr; 1507 break; 1508 case 2: 1509 Shift = ARM_AM::asr; 1510 break; 1511 case 3: 1512 Shift = ARM_AM::ror; 1513 break; 1514 } 1515 1516 Inst.addOperand(MCOperand::createImm(Shift)); 1517 1518 return S; 1519} 1520 1521static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1522 uint64_t Address, const void *Decoder) { 1523 DecodeStatus S = MCDisassembler::Success; 1524 1525 bool NeedDisjointWriteback = false; 1526 unsigned WritebackReg = 0; 1527 bool CLRM = false; 1528 switch (Inst.getOpcode()) { 1529 default: 1530 break; 1531 case ARM::LDMIA_UPD: 1532 case ARM::LDMDB_UPD: 1533 case ARM::LDMIB_UPD: 1534 case ARM::LDMDA_UPD: 1535 case ARM::t2LDMIA_UPD: 1536 case ARM::t2LDMDB_UPD: 1537 case ARM::t2STMIA_UPD: 1538 case ARM::t2STMDB_UPD: 1539 NeedDisjointWriteback = true; 1540 WritebackReg = Inst.getOperand(0).getReg(); 1541 break; 1542 case ARM::t2CLRM: 1543 CLRM = true; 1544 break; 1545 } 1546 1547 // Empty register lists are not allowed. 1548 if (Val == 0) return MCDisassembler::Fail; 1549 for (unsigned i = 0; i < 16; ++i) { 1550 if (Val & (1 << i)) { 1551 if (CLRM) { 1552 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1553 return MCDisassembler::Fail; 1554 } 1555 } else { 1556 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1557 return MCDisassembler::Fail; 1558 // Writeback not allowed if Rn is in the target list. 1559 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1560 Check(S, MCDisassembler::SoftFail); 1561 } 1562 } 1563 } 1564 1565 return S; 1566} 1567 1568static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1569 uint64_t Address, const void *Decoder) { 1570 DecodeStatus S = MCDisassembler::Success; 1571 1572 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1573 unsigned regs = fieldFromInstruction(Val, 0, 8); 1574 1575 // In case of unpredictable encoding, tweak the operands. 1576 if (regs == 0 || (Vd + regs) > 32) { 1577 regs = Vd + regs > 32 ? 32 - Vd : regs; 1578 regs = std::max( 1u, regs); 1579 S = MCDisassembler::SoftFail; 1580 } 1581 1582 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1583 return MCDisassembler::Fail; 1584 for (unsigned i = 0; i < (regs - 1); ++i) { 1585 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 } 1588 1589 return S; 1590} 1591 1592static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1593 uint64_t Address, const void *Decoder) { 1594 DecodeStatus S = MCDisassembler::Success; 1595 1596 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1597 unsigned regs = fieldFromInstruction(Val, 1, 7); 1598 1599 // In case of unpredictable encoding, tweak the operands. 1600 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1601 regs = Vd + regs > 32 ? 32 - Vd : regs; 1602 regs = std::max( 1u, regs); 1603 regs = std::min(16u, regs); 1604 S = MCDisassembler::SoftFail; 1605 } 1606 1607 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1608 return MCDisassembler::Fail; 1609 for (unsigned i = 0; i < (regs - 1); ++i) { 1610 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1611 return MCDisassembler::Fail; 1612 } 1613 1614 return S; 1615} 1616 1617static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1618 uint64_t Address, const void *Decoder) { 1619 // This operand encodes a mask of contiguous zeros between a specified MSB 1620 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1621 // the mask of all bits LSB-and-lower, and then xor them to create 1622 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1623 // create the final mask. 1624 unsigned msb = fieldFromInstruction(Val, 5, 5); 1625 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1626 1627 DecodeStatus S = MCDisassembler::Success; 1628 if (lsb > msb) { 1629 Check(S, MCDisassembler::SoftFail); 1630 // The check above will cause the warning for the "potentially undefined 1631 // instruction encoding" but we can't build a bad MCOperand value here 1632 // with a lsb > msb or else printing the MCInst will cause a crash. 1633 lsb = msb; 1634 } 1635 1636 uint32_t msb_mask = 0xFFFFFFFF; 1637 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1638 uint32_t lsb_mask = (1U << lsb) - 1; 1639 1640 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1641 return S; 1642} 1643 1644static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1645 uint64_t Address, const void *Decoder) { 1646 DecodeStatus S = MCDisassembler::Success; 1647 1648 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1649 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1650 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1651 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1653 unsigned U = fieldFromInstruction(Insn, 23, 1); 1654 const FeatureBitset &featureBits = 1655 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1656 1657 switch (Inst.getOpcode()) { 1658 case ARM::LDC_OFFSET: 1659 case ARM::LDC_PRE: 1660 case ARM::LDC_POST: 1661 case ARM::LDC_OPTION: 1662 case ARM::LDCL_OFFSET: 1663 case ARM::LDCL_PRE: 1664 case ARM::LDCL_POST: 1665 case ARM::LDCL_OPTION: 1666 case ARM::STC_OFFSET: 1667 case ARM::STC_PRE: 1668 case ARM::STC_POST: 1669 case ARM::STC_OPTION: 1670 case ARM::STCL_OFFSET: 1671 case ARM::STCL_PRE: 1672 case ARM::STCL_POST: 1673 case ARM::STCL_OPTION: 1674 case ARM::t2LDC_OFFSET: 1675 case ARM::t2LDC_PRE: 1676 case ARM::t2LDC_POST: 1677 case ARM::t2LDC_OPTION: 1678 case ARM::t2LDCL_OFFSET: 1679 case ARM::t2LDCL_PRE: 1680 case ARM::t2LDCL_POST: 1681 case ARM::t2LDCL_OPTION: 1682 case ARM::t2STC_OFFSET: 1683 case ARM::t2STC_PRE: 1684 case ARM::t2STC_POST: 1685 case ARM::t2STC_OPTION: 1686 case ARM::t2STCL_OFFSET: 1687 case ARM::t2STCL_PRE: 1688 case ARM::t2STCL_POST: 1689 case ARM::t2STCL_OPTION: 1690 case ARM::t2LDC2_OFFSET: 1691 case ARM::t2LDC2L_OFFSET: 1692 case ARM::t2LDC2_PRE: 1693 case ARM::t2LDC2L_PRE: 1694 case ARM::t2STC2_OFFSET: 1695 case ARM::t2STC2L_OFFSET: 1696 case ARM::t2STC2_PRE: 1697 case ARM::t2STC2L_PRE: 1698 case ARM::LDC2_OFFSET: 1699 case ARM::LDC2L_OFFSET: 1700 case ARM::LDC2_PRE: 1701 case ARM::LDC2L_PRE: 1702 case ARM::STC2_OFFSET: 1703 case ARM::STC2L_OFFSET: 1704 case ARM::STC2_PRE: 1705 case ARM::STC2L_PRE: 1706 case ARM::t2LDC2_OPTION: 1707 case ARM::t2STC2_OPTION: 1708 case ARM::t2LDC2_POST: 1709 case ARM::t2LDC2L_POST: 1710 case ARM::t2STC2_POST: 1711 case ARM::t2STC2L_POST: 1712 case ARM::LDC2_POST: 1713 case ARM::LDC2L_POST: 1714 case ARM::STC2_POST: 1715 case ARM::STC2L_POST: 1716 if (coproc == 0xA || coproc == 0xB || 1717 (featureBits[ARM::HasV8_1MMainlineOps] && 1718 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1719 coproc == 0xE || coproc == 0xF))) 1720 return MCDisassembler::Fail; 1721 break; 1722 default: 1723 break; 1724 } 1725 1726 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1727 return MCDisassembler::Fail; 1728 1729 Inst.addOperand(MCOperand::createImm(coproc)); 1730 Inst.addOperand(MCOperand::createImm(CRd)); 1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1732 return MCDisassembler::Fail; 1733 1734 switch (Inst.getOpcode()) { 1735 case ARM::t2LDC2_OFFSET: 1736 case ARM::t2LDC2L_OFFSET: 1737 case ARM::t2LDC2_PRE: 1738 case ARM::t2LDC2L_PRE: 1739 case ARM::t2STC2_OFFSET: 1740 case ARM::t2STC2L_OFFSET: 1741 case ARM::t2STC2_PRE: 1742 case ARM::t2STC2L_PRE: 1743 case ARM::LDC2_OFFSET: 1744 case ARM::LDC2L_OFFSET: 1745 case ARM::LDC2_PRE: 1746 case ARM::LDC2L_PRE: 1747 case ARM::STC2_OFFSET: 1748 case ARM::STC2L_OFFSET: 1749 case ARM::STC2_PRE: 1750 case ARM::STC2L_PRE: 1751 case ARM::t2LDC_OFFSET: 1752 case ARM::t2LDCL_OFFSET: 1753 case ARM::t2LDC_PRE: 1754 case ARM::t2LDCL_PRE: 1755 case ARM::t2STC_OFFSET: 1756 case ARM::t2STCL_OFFSET: 1757 case ARM::t2STC_PRE: 1758 case ARM::t2STCL_PRE: 1759 case ARM::LDC_OFFSET: 1760 case ARM::LDCL_OFFSET: 1761 case ARM::LDC_PRE: 1762 case ARM::LDCL_PRE: 1763 case ARM::STC_OFFSET: 1764 case ARM::STCL_OFFSET: 1765 case ARM::STC_PRE: 1766 case ARM::STCL_PRE: 1767 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1768 Inst.addOperand(MCOperand::createImm(imm)); 1769 break; 1770 case ARM::t2LDC2_POST: 1771 case ARM::t2LDC2L_POST: 1772 case ARM::t2STC2_POST: 1773 case ARM::t2STC2L_POST: 1774 case ARM::LDC2_POST: 1775 case ARM::LDC2L_POST: 1776 case ARM::STC2_POST: 1777 case ARM::STC2L_POST: 1778 case ARM::t2LDC_POST: 1779 case ARM::t2LDCL_POST: 1780 case ARM::t2STC_POST: 1781 case ARM::t2STCL_POST: 1782 case ARM::LDC_POST: 1783 case ARM::LDCL_POST: 1784 case ARM::STC_POST: 1785 case ARM::STCL_POST: 1786 imm |= U << 8; 1787 LLVM_FALLTHROUGH; 1788 default: 1789 // The 'option' variant doesn't encode 'U' in the immediate since 1790 // the immediate is unsigned [0,255]. 1791 Inst.addOperand(MCOperand::createImm(imm)); 1792 break; 1793 } 1794 1795 switch (Inst.getOpcode()) { 1796 case ARM::LDC_OFFSET: 1797 case ARM::LDC_PRE: 1798 case ARM::LDC_POST: 1799 case ARM::LDC_OPTION: 1800 case ARM::LDCL_OFFSET: 1801 case ARM::LDCL_PRE: 1802 case ARM::LDCL_POST: 1803 case ARM::LDCL_OPTION: 1804 case ARM::STC_OFFSET: 1805 case ARM::STC_PRE: 1806 case ARM::STC_POST: 1807 case ARM::STC_OPTION: 1808 case ARM::STCL_OFFSET: 1809 case ARM::STCL_PRE: 1810 case ARM::STCL_POST: 1811 case ARM::STCL_OPTION: 1812 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1813 return MCDisassembler::Fail; 1814 break; 1815 default: 1816 break; 1817 } 1818 1819 return S; 1820} 1821 1822static DecodeStatus 1823DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1824 uint64_t Address, const void *Decoder) { 1825 DecodeStatus S = MCDisassembler::Success; 1826 1827 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1830 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1831 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1832 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1833 unsigned P = fieldFromInstruction(Insn, 24, 1); 1834 unsigned W = fieldFromInstruction(Insn, 21, 1); 1835 1836 // On stores, the writeback operand precedes Rt. 1837 switch (Inst.getOpcode()) { 1838 case ARM::STR_POST_IMM: 1839 case ARM::STR_POST_REG: 1840 case ARM::STRB_POST_IMM: 1841 case ARM::STRB_POST_REG: 1842 case ARM::STRT_POST_REG: 1843 case ARM::STRT_POST_IMM: 1844 case ARM::STRBT_POST_REG: 1845 case ARM::STRBT_POST_IMM: 1846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 break; 1849 default: 1850 break; 1851 } 1852 1853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1854 return MCDisassembler::Fail; 1855 1856 // On loads, the writeback operand comes after Rt. 1857 switch (Inst.getOpcode()) { 1858 case ARM::LDR_POST_IMM: 1859 case ARM::LDR_POST_REG: 1860 case ARM::LDRB_POST_IMM: 1861 case ARM::LDRB_POST_REG: 1862 case ARM::LDRBT_POST_REG: 1863 case ARM::LDRBT_POST_IMM: 1864 case ARM::LDRT_POST_REG: 1865 case ARM::LDRT_POST_IMM: 1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 break; 1869 default: 1870 break; 1871 } 1872 1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 1876 ARM_AM::AddrOpc Op = ARM_AM::add; 1877 if (!fieldFromInstruction(Insn, 23, 1)) 1878 Op = ARM_AM::sub; 1879 1880 bool writeback = (P == 0) || (W == 1); 1881 unsigned idx_mode = 0; 1882 if (P && writeback) 1883 idx_mode = ARMII::IndexModePre; 1884 else if (!P && writeback) 1885 idx_mode = ARMII::IndexModePost; 1886 1887 if (writeback && (Rn == 15 || Rn == Rt)) 1888 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1889 1890 if (reg) { 1891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1892 return MCDisassembler::Fail; 1893 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1894 switch( fieldFromInstruction(Insn, 5, 2)) { 1895 case 0: 1896 Opc = ARM_AM::lsl; 1897 break; 1898 case 1: 1899 Opc = ARM_AM::lsr; 1900 break; 1901 case 2: 1902 Opc = ARM_AM::asr; 1903 break; 1904 case 3: 1905 Opc = ARM_AM::ror; 1906 break; 1907 default: 1908 return MCDisassembler::Fail; 1909 } 1910 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1911 if (Opc == ARM_AM::ror && amt == 0) 1912 Opc = ARM_AM::rrx; 1913 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1914 1915 Inst.addOperand(MCOperand::createImm(imm)); 1916 } else { 1917 Inst.addOperand(MCOperand::createReg(0)); 1918 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1919 Inst.addOperand(MCOperand::createImm(tmp)); 1920 } 1921 1922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1923 return MCDisassembler::Fail; 1924 1925 return S; 1926} 1927 1928static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1929 uint64_t Address, const void *Decoder) { 1930 DecodeStatus S = MCDisassembler::Success; 1931 1932 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1933 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1934 unsigned type = fieldFromInstruction(Val, 5, 2); 1935 unsigned imm = fieldFromInstruction(Val, 7, 5); 1936 unsigned U = fieldFromInstruction(Val, 12, 1); 1937 1938 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1939 switch (type) { 1940 case 0: 1941 ShOp = ARM_AM::lsl; 1942 break; 1943 case 1: 1944 ShOp = ARM_AM::lsr; 1945 break; 1946 case 2: 1947 ShOp = ARM_AM::asr; 1948 break; 1949 case 3: 1950 ShOp = ARM_AM::ror; 1951 break; 1952 } 1953 1954 if (ShOp == ARM_AM::ror && imm == 0) 1955 ShOp = ARM_AM::rrx; 1956 1957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1958 return MCDisassembler::Fail; 1959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1960 return MCDisassembler::Fail; 1961 unsigned shift; 1962 if (U) 1963 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1964 else 1965 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1966 Inst.addOperand(MCOperand::createImm(shift)); 1967 1968 return S; 1969} 1970 1971static DecodeStatus 1972DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1973 uint64_t Address, const void *Decoder) { 1974 DecodeStatus S = MCDisassembler::Success; 1975 1976 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1977 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1978 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1979 unsigned type = fieldFromInstruction(Insn, 22, 1); 1980 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1981 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1982 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1983 unsigned W = fieldFromInstruction(Insn, 21, 1); 1984 unsigned P = fieldFromInstruction(Insn, 24, 1); 1985 unsigned Rt2 = Rt + 1; 1986 1987 bool writeback = (W == 1) | (P == 0); 1988 1989 // For {LD,ST}RD, Rt must be even, else undefined. 1990 switch (Inst.getOpcode()) { 1991 case ARM::STRD: 1992 case ARM::STRD_PRE: 1993 case ARM::STRD_POST: 1994 case ARM::LDRD: 1995 case ARM::LDRD_PRE: 1996 case ARM::LDRD_POST: 1997 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1998 break; 1999 default: 2000 break; 2001 } 2002 switch (Inst.getOpcode()) { 2003 case ARM::STRD: 2004 case ARM::STRD_PRE: 2005 case ARM::STRD_POST: 2006 if (P == 0 && W == 1) 2007 S = MCDisassembler::SoftFail; 2008 2009 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2010 S = MCDisassembler::SoftFail; 2011 if (type && Rm == 15) 2012 S = MCDisassembler::SoftFail; 2013 if (Rt2 == 15) 2014 S = MCDisassembler::SoftFail; 2015 if (!type && fieldFromInstruction(Insn, 8, 4)) 2016 S = MCDisassembler::SoftFail; 2017 break; 2018 case ARM::STRH: 2019 case ARM::STRH_PRE: 2020 case ARM::STRH_POST: 2021 if (Rt == 15) 2022 S = MCDisassembler::SoftFail; 2023 if (writeback && (Rn == 15 || Rn == Rt)) 2024 S = MCDisassembler::SoftFail; 2025 if (!type && Rm == 15) 2026 S = MCDisassembler::SoftFail; 2027 break; 2028 case ARM::LDRD: 2029 case ARM::LDRD_PRE: 2030 case ARM::LDRD_POST: 2031 if (type && Rn == 15) { 2032 if (Rt2 == 15) 2033 S = MCDisassembler::SoftFail; 2034 break; 2035 } 2036 if (P == 0 && W == 1) 2037 S = MCDisassembler::SoftFail; 2038 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2039 S = MCDisassembler::SoftFail; 2040 if (!type && writeback && Rn == 15) 2041 S = MCDisassembler::SoftFail; 2042 if (writeback && (Rn == Rt || Rn == Rt2)) 2043 S = MCDisassembler::SoftFail; 2044 break; 2045 case ARM::LDRH: 2046 case ARM::LDRH_PRE: 2047 case ARM::LDRH_POST: 2048 if (type && Rn == 15) { 2049 if (Rt == 15) 2050 S = MCDisassembler::SoftFail; 2051 break; 2052 } 2053 if (Rt == 15) 2054 S = MCDisassembler::SoftFail; 2055 if (!type && Rm == 15) 2056 S = MCDisassembler::SoftFail; 2057 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2058 S = MCDisassembler::SoftFail; 2059 break; 2060 case ARM::LDRSH: 2061 case ARM::LDRSH_PRE: 2062 case ARM::LDRSH_POST: 2063 case ARM::LDRSB: 2064 case ARM::LDRSB_PRE: 2065 case ARM::LDRSB_POST: 2066 if (type && Rn == 15) { 2067 if (Rt == 15) 2068 S = MCDisassembler::SoftFail; 2069 break; 2070 } 2071 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2072 S = MCDisassembler::SoftFail; 2073 if (!type && (Rt == 15 || Rm == 15)) 2074 S = MCDisassembler::SoftFail; 2075 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2076 S = MCDisassembler::SoftFail; 2077 break; 2078 default: 2079 break; 2080 } 2081 2082 if (writeback) { // Writeback 2083 if (P) 2084 U |= ARMII::IndexModePre << 9; 2085 else 2086 U |= ARMII::IndexModePost << 9; 2087 2088 // On stores, the writeback operand precedes Rt. 2089 switch (Inst.getOpcode()) { 2090 case ARM::STRD: 2091 case ARM::STRD_PRE: 2092 case ARM::STRD_POST: 2093 case ARM::STRH: 2094 case ARM::STRH_PRE: 2095 case ARM::STRH_POST: 2096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 break; 2099 default: 2100 break; 2101 } 2102 } 2103 2104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2105 return MCDisassembler::Fail; 2106 switch (Inst.getOpcode()) { 2107 case ARM::STRD: 2108 case ARM::STRD_PRE: 2109 case ARM::STRD_POST: 2110 case ARM::LDRD: 2111 case ARM::LDRD_PRE: 2112 case ARM::LDRD_POST: 2113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 break; 2116 default: 2117 break; 2118 } 2119 2120 if (writeback) { 2121 // On loads, the writeback operand comes after Rt. 2122 switch (Inst.getOpcode()) { 2123 case ARM::LDRD: 2124 case ARM::LDRD_PRE: 2125 case ARM::LDRD_POST: 2126 case ARM::LDRH: 2127 case ARM::LDRH_PRE: 2128 case ARM::LDRH_POST: 2129 case ARM::LDRSH: 2130 case ARM::LDRSH_PRE: 2131 case ARM::LDRSH_POST: 2132 case ARM::LDRSB: 2133 case ARM::LDRSB_PRE: 2134 case ARM::LDRSB_POST: 2135 case ARM::LDRHTr: 2136 case ARM::LDRSBTr: 2137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 break; 2140 default: 2141 break; 2142 } 2143 } 2144 2145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2146 return MCDisassembler::Fail; 2147 2148 if (type) { 2149 Inst.addOperand(MCOperand::createReg(0)); 2150 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2151 } else { 2152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2153 return MCDisassembler::Fail; 2154 Inst.addOperand(MCOperand::createImm(U)); 2155 } 2156 2157 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 2160 return S; 2161} 2162 2163static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2164 uint64_t Address, const void *Decoder) { 2165 DecodeStatus S = MCDisassembler::Success; 2166 2167 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2168 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2169 2170 switch (mode) { 2171 case 0: 2172 mode = ARM_AM::da; 2173 break; 2174 case 1: 2175 mode = ARM_AM::ia; 2176 break; 2177 case 2: 2178 mode = ARM_AM::db; 2179 break; 2180 case 3: 2181 mode = ARM_AM::ib; 2182 break; 2183 } 2184 2185 Inst.addOperand(MCOperand::createImm(mode)); 2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2187 return MCDisassembler::Fail; 2188 2189 return S; 2190} 2191 2192static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2193 uint64_t Address, const void *Decoder) { 2194 DecodeStatus S = MCDisassembler::Success; 2195 2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2197 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2198 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2199 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2200 2201 if (pred == 0xF) 2202 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2203 2204 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 return S; 2213} 2214 2215static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2216 unsigned Insn, 2217 uint64_t Address, const void *Decoder) { 2218 DecodeStatus S = MCDisassembler::Success; 2219 2220 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2221 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2222 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2223 2224 if (pred == 0xF) { 2225 // Ambiguous with RFE and SRS 2226 switch (Inst.getOpcode()) { 2227 case ARM::LDMDA: 2228 Inst.setOpcode(ARM::RFEDA); 2229 break; 2230 case ARM::LDMDA_UPD: 2231 Inst.setOpcode(ARM::RFEDA_UPD); 2232 break; 2233 case ARM::LDMDB: 2234 Inst.setOpcode(ARM::RFEDB); 2235 break; 2236 case ARM::LDMDB_UPD: 2237 Inst.setOpcode(ARM::RFEDB_UPD); 2238 break; 2239 case ARM::LDMIA: 2240 Inst.setOpcode(ARM::RFEIA); 2241 break; 2242 case ARM::LDMIA_UPD: 2243 Inst.setOpcode(ARM::RFEIA_UPD); 2244 break; 2245 case ARM::LDMIB: 2246 Inst.setOpcode(ARM::RFEIB); 2247 break; 2248 case ARM::LDMIB_UPD: 2249 Inst.setOpcode(ARM::RFEIB_UPD); 2250 break; 2251 case ARM::STMDA: 2252 Inst.setOpcode(ARM::SRSDA); 2253 break; 2254 case ARM::STMDA_UPD: 2255 Inst.setOpcode(ARM::SRSDA_UPD); 2256 break; 2257 case ARM::STMDB: 2258 Inst.setOpcode(ARM::SRSDB); 2259 break; 2260 case ARM::STMDB_UPD: 2261 Inst.setOpcode(ARM::SRSDB_UPD); 2262 break; 2263 case ARM::STMIA: 2264 Inst.setOpcode(ARM::SRSIA); 2265 break; 2266 case ARM::STMIA_UPD: 2267 Inst.setOpcode(ARM::SRSIA_UPD); 2268 break; 2269 case ARM::STMIB: 2270 Inst.setOpcode(ARM::SRSIB); 2271 break; 2272 case ARM::STMIB_UPD: 2273 Inst.setOpcode(ARM::SRSIB_UPD); 2274 break; 2275 default: 2276 return MCDisassembler::Fail; 2277 } 2278 2279 // For stores (which become SRS's, the only operand is the mode. 2280 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2281 // Check SRS encoding constraints 2282 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2283 fieldFromInstruction(Insn, 20, 1) == 0)) 2284 return MCDisassembler::Fail; 2285 2286 Inst.addOperand( 2287 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2288 return S; 2289 } 2290 2291 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2292 } 2293 2294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2297 return MCDisassembler::Fail; // Tied 2298 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 2303 return S; 2304} 2305 2306// Check for UNPREDICTABLE predicated ESB instruction 2307static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2308 uint64_t Address, const void *Decoder) { 2309 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2310 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2311 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2312 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2313 2314 DecodeStatus S = MCDisassembler::Success; 2315 2316 Inst.addOperand(MCOperand::createImm(imm8)); 2317 2318 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 2321 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2322 // so all predicates should be allowed. 2323 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2324 S = MCDisassembler::SoftFail; 2325 2326 return S; 2327} 2328 2329static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2330 uint64_t Address, const void *Decoder) { 2331 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2332 unsigned M = fieldFromInstruction(Insn, 17, 1); 2333 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2334 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2335 2336 DecodeStatus S = MCDisassembler::Success; 2337 2338 // This decoder is called from multiple location that do not check 2339 // the full encoding is valid before they do. 2340 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2341 fieldFromInstruction(Insn, 16, 1) != 0 || 2342 fieldFromInstruction(Insn, 20, 8) != 0x10) 2343 return MCDisassembler::Fail; 2344 2345 // imod == '01' --> UNPREDICTABLE 2346 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2347 // return failure here. The '01' imod value is unprintable, so there's 2348 // nothing useful we could do even if we returned UNPREDICTABLE. 2349 2350 if (imod == 1) return MCDisassembler::Fail; 2351 2352 if (imod && M) { 2353 Inst.setOpcode(ARM::CPS3p); 2354 Inst.addOperand(MCOperand::createImm(imod)); 2355 Inst.addOperand(MCOperand::createImm(iflags)); 2356 Inst.addOperand(MCOperand::createImm(mode)); 2357 } else if (imod && !M) { 2358 Inst.setOpcode(ARM::CPS2p); 2359 Inst.addOperand(MCOperand::createImm(imod)); 2360 Inst.addOperand(MCOperand::createImm(iflags)); 2361 if (mode) S = MCDisassembler::SoftFail; 2362 } else if (!imod && M) { 2363 Inst.setOpcode(ARM::CPS1p); 2364 Inst.addOperand(MCOperand::createImm(mode)); 2365 if (iflags) S = MCDisassembler::SoftFail; 2366 } else { 2367 // imod == '00' && M == '0' --> UNPREDICTABLE 2368 Inst.setOpcode(ARM::CPS1p); 2369 Inst.addOperand(MCOperand::createImm(mode)); 2370 S = MCDisassembler::SoftFail; 2371 } 2372 2373 return S; 2374} 2375 2376static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2377 uint64_t Address, const void *Decoder) { 2378 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2379 unsigned M = fieldFromInstruction(Insn, 8, 1); 2380 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2381 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2382 2383 DecodeStatus S = MCDisassembler::Success; 2384 2385 // imod == '01' --> UNPREDICTABLE 2386 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2387 // return failure here. The '01' imod value is unprintable, so there's 2388 // nothing useful we could do even if we returned UNPREDICTABLE. 2389 2390 if (imod == 1) return MCDisassembler::Fail; 2391 2392 if (imod && M) { 2393 Inst.setOpcode(ARM::t2CPS3p); 2394 Inst.addOperand(MCOperand::createImm(imod)); 2395 Inst.addOperand(MCOperand::createImm(iflags)); 2396 Inst.addOperand(MCOperand::createImm(mode)); 2397 } else if (imod && !M) { 2398 Inst.setOpcode(ARM::t2CPS2p); 2399 Inst.addOperand(MCOperand::createImm(imod)); 2400 Inst.addOperand(MCOperand::createImm(iflags)); 2401 if (mode) S = MCDisassembler::SoftFail; 2402 } else if (!imod && M) { 2403 Inst.setOpcode(ARM::t2CPS1p); 2404 Inst.addOperand(MCOperand::createImm(mode)); 2405 if (iflags) S = MCDisassembler::SoftFail; 2406 } else { 2407 // imod == '00' && M == '0' --> this is a HINT instruction 2408 int imm = fieldFromInstruction(Insn, 0, 8); 2409 // HINT are defined only for immediate in [0..4] 2410 if(imm > 4) return MCDisassembler::Fail; 2411 Inst.setOpcode(ARM::t2HINT); 2412 Inst.addOperand(MCOperand::createImm(imm)); 2413 } 2414 2415 return S; 2416} 2417 2418static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2419 uint64_t Address, const void *Decoder) { 2420 DecodeStatus S = MCDisassembler::Success; 2421 2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2423 unsigned imm = 0; 2424 2425 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2426 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2427 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2428 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2429 2430 if (Inst.getOpcode() == ARM::t2MOVTi16) 2431 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2434 return MCDisassembler::Fail; 2435 2436 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2437 Inst.addOperand(MCOperand::createImm(imm)); 2438 2439 return S; 2440} 2441 2442static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2443 uint64_t Address, const void *Decoder) { 2444 DecodeStatus S = MCDisassembler::Success; 2445 2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2447 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2448 unsigned imm = 0; 2449 2450 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2451 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2452 2453 if (Inst.getOpcode() == ARM::MOVTi16) 2454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 2457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 2460 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2461 Inst.addOperand(MCOperand::createImm(imm)); 2462 2463 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 2466 return S; 2467} 2468 2469static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2470 uint64_t Address, const void *Decoder) { 2471 DecodeStatus S = MCDisassembler::Success; 2472 2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2474 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2475 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2476 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2477 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2478 2479 if (pred == 0xF) 2480 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2481 2482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2483 return MCDisassembler::Fail; 2484 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2485 return MCDisassembler::Fail; 2486 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2487 return MCDisassembler::Fail; 2488 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 2491 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 2494 return S; 2495} 2496 2497static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2498 uint64_t Address, const void *Decoder) { 2499 DecodeStatus S = MCDisassembler::Success; 2500 2501 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2502 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2503 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2504 2505 if (Pred == 0xF) 2506 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2507 2508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2509 return MCDisassembler::Fail; 2510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2511 return MCDisassembler::Fail; 2512 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 2515 return S; 2516} 2517 2518static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2519 uint64_t Address, const void *Decoder) { 2520 DecodeStatus S = MCDisassembler::Success; 2521 2522 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2523 2524 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2525 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2526 2527 if (!FeatureBits[ARM::HasV8_1aOps] || 2528 !FeatureBits[ARM::HasV8Ops]) 2529 return MCDisassembler::Fail; 2530 2531 // Decoder can be called from DecodeTST, which does not check the full 2532 // encoding is valid. 2533 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2534 fieldFromInstruction(Insn, 4,4) != 0) 2535 return MCDisassembler::Fail; 2536 if (fieldFromInstruction(Insn, 10,10) != 0 || 2537 fieldFromInstruction(Insn, 0,4) != 0) 2538 S = MCDisassembler::SoftFail; 2539 2540 Inst.setOpcode(ARM::SETPAN); 2541 Inst.addOperand(MCOperand::createImm(Imm)); 2542 2543 return S; 2544} 2545 2546static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2547 uint64_t Address, const void *Decoder) { 2548 DecodeStatus S = MCDisassembler::Success; 2549 2550 unsigned add = fieldFromInstruction(Val, 12, 1); 2551 unsigned imm = fieldFromInstruction(Val, 0, 12); 2552 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2553 2554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 2557 if (!add) imm *= -1; 2558 if (imm == 0 && !add) imm = INT32_MIN; 2559 Inst.addOperand(MCOperand::createImm(imm)); 2560 if (Rn == 15) 2561 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2562 2563 return S; 2564} 2565 2566static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2567 uint64_t Address, const void *Decoder) { 2568 DecodeStatus S = MCDisassembler::Success; 2569 2570 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2571 // U == 1 to add imm, 0 to subtract it. 2572 unsigned U = fieldFromInstruction(Val, 8, 1); 2573 unsigned imm = fieldFromInstruction(Val, 0, 8); 2574 2575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 2578 if (U) 2579 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2580 else 2581 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2582 2583 return S; 2584} 2585 2586static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2587 uint64_t Address, const void *Decoder) { 2588 DecodeStatus S = MCDisassembler::Success; 2589 2590 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2591 // U == 1 to add imm, 0 to subtract it. 2592 unsigned U = fieldFromInstruction(Val, 8, 1); 2593 unsigned imm = fieldFromInstruction(Val, 0, 8); 2594 2595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 2598 if (U) 2599 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2600 else 2601 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2602 2603 return S; 2604} 2605 2606static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2607 uint64_t Address, const void *Decoder) { 2608 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2609} 2610 2611static DecodeStatus 2612DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2613 uint64_t Address, const void *Decoder) { 2614 DecodeStatus Status = MCDisassembler::Success; 2615 2616 // Note the J1 and J2 values are from the encoded instruction. So here 2617 // change them to I1 and I2 values via as documented: 2618 // I1 = NOT(J1 EOR S); 2619 // I2 = NOT(J2 EOR S); 2620 // and build the imm32 with one trailing zero as documented: 2621 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2622 unsigned S = fieldFromInstruction(Insn, 26, 1); 2623 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2624 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2625 unsigned I1 = !(J1 ^ S); 2626 unsigned I2 = !(J2 ^ S); 2627 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2628 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2629 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2630 int imm32 = SignExtend32<25>(tmp << 1); 2631 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2632 true, 4, Inst, Decoder)) 2633 Inst.addOperand(MCOperand::createImm(imm32)); 2634 2635 return Status; 2636} 2637 2638static DecodeStatus 2639DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2640 uint64_t Address, const void *Decoder) { 2641 DecodeStatus S = MCDisassembler::Success; 2642 2643 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2644 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2645 2646 if (pred == 0xF) { 2647 Inst.setOpcode(ARM::BLXi); 2648 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2649 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2650 true, 4, Inst, Decoder)) 2651 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2652 return S; 2653 } 2654 2655 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2656 true, 4, Inst, Decoder)) 2657 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2658 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 2661 return S; 2662} 2663 2664static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2665 uint64_t Address, const void *Decoder) { 2666 DecodeStatus S = MCDisassembler::Success; 2667 2668 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2669 unsigned align = fieldFromInstruction(Val, 4, 2); 2670 2671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 if (!align) 2674 Inst.addOperand(MCOperand::createImm(0)); 2675 else 2676 Inst.addOperand(MCOperand::createImm(4 << align)); 2677 2678 return S; 2679} 2680 2681static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2682 uint64_t Address, const void *Decoder) { 2683 DecodeStatus S = MCDisassembler::Success; 2684 2685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2686 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2687 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2688 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2689 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2690 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2691 2692 // First output register 2693 switch (Inst.getOpcode()) { 2694 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2695 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2696 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2697 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2698 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2699 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2700 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2701 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2702 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2703 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 break; 2706 case ARM::VLD2b16: 2707 case ARM::VLD2b32: 2708 case ARM::VLD2b8: 2709 case ARM::VLD2b16wb_fixed: 2710 case ARM::VLD2b16wb_register: 2711 case ARM::VLD2b32wb_fixed: 2712 case ARM::VLD2b32wb_register: 2713 case ARM::VLD2b8wb_fixed: 2714 case ARM::VLD2b8wb_register: 2715 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 break; 2718 default: 2719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 } 2722 2723 // Second output register 2724 switch (Inst.getOpcode()) { 2725 case ARM::VLD3d8: 2726 case ARM::VLD3d16: 2727 case ARM::VLD3d32: 2728 case ARM::VLD3d8_UPD: 2729 case ARM::VLD3d16_UPD: 2730 case ARM::VLD3d32_UPD: 2731 case ARM::VLD4d8: 2732 case ARM::VLD4d16: 2733 case ARM::VLD4d32: 2734 case ARM::VLD4d8_UPD: 2735 case ARM::VLD4d16_UPD: 2736 case ARM::VLD4d32_UPD: 2737 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 case ARM::VLD3q8: 2741 case ARM::VLD3q16: 2742 case ARM::VLD3q32: 2743 case ARM::VLD3q8_UPD: 2744 case ARM::VLD3q16_UPD: 2745 case ARM::VLD3q32_UPD: 2746 case ARM::VLD4q8: 2747 case ARM::VLD4q16: 2748 case ARM::VLD4q32: 2749 case ARM::VLD4q8_UPD: 2750 case ARM::VLD4q16_UPD: 2751 case ARM::VLD4q32_UPD: 2752 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 break; 2755 default: 2756 break; 2757 } 2758 2759 // Third output register 2760 switch(Inst.getOpcode()) { 2761 case ARM::VLD3d8: 2762 case ARM::VLD3d16: 2763 case ARM::VLD3d32: 2764 case ARM::VLD3d8_UPD: 2765 case ARM::VLD3d16_UPD: 2766 case ARM::VLD3d32_UPD: 2767 case ARM::VLD4d8: 2768 case ARM::VLD4d16: 2769 case ARM::VLD4d32: 2770 case ARM::VLD4d8_UPD: 2771 case ARM::VLD4d16_UPD: 2772 case ARM::VLD4d32_UPD: 2773 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 break; 2776 case ARM::VLD3q8: 2777 case ARM::VLD3q16: 2778 case ARM::VLD3q32: 2779 case ARM::VLD3q8_UPD: 2780 case ARM::VLD3q16_UPD: 2781 case ARM::VLD3q32_UPD: 2782 case ARM::VLD4q8: 2783 case ARM::VLD4q16: 2784 case ARM::VLD4q32: 2785 case ARM::VLD4q8_UPD: 2786 case ARM::VLD4q16_UPD: 2787 case ARM::VLD4q32_UPD: 2788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 default: 2792 break; 2793 } 2794 2795 // Fourth output register 2796 switch (Inst.getOpcode()) { 2797 case ARM::VLD4d8: 2798 case ARM::VLD4d16: 2799 case ARM::VLD4d32: 2800 case ARM::VLD4d8_UPD: 2801 case ARM::VLD4d16_UPD: 2802 case ARM::VLD4d32_UPD: 2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 break; 2806 case ARM::VLD4q8: 2807 case ARM::VLD4q16: 2808 case ARM::VLD4q32: 2809 case ARM::VLD4q8_UPD: 2810 case ARM::VLD4q16_UPD: 2811 case ARM::VLD4q32_UPD: 2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 break; 2815 default: 2816 break; 2817 } 2818 2819 // Writeback operand 2820 switch (Inst.getOpcode()) { 2821 case ARM::VLD1d8wb_fixed: 2822 case ARM::VLD1d16wb_fixed: 2823 case ARM::VLD1d32wb_fixed: 2824 case ARM::VLD1d64wb_fixed: 2825 case ARM::VLD1d8wb_register: 2826 case ARM::VLD1d16wb_register: 2827 case ARM::VLD1d32wb_register: 2828 case ARM::VLD1d64wb_register: 2829 case ARM::VLD1q8wb_fixed: 2830 case ARM::VLD1q16wb_fixed: 2831 case ARM::VLD1q32wb_fixed: 2832 case ARM::VLD1q64wb_fixed: 2833 case ARM::VLD1q8wb_register: 2834 case ARM::VLD1q16wb_register: 2835 case ARM::VLD1q32wb_register: 2836 case ARM::VLD1q64wb_register: 2837 case ARM::VLD1d8Twb_fixed: 2838 case ARM::VLD1d8Twb_register: 2839 case ARM::VLD1d16Twb_fixed: 2840 case ARM::VLD1d16Twb_register: 2841 case ARM::VLD1d32Twb_fixed: 2842 case ARM::VLD1d32Twb_register: 2843 case ARM::VLD1d64Twb_fixed: 2844 case ARM::VLD1d64Twb_register: 2845 case ARM::VLD1d8Qwb_fixed: 2846 case ARM::VLD1d8Qwb_register: 2847 case ARM::VLD1d16Qwb_fixed: 2848 case ARM::VLD1d16Qwb_register: 2849 case ARM::VLD1d32Qwb_fixed: 2850 case ARM::VLD1d32Qwb_register: 2851 case ARM::VLD1d64Qwb_fixed: 2852 case ARM::VLD1d64Qwb_register: 2853 case ARM::VLD2d8wb_fixed: 2854 case ARM::VLD2d16wb_fixed: 2855 case ARM::VLD2d32wb_fixed: 2856 case ARM::VLD2q8wb_fixed: 2857 case ARM::VLD2q16wb_fixed: 2858 case ARM::VLD2q32wb_fixed: 2859 case ARM::VLD2d8wb_register: 2860 case ARM::VLD2d16wb_register: 2861 case ARM::VLD2d32wb_register: 2862 case ARM::VLD2q8wb_register: 2863 case ARM::VLD2q16wb_register: 2864 case ARM::VLD2q32wb_register: 2865 case ARM::VLD2b8wb_fixed: 2866 case ARM::VLD2b16wb_fixed: 2867 case ARM::VLD2b32wb_fixed: 2868 case ARM::VLD2b8wb_register: 2869 case ARM::VLD2b16wb_register: 2870 case ARM::VLD2b32wb_register: 2871 Inst.addOperand(MCOperand::createImm(0)); 2872 break; 2873 case ARM::VLD3d8_UPD: 2874 case ARM::VLD3d16_UPD: 2875 case ARM::VLD3d32_UPD: 2876 case ARM::VLD3q8_UPD: 2877 case ARM::VLD3q16_UPD: 2878 case ARM::VLD3q32_UPD: 2879 case ARM::VLD4d8_UPD: 2880 case ARM::VLD4d16_UPD: 2881 case ARM::VLD4d32_UPD: 2882 case ARM::VLD4q8_UPD: 2883 case ARM::VLD4q16_UPD: 2884 case ARM::VLD4q32_UPD: 2885 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 break; 2888 default: 2889 break; 2890 } 2891 2892 // AddrMode6 Base (register+alignment) 2893 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 2896 // AddrMode6 Offset (register) 2897 switch (Inst.getOpcode()) { 2898 default: 2899 // The below have been updated to have explicit am6offset split 2900 // between fixed and register offset. For those instructions not 2901 // yet updated, we need to add an additional reg0 operand for the 2902 // fixed variant. 2903 // 2904 // The fixed offset encodes as Rm == 0xd, so we check for that. 2905 if (Rm == 0xd) { 2906 Inst.addOperand(MCOperand::createReg(0)); 2907 break; 2908 } 2909 // Fall through to handle the register offset variant. 2910 LLVM_FALLTHROUGH; 2911 case ARM::VLD1d8wb_fixed: 2912 case ARM::VLD1d16wb_fixed: 2913 case ARM::VLD1d32wb_fixed: 2914 case ARM::VLD1d64wb_fixed: 2915 case ARM::VLD1d8Twb_fixed: 2916 case ARM::VLD1d16Twb_fixed: 2917 case ARM::VLD1d32Twb_fixed: 2918 case ARM::VLD1d64Twb_fixed: 2919 case ARM::VLD1d8Qwb_fixed: 2920 case ARM::VLD1d16Qwb_fixed: 2921 case ARM::VLD1d32Qwb_fixed: 2922 case ARM::VLD1d64Qwb_fixed: 2923 case ARM::VLD1d8wb_register: 2924 case ARM::VLD1d16wb_register: 2925 case ARM::VLD1d32wb_register: 2926 case ARM::VLD1d64wb_register: 2927 case ARM::VLD1q8wb_fixed: 2928 case ARM::VLD1q16wb_fixed: 2929 case ARM::VLD1q32wb_fixed: 2930 case ARM::VLD1q64wb_fixed: 2931 case ARM::VLD1q8wb_register: 2932 case ARM::VLD1q16wb_register: 2933 case ARM::VLD1q32wb_register: 2934 case ARM::VLD1q64wb_register: 2935 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2936 // variant encodes Rm == 0xf. Anything else is a register offset post- 2937 // increment and we need to add the register operand to the instruction. 2938 if (Rm != 0xD && Rm != 0xF && 2939 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2940 return MCDisassembler::Fail; 2941 break; 2942 case ARM::VLD2d8wb_fixed: 2943 case ARM::VLD2d16wb_fixed: 2944 case ARM::VLD2d32wb_fixed: 2945 case ARM::VLD2b8wb_fixed: 2946 case ARM::VLD2b16wb_fixed: 2947 case ARM::VLD2b32wb_fixed: 2948 case ARM::VLD2q8wb_fixed: 2949 case ARM::VLD2q16wb_fixed: 2950 case ARM::VLD2q32wb_fixed: 2951 break; 2952 } 2953 2954 return S; 2955} 2956 2957static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2958 uint64_t Address, const void *Decoder) { 2959 unsigned type = fieldFromInstruction(Insn, 8, 4); 2960 unsigned align = fieldFromInstruction(Insn, 4, 2); 2961 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2962 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2963 if (type == 10 && align == 3) return MCDisassembler::Fail; 2964 2965 unsigned load = fieldFromInstruction(Insn, 21, 1); 2966 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2967 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2968} 2969 2970static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2971 uint64_t Address, const void *Decoder) { 2972 unsigned size = fieldFromInstruction(Insn, 6, 2); 2973 if (size == 3) return MCDisassembler::Fail; 2974 2975 unsigned type = fieldFromInstruction(Insn, 8, 4); 2976 unsigned align = fieldFromInstruction(Insn, 4, 2); 2977 if (type == 8 && align == 3) return MCDisassembler::Fail; 2978 if (type == 9 && align == 3) return MCDisassembler::Fail; 2979 2980 unsigned load = fieldFromInstruction(Insn, 21, 1); 2981 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2982 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2983} 2984 2985static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2986 uint64_t Address, const void *Decoder) { 2987 unsigned size = fieldFromInstruction(Insn, 6, 2); 2988 if (size == 3) return MCDisassembler::Fail; 2989 2990 unsigned align = fieldFromInstruction(Insn, 4, 2); 2991 if (align & 2) return MCDisassembler::Fail; 2992 2993 unsigned load = fieldFromInstruction(Insn, 21, 1); 2994 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2995 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2996} 2997 2998static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2999 uint64_t Address, const void *Decoder) { 3000 unsigned size = fieldFromInstruction(Insn, 6, 2); 3001 if (size == 3) return MCDisassembler::Fail; 3002 3003 unsigned load = fieldFromInstruction(Insn, 21, 1); 3004 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3005 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3006} 3007 3008static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3009 uint64_t Address, const void *Decoder) { 3010 DecodeStatus S = MCDisassembler::Success; 3011 3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3013 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3014 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3015 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3016 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3017 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3018 3019 // Writeback Operand 3020 switch (Inst.getOpcode()) { 3021 case ARM::VST1d8wb_fixed: 3022 case ARM::VST1d16wb_fixed: 3023 case ARM::VST1d32wb_fixed: 3024 case ARM::VST1d64wb_fixed: 3025 case ARM::VST1d8wb_register: 3026 case ARM::VST1d16wb_register: 3027 case ARM::VST1d32wb_register: 3028 case ARM::VST1d64wb_register: 3029 case ARM::VST1q8wb_fixed: 3030 case ARM::VST1q16wb_fixed: 3031 case ARM::VST1q32wb_fixed: 3032 case ARM::VST1q64wb_fixed: 3033 case ARM::VST1q8wb_register: 3034 case ARM::VST1q16wb_register: 3035 case ARM::VST1q32wb_register: 3036 case ARM::VST1q64wb_register: 3037 case ARM::VST1d8Twb_fixed: 3038 case ARM::VST1d16Twb_fixed: 3039 case ARM::VST1d32Twb_fixed: 3040 case ARM::VST1d64Twb_fixed: 3041 case ARM::VST1d8Twb_register: 3042 case ARM::VST1d16Twb_register: 3043 case ARM::VST1d32Twb_register: 3044 case ARM::VST1d64Twb_register: 3045 case ARM::VST1d8Qwb_fixed: 3046 case ARM::VST1d16Qwb_fixed: 3047 case ARM::VST1d32Qwb_fixed: 3048 case ARM::VST1d64Qwb_fixed: 3049 case ARM::VST1d8Qwb_register: 3050 case ARM::VST1d16Qwb_register: 3051 case ARM::VST1d32Qwb_register: 3052 case ARM::VST1d64Qwb_register: 3053 case ARM::VST2d8wb_fixed: 3054 case ARM::VST2d16wb_fixed: 3055 case ARM::VST2d32wb_fixed: 3056 case ARM::VST2d8wb_register: 3057 case ARM::VST2d16wb_register: 3058 case ARM::VST2d32wb_register: 3059 case ARM::VST2q8wb_fixed: 3060 case ARM::VST2q16wb_fixed: 3061 case ARM::VST2q32wb_fixed: 3062 case ARM::VST2q8wb_register: 3063 case ARM::VST2q16wb_register: 3064 case ARM::VST2q32wb_register: 3065 case ARM::VST2b8wb_fixed: 3066 case ARM::VST2b16wb_fixed: 3067 case ARM::VST2b32wb_fixed: 3068 case ARM::VST2b8wb_register: 3069 case ARM::VST2b16wb_register: 3070 case ARM::VST2b32wb_register: 3071 if (Rm == 0xF) 3072 return MCDisassembler::Fail; 3073 Inst.addOperand(MCOperand::createImm(0)); 3074 break; 3075 case ARM::VST3d8_UPD: 3076 case ARM::VST3d16_UPD: 3077 case ARM::VST3d32_UPD: 3078 case ARM::VST3q8_UPD: 3079 case ARM::VST3q16_UPD: 3080 case ARM::VST3q32_UPD: 3081 case ARM::VST4d8_UPD: 3082 case ARM::VST4d16_UPD: 3083 case ARM::VST4d32_UPD: 3084 case ARM::VST4q8_UPD: 3085 case ARM::VST4q16_UPD: 3086 case ARM::VST4q32_UPD: 3087 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 break; 3090 default: 3091 break; 3092 } 3093 3094 // AddrMode6 Base (register+alignment) 3095 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 3098 // AddrMode6 Offset (register) 3099 switch (Inst.getOpcode()) { 3100 default: 3101 if (Rm == 0xD) 3102 Inst.addOperand(MCOperand::createReg(0)); 3103 else if (Rm != 0xF) { 3104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3105 return MCDisassembler::Fail; 3106 } 3107 break; 3108 case ARM::VST1d8wb_fixed: 3109 case ARM::VST1d16wb_fixed: 3110 case ARM::VST1d32wb_fixed: 3111 case ARM::VST1d64wb_fixed: 3112 case ARM::VST1q8wb_fixed: 3113 case ARM::VST1q16wb_fixed: 3114 case ARM::VST1q32wb_fixed: 3115 case ARM::VST1q64wb_fixed: 3116 case ARM::VST1d8Twb_fixed: 3117 case ARM::VST1d16Twb_fixed: 3118 case ARM::VST1d32Twb_fixed: 3119 case ARM::VST1d64Twb_fixed: 3120 case ARM::VST1d8Qwb_fixed: 3121 case ARM::VST1d16Qwb_fixed: 3122 case ARM::VST1d32Qwb_fixed: 3123 case ARM::VST1d64Qwb_fixed: 3124 case ARM::VST2d8wb_fixed: 3125 case ARM::VST2d16wb_fixed: 3126 case ARM::VST2d32wb_fixed: 3127 case ARM::VST2q8wb_fixed: 3128 case ARM::VST2q16wb_fixed: 3129 case ARM::VST2q32wb_fixed: 3130 case ARM::VST2b8wb_fixed: 3131 case ARM::VST2b16wb_fixed: 3132 case ARM::VST2b32wb_fixed: 3133 break; 3134 } 3135 3136 // First input register 3137 switch (Inst.getOpcode()) { 3138 case ARM::VST1q16: 3139 case ARM::VST1q32: 3140 case ARM::VST1q64: 3141 case ARM::VST1q8: 3142 case ARM::VST1q16wb_fixed: 3143 case ARM::VST1q16wb_register: 3144 case ARM::VST1q32wb_fixed: 3145 case ARM::VST1q32wb_register: 3146 case ARM::VST1q64wb_fixed: 3147 case ARM::VST1q64wb_register: 3148 case ARM::VST1q8wb_fixed: 3149 case ARM::VST1q8wb_register: 3150 case ARM::VST2d16: 3151 case ARM::VST2d32: 3152 case ARM::VST2d8: 3153 case ARM::VST2d16wb_fixed: 3154 case ARM::VST2d16wb_register: 3155 case ARM::VST2d32wb_fixed: 3156 case ARM::VST2d32wb_register: 3157 case ARM::VST2d8wb_fixed: 3158 case ARM::VST2d8wb_register: 3159 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 break; 3162 case ARM::VST2b16: 3163 case ARM::VST2b32: 3164 case ARM::VST2b8: 3165 case ARM::VST2b16wb_fixed: 3166 case ARM::VST2b16wb_register: 3167 case ARM::VST2b32wb_fixed: 3168 case ARM::VST2b32wb_register: 3169 case ARM::VST2b8wb_fixed: 3170 case ARM::VST2b8wb_register: 3171 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 break; 3174 default: 3175 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 } 3178 3179 // Second input register 3180 switch (Inst.getOpcode()) { 3181 case ARM::VST3d8: 3182 case ARM::VST3d16: 3183 case ARM::VST3d32: 3184 case ARM::VST3d8_UPD: 3185 case ARM::VST3d16_UPD: 3186 case ARM::VST3d32_UPD: 3187 case ARM::VST4d8: 3188 case ARM::VST4d16: 3189 case ARM::VST4d32: 3190 case ARM::VST4d8_UPD: 3191 case ARM::VST4d16_UPD: 3192 case ARM::VST4d32_UPD: 3193 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 break; 3196 case ARM::VST3q8: 3197 case ARM::VST3q16: 3198 case ARM::VST3q32: 3199 case ARM::VST3q8_UPD: 3200 case ARM::VST3q16_UPD: 3201 case ARM::VST3q32_UPD: 3202 case ARM::VST4q8: 3203 case ARM::VST4q16: 3204 case ARM::VST4q32: 3205 case ARM::VST4q8_UPD: 3206 case ARM::VST4q16_UPD: 3207 case ARM::VST4q32_UPD: 3208 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3209 return MCDisassembler::Fail; 3210 break; 3211 default: 3212 break; 3213 } 3214 3215 // Third input register 3216 switch (Inst.getOpcode()) { 3217 case ARM::VST3d8: 3218 case ARM::VST3d16: 3219 case ARM::VST3d32: 3220 case ARM::VST3d8_UPD: 3221 case ARM::VST3d16_UPD: 3222 case ARM::VST3d32_UPD: 3223 case ARM::VST4d8: 3224 case ARM::VST4d16: 3225 case ARM::VST4d32: 3226 case ARM::VST4d8_UPD: 3227 case ARM::VST4d16_UPD: 3228 case ARM::VST4d32_UPD: 3229 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 break; 3232 case ARM::VST3q8: 3233 case ARM::VST3q16: 3234 case ARM::VST3q32: 3235 case ARM::VST3q8_UPD: 3236 case ARM::VST3q16_UPD: 3237 case ARM::VST3q32_UPD: 3238 case ARM::VST4q8: 3239 case ARM::VST4q16: 3240 case ARM::VST4q32: 3241 case ARM::VST4q8_UPD: 3242 case ARM::VST4q16_UPD: 3243 case ARM::VST4q32_UPD: 3244 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3245 return MCDisassembler::Fail; 3246 break; 3247 default: 3248 break; 3249 } 3250 3251 // Fourth input register 3252 switch (Inst.getOpcode()) { 3253 case ARM::VST4d8: 3254 case ARM::VST4d16: 3255 case ARM::VST4d32: 3256 case ARM::VST4d8_UPD: 3257 case ARM::VST4d16_UPD: 3258 case ARM::VST4d32_UPD: 3259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 break; 3262 case ARM::VST4q8: 3263 case ARM::VST4q16: 3264 case ARM::VST4q32: 3265 case ARM::VST4q8_UPD: 3266 case ARM::VST4q16_UPD: 3267 case ARM::VST4q32_UPD: 3268 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 break; 3271 default: 3272 break; 3273 } 3274 3275 return S; 3276} 3277 3278static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3279 uint64_t Address, const void *Decoder) { 3280 DecodeStatus S = MCDisassembler::Success; 3281 3282 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3283 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3284 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3285 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3286 unsigned align = fieldFromInstruction(Insn, 4, 1); 3287 unsigned size = fieldFromInstruction(Insn, 6, 2); 3288 3289 if (size == 0 && align == 1) 3290 return MCDisassembler::Fail; 3291 align *= (1 << size); 3292 3293 switch (Inst.getOpcode()) { 3294 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3295 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3296 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3297 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3298 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3299 return MCDisassembler::Fail; 3300 break; 3301 default: 3302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3303 return MCDisassembler::Fail; 3304 break; 3305 } 3306 if (Rm != 0xF) { 3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 } 3310 3311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3312 return MCDisassembler::Fail; 3313 Inst.addOperand(MCOperand::createImm(align)); 3314 3315 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3316 // variant encodes Rm == 0xf. Anything else is a register offset post- 3317 // increment and we need to add the register operand to the instruction. 3318 if (Rm != 0xD && Rm != 0xF && 3319 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3320 return MCDisassembler::Fail; 3321 3322 return S; 3323} 3324 3325static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3326 uint64_t Address, const void *Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3332 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3333 unsigned align = fieldFromInstruction(Insn, 4, 1); 3334 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3335 align *= 2*size; 3336 3337 switch (Inst.getOpcode()) { 3338 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3339 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3340 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3341 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3342 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 break; 3345 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3346 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3347 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3348 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3349 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 break; 3352 default: 3353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 break; 3356 } 3357 3358 if (Rm != 0xF) 3359 Inst.addOperand(MCOperand::createImm(0)); 3360 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 Inst.addOperand(MCOperand::createImm(align)); 3364 3365 if (Rm != 0xD && Rm != 0xF) { 3366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 } 3369 3370 return S; 3371} 3372 3373static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3374 uint64_t Address, const void *Decoder) { 3375 DecodeStatus S = MCDisassembler::Success; 3376 3377 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3378 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3379 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3380 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3381 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3382 3383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 if (Rm != 0xF) { 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 } 3393 3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 Inst.addOperand(MCOperand::createImm(0)); 3397 3398 if (Rm == 0xD) 3399 Inst.addOperand(MCOperand::createReg(0)); 3400 else if (Rm != 0xF) { 3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 } 3404 3405 return S; 3406} 3407 3408static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3409 uint64_t Address, const void *Decoder) { 3410 DecodeStatus S = MCDisassembler::Success; 3411 3412 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3413 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3414 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3415 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3416 unsigned size = fieldFromInstruction(Insn, 6, 2); 3417 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3418 unsigned align = fieldFromInstruction(Insn, 4, 1); 3419 3420 if (size == 0x3) { 3421 if (align == 0) 3422 return MCDisassembler::Fail; 3423 align = 16; 3424 } else { 3425 if (size == 2) { 3426 align *= 8; 3427 } else { 3428 size = 1 << size; 3429 align *= 4*size; 3430 } 3431 } 3432 3433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (Rm != 0xF) { 3442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 } 3445 3446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3447 return MCDisassembler::Fail; 3448 Inst.addOperand(MCOperand::createImm(align)); 3449 3450 if (Rm == 0xD) 3451 Inst.addOperand(MCOperand::createReg(0)); 3452 else if (Rm != 0xF) { 3453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 } 3456 3457 return S; 3458} 3459 3460static DecodeStatus 3461DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3462 uint64_t Address, const void *Decoder) { 3463 DecodeStatus S = MCDisassembler::Success; 3464 3465 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3466 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3467 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3468 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3469 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3470 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3471 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3472 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3473 3474 if (Q) { 3475 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 } else { 3478 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 } 3481 3482 Inst.addOperand(MCOperand::createImm(imm)); 3483 3484 switch (Inst.getOpcode()) { 3485 case ARM::VORRiv4i16: 3486 case ARM::VORRiv2i32: 3487 case ARM::VBICiv4i16: 3488 case ARM::VBICiv2i32: 3489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 break; 3492 case ARM::VORRiv8i16: 3493 case ARM::VORRiv4i32: 3494 case ARM::VBICiv8i16: 3495 case ARM::VBICiv4i32: 3496 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 break; 3499 default: 3500 break; 3501 } 3502 3503 return S; 3504} 3505 3506static DecodeStatus 3507DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3508 uint64_t Address, const void *Decoder) { 3509 DecodeStatus S = MCDisassembler::Success; 3510 3511 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3512 fieldFromInstruction(Insn, 13, 3)); 3513 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3514 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3515 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3516 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3517 imm |= cmode << 8; 3518 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3519 3520 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3521 return MCDisassembler::Fail; 3522 3523 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3524 return MCDisassembler::Fail; 3525 3526 Inst.addOperand(MCOperand::createImm(imm)); 3527 3528 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3529 Inst.addOperand(MCOperand::createReg(0)); 3530 Inst.addOperand(MCOperand::createImm(0)); 3531 3532 return S; 3533} 3534 3535static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3536 uint64_t Address, const void *Decoder) { 3537 DecodeStatus S = MCDisassembler::Success; 3538 3539 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3540 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3541 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3544 3545 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3546 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3547 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3550 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3551 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3554 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3555 Inst.addOperand(MCOperand::createImm(Qd)); 3556 3557 return S; 3558} 3559 3560static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3561 uint64_t Address, const void *Decoder) { 3562 DecodeStatus S = MCDisassembler::Success; 3563 3564 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3565 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3566 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3567 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3568 unsigned size = fieldFromInstruction(Insn, 18, 2); 3569 3570 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 Inst.addOperand(MCOperand::createImm(8 << size)); 3575 3576 return S; 3577} 3578 3579static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3580 uint64_t Address, const void *Decoder) { 3581 Inst.addOperand(MCOperand::createImm(8 - Val)); 3582 return MCDisassembler::Success; 3583} 3584 3585static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3586 uint64_t Address, const void *Decoder) { 3587 Inst.addOperand(MCOperand::createImm(16 - Val)); 3588 return MCDisassembler::Success; 3589} 3590 3591static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3592 uint64_t Address, const void *Decoder) { 3593 Inst.addOperand(MCOperand::createImm(32 - Val)); 3594 return MCDisassembler::Success; 3595} 3596 3597static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3598 uint64_t Address, const void *Decoder) { 3599 Inst.addOperand(MCOperand::createImm(64 - Val)); 3600 return MCDisassembler::Success; 3601} 3602 3603static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3604 uint64_t Address, const void *Decoder) { 3605 DecodeStatus S = MCDisassembler::Success; 3606 3607 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3608 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3609 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3610 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3611 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3612 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3613 unsigned op = fieldFromInstruction(Insn, 6, 1); 3614 3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 if (op) { 3618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3619 return MCDisassembler::Fail; // Writeback 3620 } 3621 3622 switch (Inst.getOpcode()) { 3623 case ARM::VTBL2: 3624 case ARM::VTBX2: 3625 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 break; 3628 default: 3629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 } 3632 3633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 3636 return S; 3637} 3638 3639static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3640 uint64_t Address, const void *Decoder) { 3641 DecodeStatus S = MCDisassembler::Success; 3642 3643 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3644 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3645 3646 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 3649 switch(Inst.getOpcode()) { 3650 default: 3651 return MCDisassembler::Fail; 3652 case ARM::tADR: 3653 break; // tADR does not explicitly represent the PC as an operand. 3654 case ARM::tADDrSPi: 3655 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3656 break; 3657 } 3658 3659 Inst.addOperand(MCOperand::createImm(imm)); 3660 return S; 3661} 3662 3663static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3664 uint64_t Address, const void *Decoder) { 3665 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3666 true, 2, Inst, Decoder)) 3667 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3668 return MCDisassembler::Success; 3669} 3670 3671static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3672 uint64_t Address, const void *Decoder) { 3673 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3674 true, 4, Inst, Decoder)) 3675 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3676 return MCDisassembler::Success; 3677} 3678 3679static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3680 uint64_t Address, const void *Decoder) { 3681 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3682 true, 2, Inst, Decoder)) 3683 Inst.addOperand(MCOperand::createImm(Val << 1)); 3684 return MCDisassembler::Success; 3685} 3686 3687static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3688 uint64_t Address, const void *Decoder) { 3689 DecodeStatus S = MCDisassembler::Success; 3690 3691 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3692 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3693 3694 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 3699 return S; 3700} 3701 3702static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3703 uint64_t Address, const void *Decoder) { 3704 DecodeStatus S = MCDisassembler::Success; 3705 3706 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3707 unsigned imm = fieldFromInstruction(Val, 3, 5); 3708 3709 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 Inst.addOperand(MCOperand::createImm(imm)); 3712 3713 return S; 3714} 3715 3716static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3717 uint64_t Address, const void *Decoder) { 3718 unsigned imm = Val << 2; 3719 3720 Inst.addOperand(MCOperand::createImm(imm)); 3721 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3722 3723 return MCDisassembler::Success; 3724} 3725 3726static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3727 uint64_t Address, const void *Decoder) { 3728 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3729 Inst.addOperand(MCOperand::createImm(Val)); 3730 3731 return MCDisassembler::Success; 3732} 3733 3734static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3735 uint64_t Address, const void *Decoder) { 3736 DecodeStatus S = MCDisassembler::Success; 3737 3738 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3739 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3740 unsigned imm = fieldFromInstruction(Val, 0, 2); 3741 3742 // Thumb stores cannot use PC as dest register. 3743 switch (Inst.getOpcode()) { 3744 case ARM::t2STRHs: 3745 case ARM::t2STRBs: 3746 case ARM::t2STRs: 3747 if (Rn == 15) 3748 return MCDisassembler::Fail; 3749 break; 3750 default: 3751 break; 3752 } 3753 3754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3755 return MCDisassembler::Fail; 3756 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 Inst.addOperand(MCOperand::createImm(imm)); 3759 3760 return S; 3761} 3762 3763static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3764 uint64_t Address, const void *Decoder) { 3765 DecodeStatus S = MCDisassembler::Success; 3766 3767 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3769 3770 const FeatureBitset &featureBits = 3771 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3772 3773 bool hasMP = featureBits[ARM::FeatureMP]; 3774 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3775 3776 if (Rn == 15) { 3777 switch (Inst.getOpcode()) { 3778 case ARM::t2LDRBs: 3779 Inst.setOpcode(ARM::t2LDRBpci); 3780 break; 3781 case ARM::t2LDRHs: 3782 Inst.setOpcode(ARM::t2LDRHpci); 3783 break; 3784 case ARM::t2LDRSHs: 3785 Inst.setOpcode(ARM::t2LDRSHpci); 3786 break; 3787 case ARM::t2LDRSBs: 3788 Inst.setOpcode(ARM::t2LDRSBpci); 3789 break; 3790 case ARM::t2LDRs: 3791 Inst.setOpcode(ARM::t2LDRpci); 3792 break; 3793 case ARM::t2PLDs: 3794 Inst.setOpcode(ARM::t2PLDpci); 3795 break; 3796 case ARM::t2PLIs: 3797 Inst.setOpcode(ARM::t2PLIpci); 3798 break; 3799 default: 3800 return MCDisassembler::Fail; 3801 } 3802 3803 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3804 } 3805 3806 if (Rt == 15) { 3807 switch (Inst.getOpcode()) { 3808 case ARM::t2LDRSHs: 3809 return MCDisassembler::Fail; 3810 case ARM::t2LDRHs: 3811 Inst.setOpcode(ARM::t2PLDWs); 3812 break; 3813 case ARM::t2LDRSBs: 3814 Inst.setOpcode(ARM::t2PLIs); 3815 break; 3816 default: 3817 break; 3818 } 3819 } 3820 3821 switch (Inst.getOpcode()) { 3822 case ARM::t2PLDs: 3823 break; 3824 case ARM::t2PLIs: 3825 if (!hasV7Ops) 3826 return MCDisassembler::Fail; 3827 break; 3828 case ARM::t2PLDWs: 3829 if (!hasV7Ops || !hasMP) 3830 return MCDisassembler::Fail; 3831 break; 3832 default: 3833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3834 return MCDisassembler::Fail; 3835 } 3836 3837 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3838 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3839 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3840 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3841 return MCDisassembler::Fail; 3842 3843 return S; 3844} 3845 3846static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3847 uint64_t Address, const void* Decoder) { 3848 DecodeStatus S = MCDisassembler::Success; 3849 3850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3852 unsigned U = fieldFromInstruction(Insn, 9, 1); 3853 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3854 imm |= (U << 8); 3855 imm |= (Rn << 9); 3856 unsigned add = fieldFromInstruction(Insn, 9, 1); 3857 3858 const FeatureBitset &featureBits = 3859 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3860 3861 bool hasMP = featureBits[ARM::FeatureMP]; 3862 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3863 3864 if (Rn == 15) { 3865 switch (Inst.getOpcode()) { 3866 case ARM::t2LDRi8: 3867 Inst.setOpcode(ARM::t2LDRpci); 3868 break; 3869 case ARM::t2LDRBi8: 3870 Inst.setOpcode(ARM::t2LDRBpci); 3871 break; 3872 case ARM::t2LDRSBi8: 3873 Inst.setOpcode(ARM::t2LDRSBpci); 3874 break; 3875 case ARM::t2LDRHi8: 3876 Inst.setOpcode(ARM::t2LDRHpci); 3877 break; 3878 case ARM::t2LDRSHi8: 3879 Inst.setOpcode(ARM::t2LDRSHpci); 3880 break; 3881 case ARM::t2PLDi8: 3882 Inst.setOpcode(ARM::t2PLDpci); 3883 break; 3884 case ARM::t2PLIi8: 3885 Inst.setOpcode(ARM::t2PLIpci); 3886 break; 3887 default: 3888 return MCDisassembler::Fail; 3889 } 3890 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3891 } 3892 3893 if (Rt == 15) { 3894 switch (Inst.getOpcode()) { 3895 case ARM::t2LDRSHi8: 3896 return MCDisassembler::Fail; 3897 case ARM::t2LDRHi8: 3898 if (!add) 3899 Inst.setOpcode(ARM::t2PLDWi8); 3900 break; 3901 case ARM::t2LDRSBi8: 3902 Inst.setOpcode(ARM::t2PLIi8); 3903 break; 3904 default: 3905 break; 3906 } 3907 } 3908 3909 switch (Inst.getOpcode()) { 3910 case ARM::t2PLDi8: 3911 break; 3912 case ARM::t2PLIi8: 3913 if (!hasV7Ops) 3914 return MCDisassembler::Fail; 3915 break; 3916 case ARM::t2PLDWi8: 3917 if (!hasV7Ops || !hasMP) 3918 return MCDisassembler::Fail; 3919 break; 3920 default: 3921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 } 3924 3925 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 return S; 3928} 3929 3930static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3931 uint64_t Address, const void* Decoder) { 3932 DecodeStatus S = MCDisassembler::Success; 3933 3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3935 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3936 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3937 imm |= (Rn << 13); 3938 3939 const FeatureBitset &featureBits = 3940 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3941 3942 bool hasMP = featureBits[ARM::FeatureMP]; 3943 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3944 3945 if (Rn == 15) { 3946 switch (Inst.getOpcode()) { 3947 case ARM::t2LDRi12: 3948 Inst.setOpcode(ARM::t2LDRpci); 3949 break; 3950 case ARM::t2LDRHi12: 3951 Inst.setOpcode(ARM::t2LDRHpci); 3952 break; 3953 case ARM::t2LDRSHi12: 3954 Inst.setOpcode(ARM::t2LDRSHpci); 3955 break; 3956 case ARM::t2LDRBi12: 3957 Inst.setOpcode(ARM::t2LDRBpci); 3958 break; 3959 case ARM::t2LDRSBi12: 3960 Inst.setOpcode(ARM::t2LDRSBpci); 3961 break; 3962 case ARM::t2PLDi12: 3963 Inst.setOpcode(ARM::t2PLDpci); 3964 break; 3965 case ARM::t2PLIi12: 3966 Inst.setOpcode(ARM::t2PLIpci); 3967 break; 3968 default: 3969 return MCDisassembler::Fail; 3970 } 3971 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3972 } 3973 3974 if (Rt == 15) { 3975 switch (Inst.getOpcode()) { 3976 case ARM::t2LDRSHi12: 3977 return MCDisassembler::Fail; 3978 case ARM::t2LDRHi12: 3979 Inst.setOpcode(ARM::t2PLDWi12); 3980 break; 3981 case ARM::t2LDRSBi12: 3982 Inst.setOpcode(ARM::t2PLIi12); 3983 break; 3984 default: 3985 break; 3986 } 3987 } 3988 3989 switch (Inst.getOpcode()) { 3990 case ARM::t2PLDi12: 3991 break; 3992 case ARM::t2PLIi12: 3993 if (!hasV7Ops) 3994 return MCDisassembler::Fail; 3995 break; 3996 case ARM::t2PLDWi12: 3997 if (!hasV7Ops || !hasMP) 3998 return MCDisassembler::Fail; 3999 break; 4000 default: 4001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 } 4004 4005 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 return S; 4008} 4009 4010static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4011 uint64_t Address, const void* Decoder) { 4012 DecodeStatus S = MCDisassembler::Success; 4013 4014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4016 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4017 imm |= (Rn << 9); 4018 4019 if (Rn == 15) { 4020 switch (Inst.getOpcode()) { 4021 case ARM::t2LDRT: 4022 Inst.setOpcode(ARM::t2LDRpci); 4023 break; 4024 case ARM::t2LDRBT: 4025 Inst.setOpcode(ARM::t2LDRBpci); 4026 break; 4027 case ARM::t2LDRHT: 4028 Inst.setOpcode(ARM::t2LDRHpci); 4029 break; 4030 case ARM::t2LDRSBT: 4031 Inst.setOpcode(ARM::t2LDRSBpci); 4032 break; 4033 case ARM::t2LDRSHT: 4034 Inst.setOpcode(ARM::t2LDRSHpci); 4035 break; 4036 default: 4037 return MCDisassembler::Fail; 4038 } 4039 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4040 } 4041 4042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4043 return MCDisassembler::Fail; 4044 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4045 return MCDisassembler::Fail; 4046 return S; 4047} 4048 4049static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4050 uint64_t Address, const void* Decoder) { 4051 DecodeStatus S = MCDisassembler::Success; 4052 4053 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4054 unsigned U = fieldFromInstruction(Insn, 23, 1); 4055 int imm = fieldFromInstruction(Insn, 0, 12); 4056 4057 const FeatureBitset &featureBits = 4058 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4059 4060 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4061 4062 if (Rt == 15) { 4063 switch (Inst.getOpcode()) { 4064 case ARM::t2LDRBpci: 4065 case ARM::t2LDRHpci: 4066 Inst.setOpcode(ARM::t2PLDpci); 4067 break; 4068 case ARM::t2LDRSBpci: 4069 Inst.setOpcode(ARM::t2PLIpci); 4070 break; 4071 case ARM::t2LDRSHpci: 4072 return MCDisassembler::Fail; 4073 default: 4074 break; 4075 } 4076 } 4077 4078 switch(Inst.getOpcode()) { 4079 case ARM::t2PLDpci: 4080 break; 4081 case ARM::t2PLIpci: 4082 if (!hasV7Ops) 4083 return MCDisassembler::Fail; 4084 break; 4085 default: 4086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 } 4089 4090 if (!U) { 4091 // Special case for #-0. 4092 if (imm == 0) 4093 imm = INT32_MIN; 4094 else 4095 imm = -imm; 4096 } 4097 Inst.addOperand(MCOperand::createImm(imm)); 4098 4099 return S; 4100} 4101 4102static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4103 uint64_t Address, const void *Decoder) { 4104 if (Val == 0) 4105 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4106 else { 4107 int imm = Val & 0xFF; 4108 4109 if (!(Val & 0x100)) imm *= -1; 4110 Inst.addOperand(MCOperand::createImm(imm * 4)); 4111 } 4112 4113 return MCDisassembler::Success; 4114} 4115 4116static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4117 const void *Decoder) { 4118 if (Val == 0) 4119 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4120 else { 4121 int imm = Val & 0x7F; 4122 4123 if (!(Val & 0x80)) 4124 imm *= -1; 4125 Inst.addOperand(MCOperand::createImm(imm * 4)); 4126 } 4127 4128 return MCDisassembler::Success; 4129} 4130 4131static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4132 uint64_t Address, const void *Decoder) { 4133 DecodeStatus S = MCDisassembler::Success; 4134 4135 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4136 unsigned imm = fieldFromInstruction(Val, 0, 9); 4137 4138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 4143 return S; 4144} 4145 4146static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4147 uint64_t Address, 4148 const void *Decoder) { 4149 DecodeStatus S = MCDisassembler::Success; 4150 4151 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4152 unsigned imm = fieldFromInstruction(Val, 0, 8); 4153 4154 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4155 return MCDisassembler::Fail; 4156 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 4159 return S; 4160} 4161 4162static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4163 uint64_t Address, const void *Decoder) { 4164 DecodeStatus S = MCDisassembler::Success; 4165 4166 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4167 unsigned imm = fieldFromInstruction(Val, 0, 8); 4168 4169 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 4172 Inst.addOperand(MCOperand::createImm(imm)); 4173 4174 return S; 4175} 4176 4177static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4178 uint64_t Address, const void *Decoder) { 4179 int imm = Val & 0xFF; 4180 if (Val == 0) 4181 imm = INT32_MIN; 4182 else if (!(Val & 0x100)) 4183 imm *= -1; 4184 Inst.addOperand(MCOperand::createImm(imm)); 4185 4186 return MCDisassembler::Success; 4187} 4188 4189template<int shift> 4190static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4191 uint64_t Address, const void *Decoder) { 4192 int imm = Val & 0x7F; 4193 if (Val == 0) 4194 imm = INT32_MIN; 4195 else if (!(Val & 0x80)) 4196 imm *= -1; 4197 if (imm != INT32_MIN) 4198 imm *= (1U << shift); 4199 Inst.addOperand(MCOperand::createImm(imm)); 4200 4201 return MCDisassembler::Success; 4202} 4203 4204static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4205 uint64_t Address, const void *Decoder) { 4206 DecodeStatus S = MCDisassembler::Success; 4207 4208 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4209 unsigned imm = fieldFromInstruction(Val, 0, 9); 4210 4211 // Thumb stores cannot use PC as dest register. 4212 switch (Inst.getOpcode()) { 4213 case ARM::t2STRT: 4214 case ARM::t2STRBT: 4215 case ARM::t2STRHT: 4216 case ARM::t2STRi8: 4217 case ARM::t2STRHi8: 4218 case ARM::t2STRBi8: 4219 if (Rn == 15) 4220 return MCDisassembler::Fail; 4221 break; 4222 default: 4223 break; 4224 } 4225 4226 // Some instructions always use an additive offset. 4227 switch (Inst.getOpcode()) { 4228 case ARM::t2LDRT: 4229 case ARM::t2LDRBT: 4230 case ARM::t2LDRHT: 4231 case ARM::t2LDRSBT: 4232 case ARM::t2LDRSHT: 4233 case ARM::t2STRT: 4234 case ARM::t2STRBT: 4235 case ARM::t2STRHT: 4236 imm |= 0x100; 4237 break; 4238 default: 4239 break; 4240 } 4241 4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 4247 return S; 4248} 4249 4250template<int shift> 4251static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4252 uint64_t Address, 4253 const void *Decoder) { 4254 DecodeStatus S = MCDisassembler::Success; 4255 4256 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4257 unsigned imm = fieldFromInstruction(Val, 0, 8); 4258 4259 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 4264 return S; 4265} 4266 4267template<int shift, int WriteBack> 4268static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4269 uint64_t Address, 4270 const void *Decoder) { 4271 DecodeStatus S = MCDisassembler::Success; 4272 4273 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4274 unsigned imm = fieldFromInstruction(Val, 0, 8); 4275 if (WriteBack) { 4276 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4277 return MCDisassembler::Fail; 4278 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4279 return MCDisassembler::Fail; 4280 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 4283 return S; 4284} 4285 4286static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4287 uint64_t Address, const void *Decoder) { 4288 DecodeStatus S = MCDisassembler::Success; 4289 4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4291 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4292 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4293 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4294 addr |= Rn << 9; 4295 unsigned load = fieldFromInstruction(Insn, 20, 1); 4296 4297 if (Rn == 15) { 4298 switch (Inst.getOpcode()) { 4299 case ARM::t2LDR_PRE: 4300 case ARM::t2LDR_POST: 4301 Inst.setOpcode(ARM::t2LDRpci); 4302 break; 4303 case ARM::t2LDRB_PRE: 4304 case ARM::t2LDRB_POST: 4305 Inst.setOpcode(ARM::t2LDRBpci); 4306 break; 4307 case ARM::t2LDRH_PRE: 4308 case ARM::t2LDRH_POST: 4309 Inst.setOpcode(ARM::t2LDRHpci); 4310 break; 4311 case ARM::t2LDRSB_PRE: 4312 case ARM::t2LDRSB_POST: 4313 if (Rt == 15) 4314 Inst.setOpcode(ARM::t2PLIpci); 4315 else 4316 Inst.setOpcode(ARM::t2LDRSBpci); 4317 break; 4318 case ARM::t2LDRSH_PRE: 4319 case ARM::t2LDRSH_POST: 4320 Inst.setOpcode(ARM::t2LDRSHpci); 4321 break; 4322 default: 4323 return MCDisassembler::Fail; 4324 } 4325 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4326 } 4327 4328 if (!load) { 4329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4330 return MCDisassembler::Fail; 4331 } 4332 4333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 4336 if (load) { 4337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 } 4340 4341 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4342 return MCDisassembler::Fail; 4343 4344 return S; 4345} 4346 4347static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4348 uint64_t Address, const void *Decoder) { 4349 DecodeStatus S = MCDisassembler::Success; 4350 4351 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4352 unsigned imm = fieldFromInstruction(Val, 0, 12); 4353 4354 // Thumb stores cannot use PC as dest register. 4355 switch (Inst.getOpcode()) { 4356 case ARM::t2STRi12: 4357 case ARM::t2STRBi12: 4358 case ARM::t2STRHi12: 4359 if (Rn == 15) 4360 return MCDisassembler::Fail; 4361 break; 4362 default: 4363 break; 4364 } 4365 4366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 Inst.addOperand(MCOperand::createImm(imm)); 4369 4370 return S; 4371} 4372 4373static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4374 uint64_t Address, const void *Decoder) { 4375 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4376 4377 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4378 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4379 Inst.addOperand(MCOperand::createImm(imm)); 4380 4381 return MCDisassembler::Success; 4382} 4383 4384static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4385 uint64_t Address, const void *Decoder) { 4386 DecodeStatus S = MCDisassembler::Success; 4387 4388 if (Inst.getOpcode() == ARM::tADDrSP) { 4389 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4390 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4391 4392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4393 return MCDisassembler::Fail; 4394 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4396 return MCDisassembler::Fail; 4397 } else if (Inst.getOpcode() == ARM::tADDspr) { 4398 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4399 4400 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4401 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4403 return MCDisassembler::Fail; 4404 } 4405 4406 return S; 4407} 4408 4409static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4410 uint64_t Address, const void *Decoder) { 4411 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4412 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4413 4414 Inst.addOperand(MCOperand::createImm(imod)); 4415 Inst.addOperand(MCOperand::createImm(flags)); 4416 4417 return MCDisassembler::Success; 4418} 4419 4420static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4421 uint64_t Address, const void *Decoder) { 4422 DecodeStatus S = MCDisassembler::Success; 4423 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4424 unsigned add = fieldFromInstruction(Insn, 4, 1); 4425 4426 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 Inst.addOperand(MCOperand::createImm(add)); 4429 4430 return S; 4431} 4432 4433static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4434 uint64_t Address, const void *Decoder) { 4435 DecodeStatus S = MCDisassembler::Success; 4436 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4437 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4438 4439 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4442 return MCDisassembler::Fail; 4443 4444 return S; 4445} 4446 4447template<int shift> 4448static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4449 uint64_t Address, const void *Decoder) { 4450 DecodeStatus S = MCDisassembler::Success; 4451 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4452 int imm = fieldFromInstruction(Insn, 0, 7); 4453 4454 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4455 return MCDisassembler::Fail; 4456 4457 if(!fieldFromInstruction(Insn, 7, 1)) { 4458 if (imm == 0) 4459 imm = INT32_MIN; // indicate -0 4460 else 4461 imm *= -1; 4462 } 4463 if (imm != INT32_MIN) 4464 imm *= (1U << shift); 4465 Inst.addOperand(MCOperand::createImm(imm)); 4466 4467 return S; 4468} 4469 4470static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4471 uint64_t Address, const void *Decoder) { 4472 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4473 // Note only one trailing zero not two. Also the J1 and J2 values are from 4474 // the encoded instruction. So here change to I1 and I2 values via: 4475 // I1 = NOT(J1 EOR S); 4476 // I2 = NOT(J2 EOR S); 4477 // and build the imm32 with two trailing zeros as documented: 4478 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4479 unsigned S = (Val >> 23) & 1; 4480 unsigned J1 = (Val >> 22) & 1; 4481 unsigned J2 = (Val >> 21) & 1; 4482 unsigned I1 = !(J1 ^ S); 4483 unsigned I2 = !(J2 ^ S); 4484 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4485 int imm32 = SignExtend32<25>(tmp << 1); 4486 4487 if (!tryAddingSymbolicOperand(Address, 4488 (Address & ~2u) + imm32 + 4, 4489 true, 4, Inst, Decoder)) 4490 Inst.addOperand(MCOperand::createImm(imm32)); 4491 return MCDisassembler::Success; 4492} 4493 4494static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4495 uint64_t Address, const void *Decoder) { 4496 if (Val == 0xA || Val == 0xB) 4497 return MCDisassembler::Fail; 4498 4499 const FeatureBitset &featureBits = 4500 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4501 4502 if (!isValidCoprocessorNumber(Val, featureBits)) 4503 return MCDisassembler::Fail; 4504 4505 Inst.addOperand(MCOperand::createImm(Val)); 4506 return MCDisassembler::Success; 4507} 4508 4509static DecodeStatus 4510DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4511 uint64_t Address, const void *Decoder) { 4512 DecodeStatus S = MCDisassembler::Success; 4513 4514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4515 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4516 4517 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4519 return MCDisassembler::Fail; 4520 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4521 return MCDisassembler::Fail; 4522 return S; 4523} 4524 4525static DecodeStatus 4526DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4527 uint64_t Address, const void *Decoder) { 4528 DecodeStatus S = MCDisassembler::Success; 4529 4530 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4531 if (pred == 0xE || pred == 0xF) { 4532 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4533 switch (opc) { 4534 default: 4535 return MCDisassembler::Fail; 4536 case 0xf3bf8f4: 4537 Inst.setOpcode(ARM::t2DSB); 4538 break; 4539 case 0xf3bf8f5: 4540 Inst.setOpcode(ARM::t2DMB); 4541 break; 4542 case 0xf3bf8f6: 4543 Inst.setOpcode(ARM::t2ISB); 4544 break; 4545 } 4546 4547 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4548 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4549 } 4550 4551 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4552 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4553 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4554 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4555 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4556 4557 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 4562 return S; 4563} 4564 4565// Decode a shifted immediate operand. These basically consist 4566// of an 8-bit value, and a 4-bit directive that specifies either 4567// a splat operation or a rotation. 4568static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4569 uint64_t Address, const void *Decoder) { 4570 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4571 if (ctrl == 0) { 4572 unsigned byte = fieldFromInstruction(Val, 8, 2); 4573 unsigned imm = fieldFromInstruction(Val, 0, 8); 4574 switch (byte) { 4575 case 0: 4576 Inst.addOperand(MCOperand::createImm(imm)); 4577 break; 4578 case 1: 4579 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4580 break; 4581 case 2: 4582 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4583 break; 4584 case 3: 4585 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4586 (imm << 8) | imm)); 4587 break; 4588 } 4589 } else { 4590 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4591 unsigned rot = fieldFromInstruction(Val, 7, 5); 4592 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4593 Inst.addOperand(MCOperand::createImm(imm)); 4594 } 4595 4596 return MCDisassembler::Success; 4597} 4598 4599static DecodeStatus 4600DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4601 uint64_t Address, const void *Decoder) { 4602 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4603 true, 2, Inst, Decoder)) 4604 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4605 return MCDisassembler::Success; 4606} 4607 4608static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4609 uint64_t Address, 4610 const void *Decoder) { 4611 // Val is passed in as S:J1:J2:imm10:imm11 4612 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4613 // the encoded instruction. So here change to I1 and I2 values via: 4614 // I1 = NOT(J1 EOR S); 4615 // I2 = NOT(J2 EOR S); 4616 // and build the imm32 with one trailing zero as documented: 4617 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4618 unsigned S = (Val >> 23) & 1; 4619 unsigned J1 = (Val >> 22) & 1; 4620 unsigned J2 = (Val >> 21) & 1; 4621 unsigned I1 = !(J1 ^ S); 4622 unsigned I2 = !(J2 ^ S); 4623 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4624 int imm32 = SignExtend32<25>(tmp << 1); 4625 4626 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4627 true, 4, Inst, Decoder)) 4628 Inst.addOperand(MCOperand::createImm(imm32)); 4629 return MCDisassembler::Success; 4630} 4631 4632static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4633 uint64_t Address, const void *Decoder) { 4634 if (Val & ~0xf) 4635 return MCDisassembler::Fail; 4636 4637 Inst.addOperand(MCOperand::createImm(Val)); 4638 return MCDisassembler::Success; 4639} 4640 4641static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4642 uint64_t Address, const void *Decoder) { 4643 if (Val & ~0xf) 4644 return MCDisassembler::Fail; 4645 4646 Inst.addOperand(MCOperand::createImm(Val)); 4647 return MCDisassembler::Success; 4648} 4649 4650static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4651 uint64_t Address, const void *Decoder) { 4652 DecodeStatus S = MCDisassembler::Success; 4653 const FeatureBitset &FeatureBits = 4654 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4655 4656 if (FeatureBits[ARM::FeatureMClass]) { 4657 unsigned ValLow = Val & 0xff; 4658 4659 // Validate the SYSm value first. 4660 switch (ValLow) { 4661 case 0: // apsr 4662 case 1: // iapsr 4663 case 2: // eapsr 4664 case 3: // xpsr 4665 case 5: // ipsr 4666 case 6: // epsr 4667 case 7: // iepsr 4668 case 8: // msp 4669 case 9: // psp 4670 case 16: // primask 4671 case 20: // control 4672 break; 4673 case 17: // basepri 4674 case 18: // basepri_max 4675 case 19: // faultmask 4676 if (!(FeatureBits[ARM::HasV7Ops])) 4677 // Values basepri, basepri_max and faultmask are only valid for v7m. 4678 return MCDisassembler::Fail; 4679 break; 4680 case 0x8a: // msplim_ns 4681 case 0x8b: // psplim_ns 4682 case 0x91: // basepri_ns 4683 case 0x93: // faultmask_ns 4684 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4685 return MCDisassembler::Fail; 4686 LLVM_FALLTHROUGH; 4687 case 10: // msplim 4688 case 11: // psplim 4689 case 0x88: // msp_ns 4690 case 0x89: // psp_ns 4691 case 0x90: // primask_ns 4692 case 0x94: // control_ns 4693 case 0x98: // sp_ns 4694 if (!(FeatureBits[ARM::Feature8MSecExt])) 4695 return MCDisassembler::Fail; 4696 break; 4697 default: 4698 // Architecturally defined as unpredictable 4699 S = MCDisassembler::SoftFail; 4700 break; 4701 } 4702 4703 if (Inst.getOpcode() == ARM::t2MSR_M) { 4704 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4705 if (!(FeatureBits[ARM::HasV7Ops])) { 4706 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4707 // unpredictable. 4708 if (Mask != 2) 4709 S = MCDisassembler::SoftFail; 4710 } 4711 else { 4712 // The ARMv7-M architecture stores an additional 2-bit mask value in 4713 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4714 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4715 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4716 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4717 // only if the processor includes the DSP extension. 4718 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4719 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4720 S = MCDisassembler::SoftFail; 4721 } 4722 } 4723 } else { 4724 // A/R class 4725 if (Val == 0) 4726 return MCDisassembler::Fail; 4727 } 4728 Inst.addOperand(MCOperand::createImm(Val)); 4729 return S; 4730} 4731 4732static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4733 uint64_t Address, const void *Decoder) { 4734 unsigned R = fieldFromInstruction(Val, 5, 1); 4735 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4736 4737 // The table of encodings for these banked registers comes from B9.2.3 of the 4738 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4739 // neater. So by fiat, these values are UNPREDICTABLE: 4740 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4741 return MCDisassembler::Fail; 4742 4743 Inst.addOperand(MCOperand::createImm(Val)); 4744 return MCDisassembler::Success; 4745} 4746 4747static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4748 uint64_t Address, const void *Decoder) { 4749 DecodeStatus S = MCDisassembler::Success; 4750 4751 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4753 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4754 4755 if (Rn == 0xF) 4756 S = MCDisassembler::SoftFail; 4757 4758 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4759 return MCDisassembler::Fail; 4760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4761 return MCDisassembler::Fail; 4762 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4763 return MCDisassembler::Fail; 4764 4765 return S; 4766} 4767 4768static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4769 uint64_t Address, 4770 const void *Decoder) { 4771 DecodeStatus S = MCDisassembler::Success; 4772 4773 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4774 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4776 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4777 4778 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4779 return MCDisassembler::Fail; 4780 4781 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4782 S = MCDisassembler::SoftFail; 4783 4784 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4785 return MCDisassembler::Fail; 4786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4787 return MCDisassembler::Fail; 4788 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4789 return MCDisassembler::Fail; 4790 4791 return S; 4792} 4793 4794static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4795 uint64_t Address, const void *Decoder) { 4796 DecodeStatus S = MCDisassembler::Success; 4797 4798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4800 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4801 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4802 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4803 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4804 4805 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4806 4807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 4816 return S; 4817} 4818 4819static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4820 uint64_t Address, const void *Decoder) { 4821 DecodeStatus S = MCDisassembler::Success; 4822 4823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4825 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4826 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4827 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4828 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4830 4831 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4832 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4833 4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 4843 return S; 4844} 4845 4846static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4847 uint64_t Address, const void *Decoder) { 4848 DecodeStatus S = MCDisassembler::Success; 4849 4850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4852 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4853 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4854 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4855 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4856 4857 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4858 4859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 4868 return S; 4869} 4870 4871static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4872 uint64_t Address, const void *Decoder) { 4873 DecodeStatus S = MCDisassembler::Success; 4874 4875 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4877 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4878 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4879 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4880 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4881 4882 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4883 4884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4887 return MCDisassembler::Fail; 4888 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 4893 return S; 4894} 4895 4896static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4897 uint64_t Address, const void *Decoder) { 4898 DecodeStatus S = MCDisassembler::Success; 4899 4900 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4901 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4902 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4903 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4904 unsigned size = fieldFromInstruction(Insn, 10, 2); 4905 4906 unsigned align = 0; 4907 unsigned index = 0; 4908 switch (size) { 4909 default: 4910 return MCDisassembler::Fail; 4911 case 0: 4912 if (fieldFromInstruction(Insn, 4, 1)) 4913 return MCDisassembler::Fail; // UNDEFINED 4914 index = fieldFromInstruction(Insn, 5, 3); 4915 break; 4916 case 1: 4917 if (fieldFromInstruction(Insn, 5, 1)) 4918 return MCDisassembler::Fail; // UNDEFINED 4919 index = fieldFromInstruction(Insn, 6, 2); 4920 if (fieldFromInstruction(Insn, 4, 1)) 4921 align = 2; 4922 break; 4923 case 2: 4924 if (fieldFromInstruction(Insn, 6, 1)) 4925 return MCDisassembler::Fail; // UNDEFINED 4926 index = fieldFromInstruction(Insn, 7, 1); 4927 4928 switch (fieldFromInstruction(Insn, 4, 2)) { 4929 case 0 : 4930 align = 0; break; 4931 case 3: 4932 align = 4; break; 4933 default: 4934 return MCDisassembler::Fail; 4935 } 4936 break; 4937 } 4938 4939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (Rm != 0xF) { // Writeback 4942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4943 return MCDisassembler::Fail; 4944 } 4945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 Inst.addOperand(MCOperand::createImm(align)); 4948 if (Rm != 0xF) { 4949 if (Rm != 0xD) { 4950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4951 return MCDisassembler::Fail; 4952 } else 4953 Inst.addOperand(MCOperand::createReg(0)); 4954 } 4955 4956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4957 return MCDisassembler::Fail; 4958 Inst.addOperand(MCOperand::createImm(index)); 4959 4960 return S; 4961} 4962 4963static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4964 uint64_t Address, const void *Decoder) { 4965 DecodeStatus S = MCDisassembler::Success; 4966 4967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4968 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4969 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4970 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4971 unsigned size = fieldFromInstruction(Insn, 10, 2); 4972 4973 unsigned align = 0; 4974 unsigned index = 0; 4975 switch (size) { 4976 default: 4977 return MCDisassembler::Fail; 4978 case 0: 4979 if (fieldFromInstruction(Insn, 4, 1)) 4980 return MCDisassembler::Fail; // UNDEFINED 4981 index = fieldFromInstruction(Insn, 5, 3); 4982 break; 4983 case 1: 4984 if (fieldFromInstruction(Insn, 5, 1)) 4985 return MCDisassembler::Fail; // UNDEFINED 4986 index = fieldFromInstruction(Insn, 6, 2); 4987 if (fieldFromInstruction(Insn, 4, 1)) 4988 align = 2; 4989 break; 4990 case 2: 4991 if (fieldFromInstruction(Insn, 6, 1)) 4992 return MCDisassembler::Fail; // UNDEFINED 4993 index = fieldFromInstruction(Insn, 7, 1); 4994 4995 switch (fieldFromInstruction(Insn, 4, 2)) { 4996 case 0: 4997 align = 0; break; 4998 case 3: 4999 align = 4; break; 5000 default: 5001 return MCDisassembler::Fail; 5002 } 5003 break; 5004 } 5005 5006 if (Rm != 0xF) { // Writeback 5007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5008 return MCDisassembler::Fail; 5009 } 5010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5011 return MCDisassembler::Fail; 5012 Inst.addOperand(MCOperand::createImm(align)); 5013 if (Rm != 0xF) { 5014 if (Rm != 0xD) { 5015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5016 return MCDisassembler::Fail; 5017 } else 5018 Inst.addOperand(MCOperand::createReg(0)); 5019 } 5020 5021 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 Inst.addOperand(MCOperand::createImm(index)); 5024 5025 return S; 5026} 5027 5028static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5029 uint64_t Address, const void *Decoder) { 5030 DecodeStatus S = MCDisassembler::Success; 5031 5032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5033 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5034 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5035 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5036 unsigned size = fieldFromInstruction(Insn, 10, 2); 5037 5038 unsigned align = 0; 5039 unsigned index = 0; 5040 unsigned inc = 1; 5041 switch (size) { 5042 default: 5043 return MCDisassembler::Fail; 5044 case 0: 5045 index = fieldFromInstruction(Insn, 5, 3); 5046 if (fieldFromInstruction(Insn, 4, 1)) 5047 align = 2; 5048 break; 5049 case 1: 5050 index = fieldFromInstruction(Insn, 6, 2); 5051 if (fieldFromInstruction(Insn, 4, 1)) 5052 align = 4; 5053 if (fieldFromInstruction(Insn, 5, 1)) 5054 inc = 2; 5055 break; 5056 case 2: 5057 if (fieldFromInstruction(Insn, 5, 1)) 5058 return MCDisassembler::Fail; // UNDEFINED 5059 index = fieldFromInstruction(Insn, 7, 1); 5060 if (fieldFromInstruction(Insn, 4, 1) != 0) 5061 align = 8; 5062 if (fieldFromInstruction(Insn, 6, 1)) 5063 inc = 2; 5064 break; 5065 } 5066 5067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5068 return MCDisassembler::Fail; 5069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5070 return MCDisassembler::Fail; 5071 if (Rm != 0xF) { // Writeback 5072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5073 return MCDisassembler::Fail; 5074 } 5075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5076 return MCDisassembler::Fail; 5077 Inst.addOperand(MCOperand::createImm(align)); 5078 if (Rm != 0xF) { 5079 if (Rm != 0xD) { 5080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5081 return MCDisassembler::Fail; 5082 } else 5083 Inst.addOperand(MCOperand::createReg(0)); 5084 } 5085 5086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5089 return MCDisassembler::Fail; 5090 Inst.addOperand(MCOperand::createImm(index)); 5091 5092 return S; 5093} 5094 5095static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5096 uint64_t Address, const void *Decoder) { 5097 DecodeStatus S = MCDisassembler::Success; 5098 5099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5100 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5102 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5103 unsigned size = fieldFromInstruction(Insn, 10, 2); 5104 5105 unsigned align = 0; 5106 unsigned index = 0; 5107 unsigned inc = 1; 5108 switch (size) { 5109 default: 5110 return MCDisassembler::Fail; 5111 case 0: 5112 index = fieldFromInstruction(Insn, 5, 3); 5113 if (fieldFromInstruction(Insn, 4, 1)) 5114 align = 2; 5115 break; 5116 case 1: 5117 index = fieldFromInstruction(Insn, 6, 2); 5118 if (fieldFromInstruction(Insn, 4, 1)) 5119 align = 4; 5120 if (fieldFromInstruction(Insn, 5, 1)) 5121 inc = 2; 5122 break; 5123 case 2: 5124 if (fieldFromInstruction(Insn, 5, 1)) 5125 return MCDisassembler::Fail; // UNDEFINED 5126 index = fieldFromInstruction(Insn, 7, 1); 5127 if (fieldFromInstruction(Insn, 4, 1) != 0) 5128 align = 8; 5129 if (fieldFromInstruction(Insn, 6, 1)) 5130 inc = 2; 5131 break; 5132 } 5133 5134 if (Rm != 0xF) { // Writeback 5135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5136 return MCDisassembler::Fail; 5137 } 5138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5139 return MCDisassembler::Fail; 5140 Inst.addOperand(MCOperand::createImm(align)); 5141 if (Rm != 0xF) { 5142 if (Rm != 0xD) { 5143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5144 return MCDisassembler::Fail; 5145 } else 5146 Inst.addOperand(MCOperand::createReg(0)); 5147 } 5148 5149 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5152 return MCDisassembler::Fail; 5153 Inst.addOperand(MCOperand::createImm(index)); 5154 5155 return S; 5156} 5157 5158static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5159 uint64_t Address, const void *Decoder) { 5160 DecodeStatus S = MCDisassembler::Success; 5161 5162 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5163 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5164 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5165 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5166 unsigned size = fieldFromInstruction(Insn, 10, 2); 5167 5168 unsigned align = 0; 5169 unsigned index = 0; 5170 unsigned inc = 1; 5171 switch (size) { 5172 default: 5173 return MCDisassembler::Fail; 5174 case 0: 5175 if (fieldFromInstruction(Insn, 4, 1)) 5176 return MCDisassembler::Fail; // UNDEFINED 5177 index = fieldFromInstruction(Insn, 5, 3); 5178 break; 5179 case 1: 5180 if (fieldFromInstruction(Insn, 4, 1)) 5181 return MCDisassembler::Fail; // UNDEFINED 5182 index = fieldFromInstruction(Insn, 6, 2); 5183 if (fieldFromInstruction(Insn, 5, 1)) 5184 inc = 2; 5185 break; 5186 case 2: 5187 if (fieldFromInstruction(Insn, 4, 2)) 5188 return MCDisassembler::Fail; // UNDEFINED 5189 index = fieldFromInstruction(Insn, 7, 1); 5190 if (fieldFromInstruction(Insn, 6, 1)) 5191 inc = 2; 5192 break; 5193 } 5194 5195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5196 return MCDisassembler::Fail; 5197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5198 return MCDisassembler::Fail; 5199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5200 return MCDisassembler::Fail; 5201 5202 if (Rm != 0xF) { // Writeback 5203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5204 return MCDisassembler::Fail; 5205 } 5206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 Inst.addOperand(MCOperand::createImm(align)); 5209 if (Rm != 0xF) { 5210 if (Rm != 0xD) { 5211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5212 return MCDisassembler::Fail; 5213 } else 5214 Inst.addOperand(MCOperand::createReg(0)); 5215 } 5216 5217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5220 return MCDisassembler::Fail; 5221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5222 return MCDisassembler::Fail; 5223 Inst.addOperand(MCOperand::createImm(index)); 5224 5225 return S; 5226} 5227 5228static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5229 uint64_t Address, const void *Decoder) { 5230 DecodeStatus S = MCDisassembler::Success; 5231 5232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5233 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5234 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5235 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5236 unsigned size = fieldFromInstruction(Insn, 10, 2); 5237 5238 unsigned align = 0; 5239 unsigned index = 0; 5240 unsigned inc = 1; 5241 switch (size) { 5242 default: 5243 return MCDisassembler::Fail; 5244 case 0: 5245 if (fieldFromInstruction(Insn, 4, 1)) 5246 return MCDisassembler::Fail; // UNDEFINED 5247 index = fieldFromInstruction(Insn, 5, 3); 5248 break; 5249 case 1: 5250 if (fieldFromInstruction(Insn, 4, 1)) 5251 return MCDisassembler::Fail; // UNDEFINED 5252 index = fieldFromInstruction(Insn, 6, 2); 5253 if (fieldFromInstruction(Insn, 5, 1)) 5254 inc = 2; 5255 break; 5256 case 2: 5257 if (fieldFromInstruction(Insn, 4, 2)) 5258 return MCDisassembler::Fail; // UNDEFINED 5259 index = fieldFromInstruction(Insn, 7, 1); 5260 if (fieldFromInstruction(Insn, 6, 1)) 5261 inc = 2; 5262 break; 5263 } 5264 5265 if (Rm != 0xF) { // Writeback 5266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5267 return MCDisassembler::Fail; 5268 } 5269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5270 return MCDisassembler::Fail; 5271 Inst.addOperand(MCOperand::createImm(align)); 5272 if (Rm != 0xF) { 5273 if (Rm != 0xD) { 5274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5275 return MCDisassembler::Fail; 5276 } else 5277 Inst.addOperand(MCOperand::createReg(0)); 5278 } 5279 5280 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5283 return MCDisassembler::Fail; 5284 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 Inst.addOperand(MCOperand::createImm(index)); 5287 5288 return S; 5289} 5290 5291static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5292 uint64_t Address, const void *Decoder) { 5293 DecodeStatus S = MCDisassembler::Success; 5294 5295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5296 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5298 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5299 unsigned size = fieldFromInstruction(Insn, 10, 2); 5300 5301 unsigned align = 0; 5302 unsigned index = 0; 5303 unsigned inc = 1; 5304 switch (size) { 5305 default: 5306 return MCDisassembler::Fail; 5307 case 0: 5308 if (fieldFromInstruction(Insn, 4, 1)) 5309 align = 4; 5310 index = fieldFromInstruction(Insn, 5, 3); 5311 break; 5312 case 1: 5313 if (fieldFromInstruction(Insn, 4, 1)) 5314 align = 8; 5315 index = fieldFromInstruction(Insn, 6, 2); 5316 if (fieldFromInstruction(Insn, 5, 1)) 5317 inc = 2; 5318 break; 5319 case 2: 5320 switch (fieldFromInstruction(Insn, 4, 2)) { 5321 case 0: 5322 align = 0; break; 5323 case 3: 5324 return MCDisassembler::Fail; 5325 default: 5326 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5327 } 5328 5329 index = fieldFromInstruction(Insn, 7, 1); 5330 if (fieldFromInstruction(Insn, 6, 1)) 5331 inc = 2; 5332 break; 5333 } 5334 5335 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5340 return MCDisassembler::Fail; 5341 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5342 return MCDisassembler::Fail; 5343 5344 if (Rm != 0xF) { // Writeback 5345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5346 return MCDisassembler::Fail; 5347 } 5348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5349 return MCDisassembler::Fail; 5350 Inst.addOperand(MCOperand::createImm(align)); 5351 if (Rm != 0xF) { 5352 if (Rm != 0xD) { 5353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5354 return MCDisassembler::Fail; 5355 } else 5356 Inst.addOperand(MCOperand::createReg(0)); 5357 } 5358 5359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5362 return MCDisassembler::Fail; 5363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5364 return MCDisassembler::Fail; 5365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5366 return MCDisassembler::Fail; 5367 Inst.addOperand(MCOperand::createImm(index)); 5368 5369 return S; 5370} 5371 5372static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5373 uint64_t Address, const void *Decoder) { 5374 DecodeStatus S = MCDisassembler::Success; 5375 5376 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5377 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5378 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5379 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5380 unsigned size = fieldFromInstruction(Insn, 10, 2); 5381 5382 unsigned align = 0; 5383 unsigned index = 0; 5384 unsigned inc = 1; 5385 switch (size) { 5386 default: 5387 return MCDisassembler::Fail; 5388 case 0: 5389 if (fieldFromInstruction(Insn, 4, 1)) 5390 align = 4; 5391 index = fieldFromInstruction(Insn, 5, 3); 5392 break; 5393 case 1: 5394 if (fieldFromInstruction(Insn, 4, 1)) 5395 align = 8; 5396 index = fieldFromInstruction(Insn, 6, 2); 5397 if (fieldFromInstruction(Insn, 5, 1)) 5398 inc = 2; 5399 break; 5400 case 2: 5401 switch (fieldFromInstruction(Insn, 4, 2)) { 5402 case 0: 5403 align = 0; break; 5404 case 3: 5405 return MCDisassembler::Fail; 5406 default: 5407 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5408 } 5409 5410 index = fieldFromInstruction(Insn, 7, 1); 5411 if (fieldFromInstruction(Insn, 6, 1)) 5412 inc = 2; 5413 break; 5414 } 5415 5416 if (Rm != 0xF) { // Writeback 5417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5418 return MCDisassembler::Fail; 5419 } 5420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 Inst.addOperand(MCOperand::createImm(align)); 5423 if (Rm != 0xF) { 5424 if (Rm != 0xD) { 5425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 } else 5428 Inst.addOperand(MCOperand::createReg(0)); 5429 } 5430 5431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5434 return MCDisassembler::Fail; 5435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5436 return MCDisassembler::Fail; 5437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5438 return MCDisassembler::Fail; 5439 Inst.addOperand(MCOperand::createImm(index)); 5440 5441 return S; 5442} 5443 5444static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5445 uint64_t Address, const void *Decoder) { 5446 DecodeStatus S = MCDisassembler::Success; 5447 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5448 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5449 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5450 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5451 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5452 5453 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5454 S = MCDisassembler::SoftFail; 5455 5456 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 5467 return S; 5468} 5469 5470static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5471 uint64_t Address, const void *Decoder) { 5472 DecodeStatus S = MCDisassembler::Success; 5473 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5474 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5475 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5476 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5477 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5478 5479 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5480 S = MCDisassembler::SoftFail; 5481 5482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5483 return MCDisassembler::Fail; 5484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5485 return MCDisassembler::Fail; 5486 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5489 return MCDisassembler::Fail; 5490 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5491 return MCDisassembler::Fail; 5492 5493 return S; 5494} 5495 5496static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5497 uint64_t Address, const void *Decoder) { 5498 DecodeStatus S = MCDisassembler::Success; 5499 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5500 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5501 5502 if (pred == 0xF) { 5503 pred = 0xE; 5504 S = MCDisassembler::SoftFail; 5505 } 5506 5507 if (mask == 0x0) 5508 return MCDisassembler::Fail; 5509 5510 // IT masks are encoded as a sequence of replacement low-order bits 5511 // for the condition code. So if the low bit of the starting 5512 // condition code is 1, then we have to flip all the bits above the 5513 // terminating bit (which is the lowest 1 bit). 5514 if (pred & 1) { 5515 unsigned LowBit = mask & -mask; 5516 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5517 mask ^= BitsAboveLowBit; 5518 } 5519 5520 Inst.addOperand(MCOperand::createImm(pred)); 5521 Inst.addOperand(MCOperand::createImm(mask)); 5522 return S; 5523} 5524 5525static DecodeStatus 5526DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5527 uint64_t Address, const void *Decoder) { 5528 DecodeStatus S = MCDisassembler::Success; 5529 5530 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5531 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5532 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5533 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5534 unsigned W = fieldFromInstruction(Insn, 21, 1); 5535 unsigned U = fieldFromInstruction(Insn, 23, 1); 5536 unsigned P = fieldFromInstruction(Insn, 24, 1); 5537 bool writeback = (W == 1) | (P == 0); 5538 5539 addr |= (U << 8) | (Rn << 9); 5540 5541 if (writeback && (Rn == Rt || Rn == Rt2)) 5542 Check(S, MCDisassembler::SoftFail); 5543 if (Rt == Rt2) 5544 Check(S, MCDisassembler::SoftFail); 5545 5546 // Rt 5547 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5548 return MCDisassembler::Fail; 5549 // Rt2 5550 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5551 return MCDisassembler::Fail; 5552 // Writeback operand 5553 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5554 return MCDisassembler::Fail; 5555 // addr 5556 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5557 return MCDisassembler::Fail; 5558 5559 return S; 5560} 5561 5562static DecodeStatus 5563DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5564 uint64_t Address, const void *Decoder) { 5565 DecodeStatus S = MCDisassembler::Success; 5566 5567 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5568 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5570 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5571 unsigned W = fieldFromInstruction(Insn, 21, 1); 5572 unsigned U = fieldFromInstruction(Insn, 23, 1); 5573 unsigned P = fieldFromInstruction(Insn, 24, 1); 5574 bool writeback = (W == 1) | (P == 0); 5575 5576 addr |= (U << 8) | (Rn << 9); 5577 5578 if (writeback && (Rn == Rt || Rn == Rt2)) 5579 Check(S, MCDisassembler::SoftFail); 5580 5581 // Writeback operand 5582 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5583 return MCDisassembler::Fail; 5584 // Rt 5585 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5586 return MCDisassembler::Fail; 5587 // Rt2 5588 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5589 return MCDisassembler::Fail; 5590 // addr 5591 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5592 return MCDisassembler::Fail; 5593 5594 return S; 5595} 5596 5597static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5598 uint64_t Address, const void *Decoder) { 5599 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5600 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5601 if (sign1 != sign2) return MCDisassembler::Fail; 5602 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5603 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5604 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5605 5606 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5607 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5608 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5609 // If sign, then it is decreasing the address. 5610 if (sign1) { 5611 // Following ARMv7 Architecture Manual, when the offset 5612 // is zero, it is decoded as a subw, not as a adr.w 5613 if (!Val) { 5614 Inst.setOpcode(ARM::t2SUBri12); 5615 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5616 } else 5617 Val = -Val; 5618 } 5619 Inst.addOperand(MCOperand::createImm(Val)); 5620 return S; 5621} 5622 5623static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5624 uint64_t Address, 5625 const void *Decoder) { 5626 DecodeStatus S = MCDisassembler::Success; 5627 5628 // Shift of "asr #32" is not allowed in Thumb2 mode. 5629 if (Val == 0x20) S = MCDisassembler::Fail; 5630 Inst.addOperand(MCOperand::createImm(Val)); 5631 return S; 5632} 5633 5634static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5635 uint64_t Address, const void *Decoder) { 5636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5637 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5638 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5639 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5640 5641 if (pred == 0xF) 5642 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5643 5644 DecodeStatus S = MCDisassembler::Success; 5645 5646 if (Rt == Rn || Rn == Rt2) 5647 S = MCDisassembler::SoftFail; 5648 5649 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5650 return MCDisassembler::Fail; 5651 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5652 return MCDisassembler::Fail; 5653 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5654 return MCDisassembler::Fail; 5655 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5656 return MCDisassembler::Fail; 5657 5658 return S; 5659} 5660 5661static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5662 uint64_t Address, const void *Decoder) { 5663 const FeatureBitset &featureBits = 5664 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5665 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5666 5667 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5668 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5669 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5670 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5671 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5672 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5673 unsigned op = fieldFromInstruction(Insn, 5, 1); 5674 5675 DecodeStatus S = MCDisassembler::Success; 5676 5677 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5678 if (!(imm & 0x38)) { 5679 if (cmode == 0xF) { 5680 if (op == 1) return MCDisassembler::Fail; 5681 Inst.setOpcode(ARM::VMOVv2f32); 5682 } 5683 if (hasFullFP16) { 5684 if (cmode == 0xE) { 5685 if (op == 1) { 5686 Inst.setOpcode(ARM::VMOVv1i64); 5687 } else { 5688 Inst.setOpcode(ARM::VMOVv8i8); 5689 } 5690 } 5691 if (cmode == 0xD) { 5692 if (op == 1) { 5693 Inst.setOpcode(ARM::VMVNv2i32); 5694 } else { 5695 Inst.setOpcode(ARM::VMOVv2i32); 5696 } 5697 } 5698 if (cmode == 0xC) { 5699 if (op == 1) { 5700 Inst.setOpcode(ARM::VMVNv2i32); 5701 } else { 5702 Inst.setOpcode(ARM::VMOVv2i32); 5703 } 5704 } 5705 } 5706 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5707 } 5708 5709 if (!(imm & 0x20)) return MCDisassembler::Fail; 5710 5711 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5712 return MCDisassembler::Fail; 5713 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5714 return MCDisassembler::Fail; 5715 Inst.addOperand(MCOperand::createImm(64 - imm)); 5716 5717 return S; 5718} 5719 5720static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5721 uint64_t Address, const void *Decoder) { 5722 const FeatureBitset &featureBits = 5723 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5724 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5725 5726 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5727 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5728 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5729 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5730 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5731 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5732 unsigned op = fieldFromInstruction(Insn, 5, 1); 5733 5734 DecodeStatus S = MCDisassembler::Success; 5735 5736 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5737 if (!(imm & 0x38)) { 5738 if (cmode == 0xF) { 5739 if (op == 1) return MCDisassembler::Fail; 5740 Inst.setOpcode(ARM::VMOVv4f32); 5741 } 5742 if (hasFullFP16) { 5743 if (cmode == 0xE) { 5744 if (op == 1) { 5745 Inst.setOpcode(ARM::VMOVv2i64); 5746 } else { 5747 Inst.setOpcode(ARM::VMOVv16i8); 5748 } 5749 } 5750 if (cmode == 0xD) { 5751 if (op == 1) { 5752 Inst.setOpcode(ARM::VMVNv4i32); 5753 } else { 5754 Inst.setOpcode(ARM::VMOVv4i32); 5755 } 5756 } 5757 if (cmode == 0xC) { 5758 if (op == 1) { 5759 Inst.setOpcode(ARM::VMVNv4i32); 5760 } else { 5761 Inst.setOpcode(ARM::VMOVv4i32); 5762 } 5763 } 5764 } 5765 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5766 } 5767 5768 if (!(imm & 0x20)) return MCDisassembler::Fail; 5769 5770 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5771 return MCDisassembler::Fail; 5772 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5773 return MCDisassembler::Fail; 5774 Inst.addOperand(MCOperand::createImm(64 - imm)); 5775 5776 return S; 5777} 5778 5779static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5780 unsigned Insn, 5781 uint64_t Address, 5782 const void *Decoder) { 5783 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5784 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5785 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5786 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5787 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5788 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5789 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5790 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5791 5792 DecodeStatus S = MCDisassembler::Success; 5793 5794 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5795 5796 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5797 return MCDisassembler::Fail; 5798 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5799 return MCDisassembler::Fail; 5800 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5801 return MCDisassembler::Fail; 5802 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5803 return MCDisassembler::Fail; 5804 // The lane index does not have any bits in the encoding, because it can only 5805 // be 0. 5806 Inst.addOperand(MCOperand::createImm(0)); 5807 Inst.addOperand(MCOperand::createImm(rotate)); 5808 5809 return S; 5810} 5811 5812static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5813 uint64_t Address, const void *Decoder) { 5814 DecodeStatus S = MCDisassembler::Success; 5815 5816 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5817 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5818 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5819 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5820 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5821 5822 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5823 S = MCDisassembler::SoftFail; 5824 5825 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5826 return MCDisassembler::Fail; 5827 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5830 return MCDisassembler::Fail; 5831 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5832 return MCDisassembler::Fail; 5833 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5834 return MCDisassembler::Fail; 5835 5836 return S; 5837} 5838 5839static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5840 uint64_t Address, const void *Decoder) { 5841 DecodeStatus S = MCDisassembler::Success; 5842 5843 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5844 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5845 unsigned cop = fieldFromInstruction(Val, 8, 4); 5846 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5847 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5848 5849 if ((cop & ~0x1) == 0xa) 5850 return MCDisassembler::Fail; 5851 5852 if (Rt == Rt2) 5853 S = MCDisassembler::SoftFail; 5854 5855 // We have to check if the instruction is MRRC2 5856 // or MCRR2 when constructing the operands for 5857 // Inst. Reason is because MRRC2 stores to two 5858 // registers so it's tablegen desc has has two 5859 // outputs whereas MCRR doesn't store to any 5860 // registers so all of it's operands are listed 5861 // as inputs, therefore the operand order for 5862 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5863 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5864 5865 if (Inst.getOpcode() == ARM::MRRC2) { 5866 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5867 return MCDisassembler::Fail; 5868 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5869 return MCDisassembler::Fail; 5870 } 5871 Inst.addOperand(MCOperand::createImm(cop)); 5872 Inst.addOperand(MCOperand::createImm(opc1)); 5873 if (Inst.getOpcode() == ARM::MCRR2) { 5874 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5875 return MCDisassembler::Fail; 5876 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5877 return MCDisassembler::Fail; 5878 } 5879 Inst.addOperand(MCOperand::createImm(CRm)); 5880 5881 return S; 5882} 5883 5884static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5885 uint64_t Address, 5886 const void *Decoder) { 5887 const FeatureBitset &featureBits = 5888 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5889 DecodeStatus S = MCDisassembler::Success; 5890 5891 // Add explicit operand for the destination sysreg, for cases where 5892 // we have to model it for code generation purposes. 5893 switch (Inst.getOpcode()) { 5894 case ARM::VMSR_FPSCR_NZCVQC: 5895 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5896 break; 5897 case ARM::VMSR_P0: 5898 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5899 break; 5900 } 5901 5902 if (Inst.getOpcode() != ARM::FMSTAT) { 5903 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5904 5905 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5906 if (Rt == 13 || Rt == 15) 5907 S = MCDisassembler::SoftFail; 5908 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5909 } else 5910 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5911 } 5912 5913 // Add explicit operand for the source sysreg, similarly to above. 5914 switch (Inst.getOpcode()) { 5915 case ARM::VMRS_FPSCR_NZCVQC: 5916 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5917 break; 5918 case ARM::VMRS_P0: 5919 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5920 break; 5921 } 5922 5923 if (featureBits[ARM::ModeThumb]) { 5924 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5925 Inst.addOperand(MCOperand::createReg(0)); 5926 } else { 5927 unsigned pred = fieldFromInstruction(Val, 28, 4); 5928 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5929 return MCDisassembler::Fail; 5930 } 5931 5932 return S; 5933} 5934 5935template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5936static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5937 uint64_t Address, 5938 const void *Decoder) { 5939 DecodeStatus S = MCDisassembler::Success; 5940 if (Val == 0 && !zeroPermitted) 5941 S = MCDisassembler::Fail; 5942 5943 uint64_t DecVal; 5944 if (isSigned) 5945 DecVal = SignExtend32<size + 1>(Val << 1); 5946 else 5947 DecVal = (Val << 1); 5948 5949 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5950 Decoder)) 5951 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5952 return S; 5953} 5954 5955static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5956 uint64_t Address, 5957 const void *Decoder) { 5958 5959 uint64_t LocImm = Inst.getOperand(0).getImm(); 5960 Val = LocImm + (2 << Val); 5961 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5962 Decoder)) 5963 Inst.addOperand(MCOperand::createImm(Val)); 5964 return MCDisassembler::Success; 5965} 5966 5967static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5968 uint64_t Address, 5969 const void *Decoder) { 5970 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5971 return MCDisassembler::Fail; 5972 Inst.addOperand(MCOperand::createImm(Val)); 5973 return MCDisassembler::Success; 5974} 5975 5976static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5977 const void *Decoder) { 5978 DecodeStatus S = MCDisassembler::Success; 5979 5980 if (Inst.getOpcode() == ARM::MVE_LCTP) 5981 return S; 5982 5983 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5984 fieldFromInstruction(Insn, 1, 10) << 1; 5985 switch (Inst.getOpcode()) { 5986 case ARM::t2LEUpdate: 5987 case ARM::MVE_LETP: 5988 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5989 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5990 LLVM_FALLTHROUGH; 5991 case ARM::t2LE: 5992 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 5993 Inst, Imm, Address, Decoder))) 5994 return MCDisassembler::Fail; 5995 break; 5996 case ARM::t2WLS: 5997 case ARM::MVE_WLSTP_8: 5998 case ARM::MVE_WLSTP_16: 5999 case ARM::MVE_WLSTP_32: 6000 case ARM::MVE_WLSTP_64: 6001 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6002 if (!Check(S, 6003 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6004 Address, Decoder)) || 6005 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6006 Inst, Imm, Address, Decoder))) 6007 return MCDisassembler::Fail; 6008 break; 6009 case ARM::t2DLS: 6010 case ARM::MVE_DLSTP_8: 6011 case ARM::MVE_DLSTP_16: 6012 case ARM::MVE_DLSTP_32: 6013 case ARM::MVE_DLSTP_64: 6014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6015 if (Rn == 0xF) { 6016 // Enforce all the rest of the instruction bits in LCTP, which 6017 // won't have been reliably checked based on LCTP's own tablegen 6018 // record, because we came to this decode by a roundabout route. 6019 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6020 if ((Insn & ~SBZMask) != CanonicalLCTP) 6021 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6022 if (Insn != CanonicalLCTP) 6023 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6024 6025 Inst.setOpcode(ARM::MVE_LCTP); 6026 } else { 6027 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6028 if (!Check(S, DecoderGPRRegisterClass(Inst, 6029 fieldFromInstruction(Insn, 16, 4), 6030 Address, Decoder))) 6031 return MCDisassembler::Fail; 6032 } 6033 break; 6034 } 6035 return S; 6036} 6037 6038static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6039 uint64_t Address, 6040 const void *Decoder) { 6041 DecodeStatus S = MCDisassembler::Success; 6042 6043 if (Val == 0) 6044 Val = 32; 6045 6046 Inst.addOperand(MCOperand::createImm(Val)); 6047 6048 return S; 6049} 6050 6051static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6052 uint64_t Address, const void *Decoder) { 6053 if ((RegNo) + 1 > 11) 6054 return MCDisassembler::Fail; 6055 6056 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6057 Inst.addOperand(MCOperand::createReg(Register)); 6058 return MCDisassembler::Success; 6059} 6060 6061static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6062 uint64_t Address, const void *Decoder) { 6063 if ((RegNo) > 14) 6064 return MCDisassembler::Fail; 6065 6066 unsigned Register = GPRDecoderTable[(RegNo)]; 6067 Inst.addOperand(MCOperand::createReg(Register)); 6068 return MCDisassembler::Success; 6069} 6070 6071static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6072 const void *Decoder) { 6073 DecodeStatus S = MCDisassembler::Success; 6074 6075 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6076 Inst.addOperand(MCOperand::createReg(0)); 6077 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6078 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6079 (fieldFromInstruction(Insn, 12, 4) << 8) | 6080 (fieldFromInstruction(Insn, 22, 1) << 12); 6081 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6082 return MCDisassembler::Fail; 6083 } 6084 } else { 6085 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6086 (fieldFromInstruction(Insn, 22, 1) << 8) | 6087 (fieldFromInstruction(Insn, 12, 4) << 9); 6088 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6089 return MCDisassembler::Fail; 6090 } 6091 } 6092 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6093 6094 return S; 6095} 6096 6097static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6098 uint64_t Address, 6099 const void *Decoder) { 6100 if (RegNo > 7) 6101 return MCDisassembler::Fail; 6102 6103 unsigned Register = QPRDecoderTable[RegNo]; 6104 Inst.addOperand(MCOperand::createReg(Register)); 6105 return MCDisassembler::Success; 6106} 6107 6108static const uint16_t QQPRDecoderTable[] = { 6109 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6110 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6111}; 6112 6113static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6114 uint64_t Address, 6115 const void *Decoder) { 6116 if (RegNo > 6) 6117 return MCDisassembler::Fail; 6118 6119 unsigned Register = QQPRDecoderTable[RegNo]; 6120 Inst.addOperand(MCOperand::createReg(Register)); 6121 return MCDisassembler::Success; 6122} 6123 6124static const uint16_t QQQQPRDecoderTable[] = { 6125 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6126 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6127}; 6128 6129static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6130 uint64_t Address, 6131 const void *Decoder) { 6132 if (RegNo > 4) 6133 return MCDisassembler::Fail; 6134 6135 unsigned Register = QQQQPRDecoderTable[RegNo]; 6136 Inst.addOperand(MCOperand::createReg(Register)); 6137 return MCDisassembler::Success; 6138} 6139 6140static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6141 uint64_t Address, 6142 const void *Decoder) { 6143 DecodeStatus S = MCDisassembler::Success; 6144 6145 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6146 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6147 // 't' as 0 and finish with a 1. 6148 unsigned Imm = 0; 6149 // We always start with a 't'. 6150 unsigned CurBit = 0; 6151 for (int i = 3; i >= 0; --i) { 6152 // If the bit we are looking at is not the same as last one, invert the 6153 // CurBit, if it is the same leave it as is. 6154 CurBit ^= (Val >> i) & 1U; 6155 6156 // Encode the CurBit at the right place in the immediate. 6157 Imm |= (CurBit << i); 6158 6159 // If we are done, finish the encoding with a 1. 6160 if ((Val & ~(~0U << i)) == 0) { 6161 Imm |= 1U << i; 6162 break; 6163 } 6164 } 6165 6166 Inst.addOperand(MCOperand::createImm(Imm)); 6167 6168 return S; 6169} 6170 6171static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6172 uint64_t Address, const void *Decoder) { 6173 // The vpred_r operand type includes an MQPR register field derived 6174 // from the encoding. But we don't actually want to add an operand 6175 // to the MCInst at this stage, because AddThumbPredicate will do it 6176 // later, and will infer the register number from the TIED_TO 6177 // constraint. So this is a deliberately empty decoder method that 6178 // will inhibit the auto-generated disassembly code from adding an 6179 // operand at all. 6180 return MCDisassembler::Success; 6181} 6182 6183static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6184 unsigned Val, 6185 uint64_t Address, 6186 const void *Decoder) { 6187 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6188 return MCDisassembler::Success; 6189} 6190 6191static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6192 unsigned Val, 6193 uint64_t Address, 6194 const void *Decoder) { 6195 unsigned Code; 6196 switch (Val & 0x3) { 6197 case 0: 6198 Code = ARMCC::GE; 6199 break; 6200 case 1: 6201 Code = ARMCC::LT; 6202 break; 6203 case 2: 6204 Code = ARMCC::GT; 6205 break; 6206 case 3: 6207 Code = ARMCC::LE; 6208 break; 6209 } 6210 Inst.addOperand(MCOperand::createImm(Code)); 6211 return MCDisassembler::Success; 6212} 6213 6214static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6215 unsigned Val, 6216 uint64_t Address, 6217 const void *Decoder) { 6218 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6219 return MCDisassembler::Success; 6220} 6221 6222static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6223 uint64_t Address, 6224 const void *Decoder) { 6225 unsigned Code; 6226 switch (Val) { 6227 default: 6228 return MCDisassembler::Fail; 6229 case 0: 6230 Code = ARMCC::EQ; 6231 break; 6232 case 1: 6233 Code = ARMCC::NE; 6234 break; 6235 case 4: 6236 Code = ARMCC::GE; 6237 break; 6238 case 5: 6239 Code = ARMCC::LT; 6240 break; 6241 case 6: 6242 Code = ARMCC::GT; 6243 break; 6244 case 7: 6245 Code = ARMCC::LE; 6246 break; 6247 } 6248 6249 Inst.addOperand(MCOperand::createImm(Code)); 6250 return MCDisassembler::Success; 6251} 6252 6253static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6254 uint64_t Address, const void *Decoder) { 6255 DecodeStatus S = MCDisassembler::Success; 6256 6257 unsigned DecodedVal = 64 - Val; 6258 6259 switch (Inst.getOpcode()) { 6260 case ARM::MVE_VCVTf16s16_fix: 6261 case ARM::MVE_VCVTs16f16_fix: 6262 case ARM::MVE_VCVTf16u16_fix: 6263 case ARM::MVE_VCVTu16f16_fix: 6264 if (DecodedVal > 16) 6265 return MCDisassembler::Fail; 6266 break; 6267 case ARM::MVE_VCVTf32s32_fix: 6268 case ARM::MVE_VCVTs32f32_fix: 6269 case ARM::MVE_VCVTf32u32_fix: 6270 case ARM::MVE_VCVTu32f32_fix: 6271 if (DecodedVal > 32) 6272 return MCDisassembler::Fail; 6273 break; 6274 } 6275 6276 Inst.addOperand(MCOperand::createImm(64 - Val)); 6277 6278 return S; 6279} 6280 6281static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6282 switch (Opcode) { 6283 case ARM::VSTR_P0_off: 6284 case ARM::VSTR_P0_pre: 6285 case ARM::VSTR_P0_post: 6286 case ARM::VLDR_P0_off: 6287 case ARM::VLDR_P0_pre: 6288 case ARM::VLDR_P0_post: 6289 return ARM::P0; 6290 default: 6291 return 0; 6292 } 6293} 6294 6295template<bool Writeback> 6296static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6297 uint64_t Address, 6298 const void *Decoder) { 6299 switch (Inst.getOpcode()) { 6300 case ARM::VSTR_FPSCR_pre: 6301 case ARM::VSTR_FPSCR_NZCVQC_pre: 6302 case ARM::VLDR_FPSCR_pre: 6303 case ARM::VLDR_FPSCR_NZCVQC_pre: 6304 case ARM::VSTR_FPSCR_off: 6305 case ARM::VSTR_FPSCR_NZCVQC_off: 6306 case ARM::VLDR_FPSCR_off: 6307 case ARM::VLDR_FPSCR_NZCVQC_off: 6308 case ARM::VSTR_FPSCR_post: 6309 case ARM::VSTR_FPSCR_NZCVQC_post: 6310 case ARM::VLDR_FPSCR_post: 6311 case ARM::VLDR_FPSCR_NZCVQC_post: 6312 const FeatureBitset &featureBits = 6313 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6314 6315 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6316 return MCDisassembler::Fail; 6317 } 6318 6319 DecodeStatus S = MCDisassembler::Success; 6320 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6321 Inst.addOperand(MCOperand::createReg(Sysreg)); 6322 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6323 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6324 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6325 6326 if (Writeback) { 6327 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6328 return MCDisassembler::Fail; 6329 } 6330 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6331 return MCDisassembler::Fail; 6332 6333 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6334 Inst.addOperand(MCOperand::createReg(0)); 6335 6336 return S; 6337} 6338 6339static inline DecodeStatus DecodeMVE_MEM_pre( 6340 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6341 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6342 DecodeStatus S = MCDisassembler::Success; 6343 6344 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6345 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6346 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6347 6348 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6349 return MCDisassembler::Fail; 6350 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6351 return MCDisassembler::Fail; 6352 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6353 return MCDisassembler::Fail; 6354 6355 return S; 6356} 6357 6358template <int shift> 6359static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6360 uint64_t Address, const void *Decoder) { 6361 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6362 fieldFromInstruction(Val, 16, 3), 6363 DecodetGPRRegisterClass, 6364 DecodeTAddrModeImm7<shift>); 6365} 6366 6367template <int shift> 6368static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6369 uint64_t Address, const void *Decoder) { 6370 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6371 fieldFromInstruction(Val, 16, 4), 6372 DecoderGPRRegisterClass, 6373 DecodeT2AddrModeImm7<shift,1>); 6374} 6375 6376template <int shift> 6377static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6378 uint64_t Address, const void *Decoder) { 6379 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6380 fieldFromInstruction(Val, 17, 3), 6381 DecodeMQPRRegisterClass, 6382 DecodeMveAddrModeQ<shift>); 6383} 6384 6385template<unsigned MinLog, unsigned MaxLog> 6386static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6387 uint64_t Address, 6388 const void *Decoder) { 6389 DecodeStatus S = MCDisassembler::Success; 6390 6391 if (Val < MinLog || Val > MaxLog) 6392 return MCDisassembler::Fail; 6393 6394 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6395 return S; 6396} 6397 6398template <int shift> 6399static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6400 uint64_t Address, 6401 const void *Decoder) { 6402 Val <<= shift; 6403 6404 Inst.addOperand(MCOperand::createImm(Val)); 6405 return MCDisassembler::Success; 6406} 6407 6408template<unsigned start> 6409static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6410 uint64_t Address, 6411 const void *Decoder) { 6412 DecodeStatus S = MCDisassembler::Success; 6413 6414 Inst.addOperand(MCOperand::createImm(start + Val)); 6415 6416 return S; 6417} 6418 6419static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6420 uint64_t Address, const void *Decoder) { 6421 DecodeStatus S = MCDisassembler::Success; 6422 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6423 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6424 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6425 fieldFromInstruction(Insn, 13, 3)); 6426 unsigned index = fieldFromInstruction(Insn, 4, 1); 6427 6428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6429 return MCDisassembler::Fail; 6430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6431 return MCDisassembler::Fail; 6432 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6433 return MCDisassembler::Fail; 6434 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6435 return MCDisassembler::Fail; 6436 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6437 return MCDisassembler::Fail; 6438 6439 return S; 6440} 6441 6442static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6443 uint64_t Address, const void *Decoder) { 6444 DecodeStatus S = MCDisassembler::Success; 6445 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6446 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6447 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6448 fieldFromInstruction(Insn, 13, 3)); 6449 unsigned index = fieldFromInstruction(Insn, 4, 1); 6450 6451 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6452 return MCDisassembler::Fail; 6453 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6454 return MCDisassembler::Fail; 6455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6456 return MCDisassembler::Fail; 6457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6458 return MCDisassembler::Fail; 6459 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6460 return MCDisassembler::Fail; 6461 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6462 return MCDisassembler::Fail; 6463 6464 return S; 6465} 6466 6467static DecodeStatus DecodeMVEOverlappingLongShift( 6468 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6469 DecodeStatus S = MCDisassembler::Success; 6470 6471 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6472 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6473 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6474 6475 if (RdaHi == 14) { 6476 // This value of RdaHi (really indicating pc, because RdaHi has to 6477 // be an odd-numbered register, so the low bit will be set by the 6478 // decode function below) indicates that we must decode as SQRSHR 6479 // or UQRSHL, which both have a single Rda register field with all 6480 // four bits. 6481 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6482 6483 switch (Inst.getOpcode()) { 6484 case ARM::MVE_ASRLr: 6485 case ARM::MVE_SQRSHRL: 6486 Inst.setOpcode(ARM::MVE_SQRSHR); 6487 break; 6488 case ARM::MVE_LSLLr: 6489 case ARM::MVE_UQRSHLL: 6490 Inst.setOpcode(ARM::MVE_UQRSHL); 6491 break; 6492 default: 6493 llvm_unreachable("Unexpected starting opcode!"); 6494 } 6495 6496 // Rda as output parameter 6497 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6498 return MCDisassembler::Fail; 6499 6500 // Rda again as input parameter 6501 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6502 return MCDisassembler::Fail; 6503 6504 // Rm, the amount to shift by 6505 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6506 return MCDisassembler::Fail; 6507 6508 if (fieldFromInstruction (Insn, 6, 3) != 4) 6509 return MCDisassembler::SoftFail; 6510 6511 if (Rda == Rm) 6512 return MCDisassembler::SoftFail; 6513 6514 return S; 6515 } 6516 6517 // Otherwise, we decode as whichever opcode our caller has already 6518 // put into Inst. Those all look the same: 6519 6520 // RdaLo,RdaHi as output parameters 6521 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6522 return MCDisassembler::Fail; 6523 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6524 return MCDisassembler::Fail; 6525 6526 // RdaLo,RdaHi again as input parameters 6527 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6528 return MCDisassembler::Fail; 6529 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6530 return MCDisassembler::Fail; 6531 6532 // Rm, the amount to shift by 6533 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6534 return MCDisassembler::Fail; 6535 6536 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6537 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6538 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6539 // Saturate, the bit position for saturation 6540 Inst.addOperand(MCOperand::createImm(Saturate)); 6541 } 6542 6543 return S; 6544} 6545 6546static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6547 const void *Decoder) { 6548 DecodeStatus S = MCDisassembler::Success; 6549 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6550 fieldFromInstruction(Insn, 13, 3)); 6551 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6552 fieldFromInstruction(Insn, 1, 3)); 6553 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6554 6555 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6556 return MCDisassembler::Fail; 6557 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6558 return MCDisassembler::Fail; 6559 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6560 return MCDisassembler::Fail; 6561 6562 return S; 6563} 6564 6565template<bool scalar, OperandDecoder predicate_decoder> 6566static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6567 const void *Decoder) { 6568 DecodeStatus S = MCDisassembler::Success; 6569 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6570 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6571 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6572 return MCDisassembler::Fail; 6573 6574 unsigned fc; 6575 6576 if (scalar) { 6577 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6578 fieldFromInstruction(Insn, 7, 1) | 6579 fieldFromInstruction(Insn, 5, 1) << 1; 6580 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6581 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6582 return MCDisassembler::Fail; 6583 } else { 6584 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6585 fieldFromInstruction(Insn, 7, 1) | 6586 fieldFromInstruction(Insn, 0, 1) << 1; 6587 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6588 fieldFromInstruction(Insn, 1, 3); 6589 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6590 return MCDisassembler::Fail; 6591 } 6592 6593 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6594 return MCDisassembler::Fail; 6595 6596 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6597 Inst.addOperand(MCOperand::createReg(0)); 6598 Inst.addOperand(MCOperand::createImm(0)); 6599 6600 return S; 6601} 6602 6603static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6604 const void *Decoder) { 6605 DecodeStatus S = MCDisassembler::Success; 6606 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6608 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6609 return MCDisassembler::Fail; 6610 return S; 6611} 6612 6613static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6614 const void *Decoder) { 6615 DecodeStatus S = MCDisassembler::Success; 6616 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6617 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6618 return S; 6619} 6620 6621static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6622 uint64_t Address, const void *Decoder) { 6623 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6624 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6625 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6626 fieldFromInstruction(Insn, 12, 3) << 8 | 6627 fieldFromInstruction(Insn, 0, 8); 6628 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6629 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6630 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6631 unsigned S = fieldFromInstruction(Insn, 20, 1); 6632 if (sign1 != sign2) 6633 return MCDisassembler::Fail; 6634 6635 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6636 DecodeStatus DS = MCDisassembler::Success; 6637 if ((!Check(DS, 6638 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6639 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6640 return MCDisassembler::Fail; 6641 if (TypeT3) { 6642 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6643 S = 0; 6644 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6645 } else { 6646 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6647 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6648 return MCDisassembler::Fail; 6649 } 6650 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6651 return MCDisassembler::Fail; 6652 6653 Inst.addOperand(MCOperand::createReg(0)); // pred 6654 6655 return DS; 6656} 6657