Lines Matching refs:ARM
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
129 /// ARM disassembler for all ARM platforms.
586 case ARM::HVC: {
596 case ARM::t2ADDri:
597 case ARM::t2ADDri12:
598 case ARM::t2ADDrr:
599 case ARM::t2ADDrs:
600 case ARM::t2SUBri:
601 case ARM::t2SUBri12:
602 case ARM::t2SUBrr:
603 case ARM::t2SUBrs:
604 if (MI.getOperand(0).getReg() == ARM::SP &&
605 MI.getOperand(1).getReg() != ARM::SP)
616 if (STI.getFeatureBits()[ARM::ModeThumb])
627 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
628 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
736 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
750 if (ARM::isVpred(OpInfo[i].OperandType))
769 case ARM::tBcc:
770 case ARM::t2Bcc:
771 case ARM::tCBZ:
772 case ARM::tCBNZ:
773 case ARM::tCPS:
774 case ARM::t2CPS3p:
775 case ARM::t2CPS2p:
776 case ARM::t2CPS1p:
777 case ARM::t2CSEL:
778 case ARM::t2CSINC:
779 case ARM::t2CSINV:
780 case ARM::t2CSNEG:
781 case ARM::tMOVSr:
782 case ARM::tSETEND:
790 case ARM::t2HINT:
791 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
794 case ARM::tB:
795 case ARM::t2B:
796 case ARM::t2TBB:
797 case ARM::t2TBH:
839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
847 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
856 MI.insert(VCCI, MCOperand::createReg(ARM::P0));
857 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
872 // encodings between ARM and Thumb modes, and they are predicable in ARM
901 I->setReg(ARM::CPSR);
913 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
914 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
948 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
956 if (MI.getOpcode() == ARM::t2IT) {
1114 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1115 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1116 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1121 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1122 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1123 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1124 ARM::R12, 0, ARM::LR, ARM::APSR
1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1186 Inst.addOperand(MCOperand::createReg(ARM::ZR));
1215 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1216 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1250 Register = ARM::R0;
1253 Register = ARM::R1;
1256 Register = ARM::R2;
1259 Register = ARM::R3;
1262 Register = ARM::R9;
1265 Register = ARM::R12;
1282 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1290 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1291 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1292 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1293 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1294 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1295 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1296 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1297 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1316 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1318 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1319 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1320 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1321 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1322 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1323 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1331 bool hasD32 = featureBits[ARM::FeatureD32];
1364 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1365 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1366 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1367 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1382 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1384 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1385 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1386 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1387 ARM::Q15
1401 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1402 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1403 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1404 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1405 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1406 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1407 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1408 ARM::D28_D30, ARM::D29_D31
1428 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1436 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1443 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1531 case ARM::LDMIA_UPD:
1532 case ARM::LDMDB_UPD:
1533 case ARM::LDMIB_UPD:
1534 case ARM::LDMDA_UPD:
1535 case ARM::t2LDMIA_UPD:
1536 case ARM::t2LDMDB_UPD:
1537 case ARM::t2STMIA_UPD:
1538 case ARM::t2STMDB_UPD:
1542 case ARM::t2CLRM:
1658 case ARM::LDC_OFFSET:
1659 case ARM::LDC_PRE:
1660 case ARM::LDC_POST:
1661 case ARM::LDC_OPTION:
1662 case ARM::LDCL_OFFSET:
1663 case ARM::LDCL_PRE:
1664 case ARM::LDCL_POST:
1665 case ARM::LDCL_OPTION:
1666 case ARM::STC_OFFSET:
1667 case ARM::STC_PRE:
1668 case ARM::STC_POST:
1669 case ARM::STC_OPTION:
1670 case ARM::STCL_OFFSET:
1671 case ARM::STCL_PRE:
1672 case ARM::STCL_POST:
1673 case ARM::STCL_OPTION:
1674 case ARM::t2LDC_OFFSET:
1675 case ARM::t2LDC_PRE:
1676 case ARM::t2LDC_POST:
1677 case ARM::t2LDC_OPTION:
1678 case ARM::t2LDCL_OFFSET:
1679 case ARM::t2LDCL_PRE:
1680 case ARM::t2LDCL_POST:
1681 case ARM::t2LDCL_OPTION:
1682 case ARM::t2STC_OFFSET:
1683 case ARM::t2STC_PRE:
1684 case ARM::t2STC_POST:
1685 case ARM::t2STC_OPTION:
1686 case ARM::t2STCL_OFFSET:
1687 case ARM::t2STCL_PRE:
1688 case ARM::t2STCL_POST:
1689 case ARM::t2STCL_OPTION:
1690 case ARM::t2LDC2_OFFSET:
1691 case ARM::t2LDC2L_OFFSET:
1692 case ARM::t2LDC2_PRE:
1693 case ARM::t2LDC2L_PRE:
1694 case ARM::t2STC2_OFFSET:
1695 case ARM::t2STC2L_OFFSET:
1696 case ARM::t2STC2_PRE:
1697 case ARM::t2STC2L_PRE:
1698 case ARM::LDC2_OFFSET:
1699 case ARM::LDC2L_OFFSET:
1700 case ARM::LDC2_PRE:
1701 case ARM::LDC2L_PRE:
1702 case ARM::STC2_OFFSET:
1703 case ARM::STC2L_OFFSET:
1704 case ARM::STC2_PRE:
1705 case ARM::STC2L_PRE:
1706 case ARM::t2LDC2_OPTION:
1707 case ARM::t2STC2_OPTION:
1708 case ARM::t2LDC2_POST:
1709 case ARM::t2LDC2L_POST:
1710 case ARM::t2STC2_POST:
1711 case ARM::t2STC2L_POST:
1712 case ARM::LDC2_POST:
1713 case ARM::LDC2L_POST:
1714 case ARM::STC2_POST:
1715 case ARM::STC2L_POST:
1717 (featureBits[ARM::HasV8_1MMainlineOps] &&
1726 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1735 case ARM::t2LDC2_OFFSET:
1736 case ARM::t2LDC2L_OFFSET:
1737 case ARM::t2LDC2_PRE:
1738 case ARM::t2LDC2L_PRE:
1739 case ARM::t2STC2_OFFSET:
1740 case ARM::t2STC2L_OFFSET:
1741 case ARM::t2STC2_PRE:
1742 case ARM::t2STC2L_PRE:
1743 case ARM::LDC2_OFFSET:
1744 case ARM::LDC2L_OFFSET:
1745 case ARM::LDC2_PRE:
1746 case ARM::LDC2L_PRE:
1747 case ARM::STC2_OFFSET:
1748 case ARM::STC2L_OFFSET:
1749 case ARM::STC2_PRE:
1750 case ARM::STC2L_PRE:
1751 case ARM::t2LDC_OFFSET:
1752 case ARM::t2LDCL_OFFSET:
1753 case ARM::t2LDC_PRE:
1754 case ARM::t2LDCL_PRE:
1755 case ARM::t2STC_OFFSET:
1756 case ARM::t2STCL_OFFSET:
1757 case ARM::t2STC_PRE:
1758 case ARM::t2STCL_PRE:
1759 case ARM::LDC_OFFSET:
1760 case ARM::LDCL_OFFSET:
1761 case ARM::LDC_PRE:
1762 case ARM::LDCL_PRE:
1763 case ARM::STC_OFFSET:
1764 case ARM::STCL_OFFSET:
1765 case ARM::STC_PRE:
1766 case ARM::STCL_PRE:
1770 case ARM::t2LDC2_POST:
1771 case ARM::t2LDC2L_POST:
1772 case ARM::t2STC2_POST:
1773 case ARM::t2STC2L_POST:
1774 case ARM::LDC2_POST:
1775 case ARM::LDC2L_POST:
1776 case ARM::STC2_POST:
1777 case ARM::STC2L_POST:
1778 case ARM::t2LDC_POST:
1779 case ARM::t2LDCL_POST:
1780 case ARM::t2STC_POST:
1781 case ARM::t2STCL_POST:
1782 case ARM::LDC_POST:
1783 case ARM::LDCL_POST:
1784 case ARM::STC_POST:
1785 case ARM::STCL_POST:
1796 case ARM::LDC_OFFSET:
1797 case ARM::LDC_PRE:
1798 case ARM::LDC_POST:
1799 case ARM::LDC_OPTION:
1800 case ARM::LDCL_OFFSET:
1801 case ARM::LDCL_PRE:
1802 case ARM::LDCL_POST:
1803 case ARM::LDCL_OPTION:
1804 case ARM::STC_OFFSET:
1805 case ARM::STC_PRE:
1806 case ARM::STC_POST:
1807 case ARM::STC_OPTION:
1808 case ARM::STCL_OFFSET:
1809 case ARM::STCL_PRE:
1810 case ARM::STCL_POST:
1811 case ARM::STCL_OPTION:
1838 case ARM::STR_POST_IMM:
1839 case ARM::STR_POST_REG:
1840 case ARM::STRB_POST_IMM:
1841 case ARM::STRB_POST_REG:
1842 case ARM::STRT_POST_REG:
1843 case ARM::STRT_POST_IMM:
1844 case ARM::STRBT_POST_REG:
1845 case ARM::STRBT_POST_IMM:
1858 case ARM::LDR_POST_IMM:
1859 case ARM::LDR_POST_REG:
1860 case ARM::LDRB_POST_IMM:
1861 case ARM::LDRB_POST_REG:
1862 case ARM::LDRBT_POST_REG:
1863 case ARM::LDRBT_POST_IMM:
1864 case ARM::LDRT_POST_REG:
1865 case ARM::LDRT_POST_IMM:
1991 case ARM::STRD:
1992 case ARM::STRD_PRE:
1993 case ARM::STRD_POST:
1994 case ARM::LDRD:
1995 case ARM::LDRD_PRE:
1996 case ARM::LDRD_POST:
2003 case ARM::STRD:
2004 case ARM::STRD_PRE:
2005 case ARM::STRD_POST:
2018 case ARM::STRH:
2019 case ARM::STRH_PRE:
2020 case ARM::STRH_POST:
2028 case ARM::LDRD:
2029 case ARM::LDRD_PRE:
2030 case ARM::LDRD_POST:
2045 case ARM::LDRH:
2046 case ARM::LDRH_PRE:
2047 case ARM::LDRH_POST:
2060 case ARM::LDRSH:
2061 case ARM::LDRSH_PRE:
2062 case ARM::LDRSH_POST:
2063 case ARM::LDRSB:
2064 case ARM::LDRSB_PRE:
2065 case ARM::LDRSB_POST:
2090 case ARM::STRD:
2091 case ARM::STRD_PRE:
2092 case ARM::STRD_POST:
2093 case ARM::STRH:
2094 case ARM::STRH_PRE:
2095 case ARM::STRH_POST:
2107 case ARM::STRD:
2108 case ARM::STRD_PRE:
2109 case ARM::STRD_POST:
2110 case ARM::LDRD:
2111 case ARM::LDRD_PRE:
2112 case ARM::LDRD_POST:
2123 case ARM::LDRD:
2124 case ARM::LDRD_PRE:
2125 case ARM::LDRD_POST:
2126 case ARM::LDRH:
2127 case ARM::LDRH_PRE:
2128 case ARM::LDRH_POST:
2129 case ARM::LDRSH:
2130 case ARM::LDRSH_PRE:
2131 case ARM::LDRSH_POST:
2132 case ARM::LDRSB:
2133 case ARM::LDRSB_PRE:
2134 case ARM::LDRSB_POST:
2135 case ARM::LDRHTr:
2136 case ARM::LDRSBTr:
2227 case ARM::LDMDA:
2228 Inst.setOpcode(ARM::RFEDA);
2230 case ARM::LDMDA_UPD:
2231 Inst.setOpcode(ARM::RFEDA_UPD);
2233 case ARM::LDMDB:
2234 Inst.setOpcode(ARM::RFEDB);
2236 case ARM::LDMDB_UPD:
2237 Inst.setOpcode(ARM::RFEDB_UPD);
2239 case ARM::LDMIA:
2240 Inst.setOpcode(ARM::RFEIA);
2242 case ARM::LDMIA_UPD:
2243 Inst.setOpcode(ARM::RFEIA_UPD);
2245 case ARM::LDMIB:
2246 Inst.setOpcode(ARM::RFEIB);
2248 case ARM::LDMIB_UPD:
2249 Inst.setOpcode(ARM::RFEIB_UPD);
2251 case ARM::STMDA:
2252 Inst.setOpcode(ARM::SRSDA);
2254 case ARM::STMDA_UPD:
2255 Inst.setOpcode(ARM::SRSDA_UPD);
2257 case ARM::STMDB:
2258 Inst.setOpcode(ARM::SRSDB);
2260 case ARM::STMDB_UPD:
2261 Inst.setOpcode(ARM::SRSDB_UPD);
2263 case ARM::STMIA:
2264 Inst.setOpcode(ARM::SRSIA);
2266 case ARM::STMIA_UPD:
2267 Inst.setOpcode(ARM::SRSIA_UPD);
2269 case ARM::STMIB:
2270 Inst.setOpcode(ARM::SRSIB);
2272 case ARM::STMIB_UPD:
2273 Inst.setOpcode(ARM::SRSIB_UPD);
2323 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2353 Inst.setOpcode(ARM::CPS3p);
2358 Inst.setOpcode(ARM::CPS2p);
2363 Inst.setOpcode(ARM::CPS1p);
2368 Inst.setOpcode(ARM::CPS1p);
2393 Inst.setOpcode(ARM::t2CPS3p);
2398 Inst.setOpcode(ARM::t2CPS2p);
2403 Inst.setOpcode(ARM::t2CPS1p);
2411 Inst.setOpcode(ARM::t2HINT);
2430 if (Inst.getOpcode() == ARM::t2MOVTi16)
2453 if (Inst.getOpcode() == ARM::MOVTi16)
2527 if (!FeatureBits[ARM::HasV8_1aOps] ||
2528 !FeatureBits[ARM::HasV8Ops])
2540 Inst.setOpcode(ARM::SETPAN);
2647 Inst.setOpcode(ARM::BLXi);
2694 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2695 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2696 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2697 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2698 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2699 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2700 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2701 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2702 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2706 case ARM::VLD2b16:
2707 case ARM::VLD2b32:
2708 case ARM::VLD2b8:
2709 case ARM::VLD2b16wb_fixed:
2710 case ARM::VLD2b16wb_register:
2711 case ARM::VLD2b32wb_fixed:
2712 case ARM::VLD2b32wb_register:
2713 case ARM::VLD2b8wb_fixed:
2714 case ARM::VLD2b8wb_register:
2725 case ARM::VLD3d8:
2726 case ARM::VLD3d16:
2727 case ARM::VLD3d32:
2728 case ARM::VLD3d8_UPD:
2729 case ARM::VLD3d16_UPD:
2730 case ARM::VLD3d32_UPD:
2731 case ARM::VLD4d8:
2732 case ARM::VLD4d16:
2733 case ARM::VLD4d32:
2734 case ARM::VLD4d8_UPD:
2735 case ARM::VLD4d16_UPD:
2736 case ARM::VLD4d32_UPD:
2740 case ARM::VLD3q8:
2741 case ARM::VLD3q16:
2742 case ARM::VLD3q32:
2743 case ARM::VLD3q8_UPD:
2744 case ARM::VLD3q16_UPD:
2745 case ARM::VLD3q32_UPD:
2746 case ARM::VLD4q8:
2747 case ARM::VLD4q16:
2748 case ARM::VLD4q32:
2749 case ARM::VLD4q8_UPD:
2750 case ARM::VLD4q16_UPD:
2751 case ARM::VLD4q32_UPD:
2761 case ARM::VLD3d8:
2762 case ARM::VLD3d16:
2763 case ARM::VLD3d32:
2764 case ARM::VLD3d8_UPD:
2765 case ARM::VLD3d16_UPD:
2766 case ARM::VLD3d32_UPD:
2767 case ARM::VLD4d8:
2768 case ARM::VLD4d16:
2769 case ARM::VLD4d32:
2770 case ARM::VLD4d8_UPD:
2771 case ARM::VLD4d16_UPD:
2772 case ARM::VLD4d32_UPD:
2776 case ARM::VLD3q8:
2777 case ARM::VLD3q16:
2778 case ARM::VLD3q32:
2779 case ARM::VLD3q8_UPD:
2780 case ARM::VLD3q16_UPD:
2781 case ARM::VLD3q32_UPD:
2782 case ARM::VLD4q8:
2783 case ARM::VLD4q16:
2784 case ARM::VLD4q32:
2785 case ARM::VLD4q8_UPD:
2786 case ARM::VLD4q16_UPD:
2787 case ARM::VLD4q32_UPD:
2797 case ARM::VLD4d8:
2798 case ARM::VLD4d16:
2799 case ARM::VLD4d32:
2800 case ARM::VLD4d8_UPD:
2801 case ARM::VLD4d16_UPD:
2802 case ARM::VLD4d32_UPD:
2806 case ARM::VLD4q8:
2807 case ARM::VLD4q16:
2808 case ARM::VLD4q32:
2809 case ARM::VLD4q8_UPD:
2810 case ARM::VLD4q16_UPD:
2811 case ARM::VLD4q32_UPD:
2821 case ARM::VLD1d8wb_fixed:
2822 case ARM::VLD1d16wb_fixed:
2823 case ARM::VLD1d32wb_fixed:
2824 case ARM::VLD1d64wb_fixed:
2825 case ARM::VLD1d8wb_register:
2826 case ARM::VLD1d16wb_register:
2827 case ARM::VLD1d32wb_register:
2828 case ARM::VLD1d64wb_register:
2829 case ARM::VLD1q8wb_fixed:
2830 case ARM::VLD1q16wb_fixed:
2831 case ARM::VLD1q32wb_fixed:
2832 case ARM::VLD1q64wb_fixed:
2833 case ARM::VLD1q8wb_register:
2834 case ARM::VLD1q16wb_register:
2835 case ARM::VLD1q32wb_register:
2836 case ARM::VLD1q64wb_register:
2837 case ARM::VLD1d8Twb_fixed:
2838 case ARM::VLD1d8Twb_register:
2839 case ARM::VLD1d16Twb_fixed:
2840 case ARM::VLD1d16Twb_register:
2841 case ARM::VLD1d32Twb_fixed:
2842 case ARM::VLD1d32Twb_register:
2843 case ARM::VLD1d64Twb_fixed:
2844 case ARM::VLD1d64Twb_register:
2845 case ARM::VLD1d8Qwb_fixed:
2846 case ARM::VLD1d8Qwb_register:
2847 case ARM::VLD1d16Qwb_fixed:
2848 case ARM::VLD1d16Qwb_register:
2849 case ARM::VLD1d32Qwb_fixed:
2850 case ARM::VLD1d32Qwb_register:
2851 case ARM::VLD1d64Qwb_fixed:
2852 case ARM::VLD1d64Qwb_register:
2853 case ARM::VLD2d8wb_fixed:
2854 case ARM::VLD2d16wb_fixed:
2855 case ARM::VLD2d32wb_fixed:
2856 case ARM::VLD2q8wb_fixed:
2857 case ARM::VLD2q16wb_fixed:
2858 case ARM::VLD2q32wb_fixed:
2859 case ARM::VLD2d8wb_register:
2860 case ARM::VLD2d16wb_register:
2861 case ARM::VLD2d32wb_register:
2862 case ARM::VLD2q8wb_register:
2863 case ARM::VLD2q16wb_register:
2864 case ARM::VLD2q32wb_register:
2865 case ARM::VLD2b8wb_fixed:
2866 case ARM::VLD2b16wb_fixed:
2867 case ARM::VLD2b32wb_fixed:
2868 case ARM::VLD2b8wb_register:
2869 case ARM::VLD2b16wb_register:
2870 case ARM::VLD2b32wb_register:
2873 case ARM::VLD3d8_UPD:
2874 case ARM::VLD3d16_UPD:
2875 case ARM::VLD3d32_UPD:
2876 case ARM::VLD3q8_UPD:
2877 case ARM::VLD3q16_UPD:
2878 case ARM::VLD3q32_UPD:
2879 case ARM::VLD4d8_UPD:
2880 case ARM::VLD4d16_UPD:
2881 case ARM::VLD4d32_UPD:
2882 case ARM::VLD4q8_UPD:
2883 case ARM::VLD4q16_UPD:
2884 case ARM::VLD4q32_UPD:
2911 case ARM::VLD1d8wb_fixed:
2912 case ARM::VLD1d16wb_fixed:
2913 case ARM::VLD1d32wb_fixed:
2914 case ARM::VLD1d64wb_fixed:
2915 case ARM::VLD1d8Twb_fixed:
2916 case ARM::VLD1d16Twb_fixed:
2917 case ARM::VLD1d32Twb_fixed:
2918 case ARM::VLD1d64Twb_fixed:
2919 case ARM::VLD1d8Qwb_fixed:
2920 case ARM::VLD1d16Qwb_fixed:
2921 case ARM::VLD1d32Qwb_fixed:
2922 case ARM::VLD1d64Qwb_fixed:
2923 case ARM::VLD1d8wb_register:
2924 case ARM::VLD1d16wb_register:
2925 case ARM::VLD1d32wb_register:
2926 case ARM::VLD1d64wb_register:
2927 case ARM::VLD1q8wb_fixed:
2928 case ARM::VLD1q16wb_fixed:
2929 case ARM::VLD1q32wb_fixed:
2930 case ARM::VLD1q64wb_fixed:
2931 case ARM::VLD1q8wb_register:
2932 case ARM::VLD1q16wb_register:
2933 case ARM::VLD1q32wb_register:
2934 case ARM::VLD1q64wb_register:
2942 case ARM::VLD2d8wb_fixed:
2943 case ARM::VLD2d16wb_fixed:
2944 case ARM::VLD2d32wb_fixed:
2945 case ARM::VLD2b8wb_fixed:
2946 case ARM::VLD2b16wb_fixed:
2947 case ARM::VLD2b32wb_fixed:
2948 case ARM::VLD2q8wb_fixed:
2949 case ARM::VLD2q16wb_fixed:
2950 case ARM::VLD2q32wb_fixed:
3021 case ARM::VST1d8wb_fixed:
3022 case ARM::VST1d16wb_fixed:
3023 case ARM::VST1d32wb_fixed:
3024 case ARM::VST1d64wb_fixed:
3025 case ARM::VST1d8wb_register:
3026 case ARM::VST1d16wb_register:
3027 case ARM::VST1d32wb_register:
3028 case ARM::VST1d64wb_register:
3029 case ARM::VST1q8wb_fixed:
3030 case ARM::VST1q16wb_fixed:
3031 case ARM::VST1q32wb_fixed:
3032 case ARM::VST1q64wb_fixed:
3033 case ARM::VST1q8wb_register:
3034 case ARM::VST1q16wb_register:
3035 case ARM::VST1q32wb_register:
3036 case ARM::VST1q64wb_register:
3037 case ARM::VST1d8Twb_fixed:
3038 case ARM::VST1d16Twb_fixed:
3039 case ARM::VST1d32Twb_fixed:
3040 case ARM::VST1d64Twb_fixed:
3041 case ARM::VST1d8Twb_register:
3042 case ARM::VST1d16Twb_register:
3043 case ARM::VST1d32Twb_register:
3044 case ARM::VST1d64Twb_register:
3045 case ARM::VST1d8Qwb_fixed:
3046 case ARM::VST1d16Qwb_fixed:
3047 case ARM::VST1d32Qwb_fixed:
3048 case ARM::VST1d64Qwb_fixed:
3049 case ARM::VST1d8Qwb_register:
3050 case ARM::VST1d16Qwb_register:
3051 case ARM::VST1d32Qwb_register:
3052 case ARM::VST1d64Qwb_register:
3053 case ARM::VST2d8wb_fixed:
3054 case ARM::VST2d16wb_fixed:
3055 case ARM::VST2d32wb_fixed:
3056 case ARM::VST2d8wb_register:
3057 case ARM::VST2d16wb_register:
3058 case ARM::VST2d32wb_register:
3059 case ARM::VST2q8wb_fixed:
3060 case ARM::VST2q16wb_fixed:
3061 case ARM::VST2q32wb_fixed:
3062 case ARM::VST2q8wb_register:
3063 case ARM::VST2q16wb_register:
3064 case ARM::VST2q32wb_register:
3065 case ARM::VST2b8wb_fixed:
3066 case ARM::VST2b16wb_fixed:
3067 case ARM::VST2b32wb_fixed:
3068 case ARM::VST2b8wb_register:
3069 case ARM::VST2b16wb_register:
3070 case ARM::VST2b32wb_register:
3075 case ARM::VST3d8_UPD:
3076 case ARM::VST3d16_UPD:
3077 case ARM::VST3d32_UPD:
3078 case ARM::VST3q8_UPD:
3079 case ARM::VST3q16_UPD:
3080 case ARM::VST3q32_UPD:
3081 case ARM::VST4d8_UPD:
3082 case ARM::VST4d16_UPD:
3083 case ARM::VST4d32_UPD:
3084 case ARM::VST4q8_UPD:
3085 case ARM::VST4q16_UPD:
3086 case ARM::VST4q32_UPD:
3108 case ARM::VST1d8wb_fixed:
3109 case ARM::VST1d16wb_fixed:
3110 case ARM::VST1d32wb_fixed:
3111 case ARM::VST1d64wb_fixed:
3112 case ARM::VST1q8wb_fixed:
3113 case ARM::VST1q16wb_fixed:
3114 case ARM::VST1q32wb_fixed:
3115 case ARM::VST1q64wb_fixed:
3116 case ARM::VST1d8Twb_fixed:
3117 case ARM::VST1d16Twb_fixed:
3118 case ARM::VST1d32Twb_fixed:
3119 case ARM::VST1d64Twb_fixed:
3120 case ARM::VST1d8Qwb_fixed:
3121 case ARM::VST1d16Qwb_fixed:
3122 case ARM::VST1d32Qwb_fixed:
3123 case ARM::VST1d64Qwb_fixed:
3124 case ARM::VST2d8wb_fixed:
3125 case ARM::VST2d16wb_fixed:
3126 case ARM::VST2d32wb_fixed:
3127 case ARM::VST2q8wb_fixed:
3128 case ARM::VST2q16wb_fixed:
3129 case ARM::VST2q32wb_fixed:
3130 case ARM::VST2b8wb_fixed:
3131 case ARM::VST2b16wb_fixed:
3132 case ARM::VST2b32wb_fixed:
3138 case ARM::VST1q16:
3139 case ARM::VST1q32:
3140 case ARM::VST1q64:
3141 case ARM::VST1q8:
3142 case ARM::VST1q16wb_fixed:
3143 case ARM::VST1q16wb_register:
3144 case ARM::VST1q32wb_fixed:
3145 case ARM::VST1q32wb_register:
3146 case ARM::VST1q64wb_fixed:
3147 case ARM::VST1q64wb_register:
3148 case ARM::VST1q8wb_fixed:
3149 case ARM::VST1q8wb_register:
3150 case ARM::VST2d16:
3151 case ARM::VST2d32:
3152 case ARM::VST2d8:
3153 case ARM::VST2d16wb_fixed:
3154 case ARM::VST2d16wb_register:
3155 case ARM::VST2d32wb_fixed:
3156 case ARM::VST2d32wb_register:
3157 case ARM::VST2d8wb_fixed:
3158 case ARM::VST2d8wb_register:
3162 case ARM::VST2b16:
3163 case ARM::VST2b32:
3164 case ARM::VST2b8:
3165 case ARM::VST2b16wb_fixed:
3166 case ARM::VST2b16wb_register:
3167 case ARM::VST2b32wb_fixed:
3168 case ARM::VST2b32wb_register:
3169 case ARM::VST2b8wb_fixed:
3170 case ARM::VST2b8wb_register:
3181 case ARM::VST3d8:
3182 case ARM::VST3d16:
3183 case ARM::VST3d32:
3184 case ARM::VST3d8_UPD:
3185 case ARM::VST3d16_UPD:
3186 case ARM::VST3d32_UPD:
3187 case ARM::VST4d8:
3188 case ARM::VST4d16:
3189 case ARM::VST4d32:
3190 case ARM::VST4d8_UPD:
3191 case ARM::VST4d16_UPD:
3192 case ARM::VST4d32_UPD:
3196 case ARM::VST3q8:
3197 case ARM::VST3q16:
3198 case ARM::VST3q32:
3199 case ARM::VST3q8_UPD:
3200 case ARM::VST3q16_UPD:
3201 case ARM::VST3q32_UPD:
3202 case ARM::VST4q8:
3203 case ARM::VST4q16:
3204 case ARM::VST4q32:
3205 case ARM::VST4q8_UPD:
3206 case ARM::VST4q16_UPD:
3207 case ARM::VST4q32_UPD:
3217 case ARM::VST3d8:
3218 case ARM::VST3d16:
3219 case ARM::VST3d32:
3220 case ARM::VST3d8_UPD:
3221 case ARM::VST3d16_UPD:
3222 case ARM::VST3d32_UPD:
3223 case ARM::VST4d8:
3224 case ARM::VST4d16:
3225 case ARM::VST4d32:
3226 case ARM::VST4d8_UPD:
3227 case ARM::VST4d16_UPD:
3228 case ARM::VST4d32_UPD:
3232 case ARM::VST3q8:
3233 case ARM::VST3q16:
3234 case ARM::VST3q32:
3235 case ARM::VST3q8_UPD:
3236 case ARM::VST3q16_UPD:
3237 case ARM::VST3q32_UPD:
3238 case ARM::VST4q8:
3239 case ARM::VST4q16:
3240 case ARM::VST4q32:
3241 case ARM::VST4q8_UPD:
3242 case ARM::VST4q16_UPD:
3243 case ARM::VST4q32_UPD:
3253 case ARM::VST4d8:
3254 case ARM::VST4d16:
3255 case ARM::VST4d32:
3256 case ARM::VST4d8_UPD:
3257 case ARM::VST4d16_UPD:
3258 case ARM::VST4d32_UPD:
3262 case ARM::VST4q8:
3263 case ARM::VST4q16:
3264 case ARM::VST4q32:
3265 case ARM::VST4q8_UPD:
3266 case ARM::VST4q16_UPD:
3267 case ARM::VST4q32_UPD:
3294 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3295 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3296 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3297 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3338 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3339 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3340 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3341 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3345 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3346 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3347 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3348 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3485 case ARM::VORRiv4i16:
3486 case ARM::VORRiv2i32:
3487 case ARM::VBICiv4i16:
3488 case ARM::VBICiv2i32:
3492 case ARM::VORRiv8i16:
3493 case ARM::VORRiv4i32:
3494 case ARM::VBICiv8i16:
3495 case ARM::VBICiv4i32:
3520 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3543 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3554 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3623 case ARM::VTBL2:
3624 case ARM::VTBX2:
3652 case ARM::tADR:
3654 case ARM::tADDrSPi:
3655 Inst.addOperand(MCOperand::createReg(ARM::SP));
3728 Inst.addOperand(MCOperand::createReg(ARM::SP));
3744 case ARM::t2STRHs:
3745 case ARM::t2STRBs:
3746 case ARM::t2STRs:
3773 bool hasMP = featureBits[ARM::FeatureMP];
3774 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3778 case ARM::t2LDRBs:
3779 Inst.setOpcode(ARM::t2LDRBpci);
3781 case ARM::t2LDRHs:
3782 Inst.setOpcode(ARM::t2LDRHpci);
3784 case ARM::t2LDRSHs:
3785 Inst.setOpcode(ARM::t2LDRSHpci);
3787 case ARM::t2LDRSBs:
3788 Inst.setOpcode(ARM::t2LDRSBpci);
3790 case ARM::t2LDRs:
3791 Inst.setOpcode(ARM::t2LDRpci);
3793 case ARM::t2PLDs:
3794 Inst.setOpcode(ARM::t2PLDpci);
3796 case ARM::t2PLIs:
3797 Inst.setOpcode(ARM::t2PLIpci);
3808 case ARM::t2LDRSHs:
3810 case ARM::t2LDRHs:
3811 Inst.setOpcode(ARM::t2PLDWs);
3813 case ARM::t2LDRSBs:
3814 Inst.setOpcode(ARM::t2PLIs);
3822 case ARM::t2PLDs:
3824 case ARM::t2PLIs:
3828 case ARM::t2PLDWs:
3861 bool hasMP = featureBits[ARM::FeatureMP];
3862 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3866 case ARM::t2LDRi8:
3867 Inst.setOpcode(ARM::t2LDRpci);
3869 case ARM::t2LDRBi8:
3870 Inst.setOpcode(ARM::t2LDRBpci);
3872 case ARM::t2LDRSBi8:
3873 Inst.setOpcode(ARM::t2LDRSBpci);
3875 case ARM::t2LDRHi8:
3876 Inst.setOpcode(ARM::t2LDRHpci);
3878 case ARM::t2LDRSHi8:
3879 Inst.setOpcode(ARM::t2LDRSHpci);
3881 case ARM::t2PLDi8:
3882 Inst.setOpcode(ARM::t2PLDpci);
3884 case ARM::t2PLIi8:
3885 Inst.setOpcode(ARM::t2PLIpci);
3895 case ARM::t2LDRSHi8:
3897 case ARM::t2LDRHi8:
3899 Inst.setOpcode(ARM::t2PLDWi8);
3901 case ARM::t2LDRSBi8:
3902 Inst.setOpcode(ARM::t2PLIi8);
3910 case ARM::t2PLDi8:
3912 case ARM::t2PLIi8:
3916 case ARM::t2PLDWi8:
3942 bool hasMP = featureBits[ARM::FeatureMP];
3943 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3947 case ARM::t2LDRi12:
3948 Inst.setOpcode(ARM::t2LDRpci);
3950 case ARM::t2LDRHi12:
3951 Inst.setOpcode(ARM::t2LDRHpci);
3953 case ARM::t2LDRSHi12:
3954 Inst.setOpcode(ARM::t2LDRSHpci);
3956 case ARM::t2LDRBi12:
3957 Inst.setOpcode(ARM::t2LDRBpci);
3959 case ARM::t2LDRSBi12:
3960 Inst.setOpcode(ARM::t2LDRSBpci);
3962 case ARM::t2PLDi12:
3963 Inst.setOpcode(ARM::t2PLDpci);
3965 case ARM::t2PLIi12:
3966 Inst.setOpcode(ARM::t2PLIpci);
3976 case ARM::t2LDRSHi12:
3978 case ARM::t2LDRHi12:
3979 Inst.setOpcode(ARM::t2PLDWi12);
3981 case ARM::t2LDRSBi12:
3982 Inst.setOpcode(ARM::t2PLIi12);
3990 case ARM::t2PLDi12:
3992 case ARM::t2PLIi12:
3996 case ARM::t2PLDWi12:
4021 case ARM::t2LDRT:
4022 Inst.setOpcode(ARM::t2LDRpci);
4024 case ARM::t2LDRBT:
4025 Inst.setOpcode(ARM::t2LDRBpci);
4027 case ARM::t2LDRHT:
4028 Inst.setOpcode(ARM::t2LDRHpci);
4030 case ARM::t2LDRSBT:
4031 Inst.setOpcode(ARM::t2LDRSBpci);
4033 case ARM::t2LDRSHT:
4034 Inst.setOpcode(ARM::t2LDRSHpci);
4060 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4064 case ARM::t2LDRBpci:
4065 case ARM::t2LDRHpci:
4066 Inst.setOpcode(ARM::t2PLDpci);
4068 case ARM::t2LDRSBpci:
4069 Inst.setOpcode(ARM::t2PLIpci);
4071 case ARM::t2LDRSHpci:
4079 case ARM::t2PLDpci:
4081 case ARM::t2PLIpci:
4213 case ARM::t2STRT:
4214 case ARM::t2STRBT:
4215 case ARM::t2STRHT:
4216 case ARM::t2STRi8:
4217 case ARM::t2STRHi8:
4218 case ARM::t2STRBi8:
4228 case ARM::t2LDRT:
4229 case ARM::t2LDRBT:
4230 case ARM::t2LDRHT:
4231 case ARM::t2LDRSBT:
4232 case ARM::t2LDRSHT:
4233 case ARM::t2STRT:
4234 case ARM::t2STRBT:
4235 case ARM::t2STRHT:
4299 case ARM::t2LDR_PRE:
4300 case ARM::t2LDR_POST:
4301 Inst.setOpcode(ARM::t2LDRpci);
4303 case ARM::t2LDRB_PRE:
4304 case ARM::t2LDRB_POST:
4305 Inst.setOpcode(ARM::t2LDRBpci);
4307 case ARM::t2LDRH_PRE:
4308 case ARM::t2LDRH_POST:
4309 Inst.setOpcode(ARM::t2LDRHpci);
4311 case ARM::t2LDRSB_PRE:
4312 case ARM::t2LDRSB_POST:
4314 Inst.setOpcode(ARM::t2PLIpci);
4316 Inst.setOpcode(ARM::t2LDRSBpci);
4318 case ARM::t2LDRSH_PRE:
4319 case ARM::t2LDRSH_POST:
4320 Inst.setOpcode(ARM::t2LDRSHpci);
4356 case ARM::t2STRi12:
4357 case ARM::t2STRBi12:
4358 case ARM::t2STRHi12:
4377 Inst.addOperand(MCOperand::createReg(ARM::SP));
4378 Inst.addOperand(MCOperand::createReg(ARM::SP));
4388 if (Inst.getOpcode() == ARM::tADDrSP) {
4394 Inst.addOperand(MCOperand::createReg(ARM::SP));
4397 } else if (Inst.getOpcode() == ARM::tADDspr) {
4400 Inst.addOperand(MCOperand::createReg(ARM::SP));
4401 Inst.addOperand(MCOperand::createReg(ARM::SP));
4517 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
4537 Inst.setOpcode(ARM::t2DSB);
4540 Inst.setOpcode(ARM::t2DMB);
4543 Inst.setOpcode(ARM::t2ISB);
4656 if (FeatureBits[ARM::FeatureMClass]) {
4676 if (!(FeatureBits[ARM::HasV7Ops]))
4684 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4694 if (!(FeatureBits[ARM::Feature8MSecExt]))
4703 if (Inst.getOpcode() == ARM::t2MSR_M) {
4705 if (!(FeatureBits[ARM::HasV7Ops])) {
4719 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4738 // ARM ARM. There are patterns, but nothing regular enough to make this logic
5614 Inst.setOpcode(ARM::t2SUBri12);
5615 Inst.addOperand(MCOperand::createReg(ARM::PC));
5665 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5681 Inst.setOpcode(ARM::VMOVv2f32);
5686 Inst.setOpcode(ARM::VMOVv1i64);
5688 Inst.setOpcode(ARM::VMOVv8i8);
5693 Inst.setOpcode(ARM::VMVNv2i32);
5695 Inst.setOpcode(ARM::VMOVv2i32);
5700 Inst.setOpcode(ARM::VMVNv2i32);
5702 Inst.setOpcode(ARM::VMOVv2i32);
5724 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5740 Inst.setOpcode(ARM::VMOVv4f32);
5745 Inst.setOpcode(ARM::VMOVv2i64);
5747 Inst.setOpcode(ARM::VMOVv16i8);
5752 Inst.setOpcode(ARM::VMVNv4i32);
5754 Inst.setOpcode(ARM::VMOVv4i32);
5759 Inst.setOpcode(ARM::VMVNv4i32);
5761 Inst.setOpcode(ARM::VMOVv4i32);
5865 if (Inst.getOpcode() == ARM::MRRC2) {
5873 if (Inst.getOpcode() == ARM::MCRR2) {
5894 case ARM::VMSR_FPSCR_NZCVQC:
5895 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5897 case ARM::VMSR_P0:
5898 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5902 if (Inst.getOpcode() != ARM::FMSTAT) {
5905 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5915 case ARM::VMRS_FPSCR_NZCVQC:
5916 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5918 case ARM::VMRS_P0:
5919 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5923 if (featureBits[ARM::ModeThumb]) {
5980 if (Inst.getOpcode() == ARM::MVE_LCTP)
5986 case ARM::t2LEUpdate:
5987 case ARM::MVE_LETP:
5988 Inst.addOperand(MCOperand::createReg(ARM::LR));
5989 Inst.addOperand(MCOperand::createReg(ARM::LR));
5991 case ARM::t2LE:
5996 case ARM::t2WLS:
5997 case ARM::MVE_WLSTP_8:
5998 case ARM::MVE_WLSTP_16:
5999 case ARM::MVE_WLSTP_32:
6000 case ARM::MVE_WLSTP_64:
6001 Inst.addOperand(MCOperand::createReg(ARM::LR));
6009 case ARM::t2DLS:
6010 case ARM::MVE_DLSTP_8:
6011 case ARM::MVE_DLSTP_16:
6012 case ARM::MVE_DLSTP_32:
6013 case ARM::MVE_DLSTP_64:
6025 Inst.setOpcode(ARM::MVE_LCTP);
6027 Inst.addOperand(MCOperand::createReg(ARM::LR));
6077 if (Inst.getOpcode() == ARM::VSCCLRMD) {
6092 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6109 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6110 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6125 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6126 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6260 case ARM::MVE_VCVTf16s16_fix:
6261 case ARM::MVE_VCVTs16f16_fix:
6262 case ARM::MVE_VCVTf16u16_fix:
6263 case ARM::MVE_VCVTu16f16_fix:
6267 case ARM::MVE_VCVTf32s32_fix:
6268 case ARM::MVE_VCVTs32f32_fix:
6269 case ARM::MVE_VCVTf32u32_fix:
6270 case ARM::MVE_VCVTu32f32_fix:
6283 case ARM::VSTR_P0_off:
6284 case ARM::VSTR_P0_pre:
6285 case ARM::VSTR_P0_post:
6286 case ARM::VLDR_P0_off:
6287 case ARM::VLDR_P0_pre:
6288 case ARM::VLDR_P0_post:
6289 return ARM::P0;
6300 case ARM::VSTR_FPSCR_pre:
6301 case ARM::VSTR_FPSCR_NZCVQC_pre:
6302 case ARM::VLDR_FPSCR_pre:
6303 case ARM::VLDR_FPSCR_NZCVQC_pre:
6304 case ARM::VSTR_FPSCR_off:
6305 case ARM::VSTR_FPSCR_NZCVQC_off:
6306 case ARM::VLDR_FPSCR_off:
6307 case ARM::VLDR_FPSCR_NZCVQC_off:
6308 case ARM::VSTR_FPSCR_post:
6309 case ARM::VSTR_FPSCR_NZCVQC_post:
6310 case ARM::VLDR_FPSCR_post:
6311 case ARM::VLDR_FPSCR_NZCVQC_post:
6315 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6484 case ARM::MVE_ASRLr:
6485 case ARM::MVE_SQRSHRL:
6486 Inst.setOpcode(ARM::MVE_SQRSHR);
6488 case ARM::MVE_LSLLr:
6489 case ARM::MVE_UQRSHLL:
6490 Inst.setOpcode(ARM::MVE_UQRSHL);
6536 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6537 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6569 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6606 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6616 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6617 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6642 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
6646 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);