Searched refs:wptr (Results 76 - 100 of 137) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
389 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
390 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
559 WARN_ON(ring->wptr % 2 || count % 2);
H A Damdgpu_amdkfd_gfx_v8.c156 uint32_t __user *wptr, uint32_t wptr_shift,
215 valid_wptr = read_user_wptr(mm, wptr, wptr_val);
264 uint32_t __user *wptr, struct mm_struct *mm)
294 if (read_user_wptr(mm, wptr, data))
154 kgd_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
263 kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
H A Djpeg_v2_5.c366 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
446 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
447 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
449 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
H A Damdgpu_amdkfd_arcturus.c125 uint32_t __user *wptr, struct mm_struct *mm)
132 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
124 kgd_arcturus_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
H A Damdgpu_amdkfd_gfx_v10.c210 uint32_t __user *wptr, uint32_t wptr_shift,
236 if (wptr) {
237 /* Don't read wptr with get_user because the user
241 * that wptr is GPU-accessible in the queue's VMID via
268 lower_32_bits((uint64_t)wptr));
270 upper_32_bits((uint64_t)wptr));
374 uint32_t __user *wptr, struct mm_struct *mm)
381 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
208 kgd_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
373 kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
H A Damdgpu_amdkfd_gfx_v11.c165 uint32_t queue_id, uint32_t __user *wptr,
207 if (wptr) {
208 /* Don't read wptr with get_user because the user
212 * that wptr is GPU-accessible in the queue's VMID via
239 lower_32_bits((uint64_t)wptr));
241 upper_32_bits((uint64_t)wptr));
345 uint32_t __user *wptr, struct mm_struct *mm)
352 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
164 hqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
344 hqd_sdma_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
H A Damdgpu_amdkfd_gfx_v9.c224 uint32_t __user *wptr, uint32_t wptr_shift,
250 if (wptr) {
251 /* Don't read wptr with get_user because the user
255 * that wptr is GPU-accessible in the queue's VMID via
282 lower_32_bits((uintptr_t)wptr));
284 upper_32_bits((uintptr_t)wptr));
385 uint32_t __user *wptr, struct mm_struct *mm)
392 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
222 kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
384 kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
H A Dsdma_v2_4.c197 * Get the current wptr from the hardware (VI+).
202 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; local
204 return wptr;
212 * Write the wptr back to the hardware (VI+).
218 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
252 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
451 ring->wptr = 0;
452 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
H A Dmes_v10_1.c55 ring->wptr);
56 WDOORBELL64(ring->doorbell_index, ring->wptr);
69 u64 wptr; local
72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
75 return wptr;
657 ring->wptr = 0;
H A Djpeg_v4_0_3.c309 ring->wptr = 0;
542 ring->wptr = RREG32_SOC15_OFFSET(
637 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
638 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
644 lower_32_bits(ring->wptr));
882 WARN_ON(ring->wptr % 2 || count % 2);
H A Dmes_v11_0.c69 ring->wptr);
70 WDOORBELL64(ring->doorbell_index, ring->wptr);
83 u64 wptr; local
86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
89 return wptr;
701 ring->wptr = 0;
H A Damdgpu_vcn.h337 uint32_t wptr; member in struct:amdgpu_fw_shared_rb_ptrs_struct
435 uint32_t wptr; member in struct:amdgpu_vcn_fwlog
H A Dcik_sdma.c173 * Get the current wptr from the hardware (CIK+).
187 * Write the wptr back to the hardware (CIK+).
194 (ring->wptr << 2) & 0x3fffc);
229 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
477 ring->wptr = 0;
478 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
H A Dsi_dma.c59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
71 while ((lower_32_bits(ring->wptr) & 7) != 5)
171 ring->wptr = 0;
172 WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
H A Dvcn_v4_0_3.c217 ring->wptr = 0;
835 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
957 ring_enc->wptr = 0;
1203 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1398 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1399 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1402 lower_32_bits(ring->wptr));
/linux-master/drivers/scsi/lpfc/
H A Dlpfc_nvme.c832 uint32_t *wptr, *dptr; local
871 wptr = &wqe->words[16]; /* WQE ptr */
875 *wptr++ = *dptr++; /* Word 1 */
876 *wptr++ = *dptr++; /* Word 2 */
877 *wptr++ = *dptr++; /* Word 3 */
878 *wptr++ = *dptr++; /* Word 4 */
880 *wptr++ = *dptr++; /* Word 6 */
881 *wptr++ = *dptr++; /* Word 7 */
883 *wptr++ = *dptr++; /* Word 16 */
884 *wptr
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/linux-master/drivers/media/platform/amphion/
H A Dvpu_windsor.c582 iface->cmd_buffer_desc.wptr = phy_addr;
590 iface->msg_buffer_desc.wptr =
639 iface->log_buffer_desc.wptr =
734 info->wptr = get_ptr(windsor->str_buff_wptr);
862 desc->wptr = buf->phys;
882 /*update wptr/rptr after data is written or read*/
885 desc->wptr = ptr;
899 desc->wptr = get_ptr(rpc_desc->wptr);
/linux-master/drivers/scsi/
H A Dqla1280.c572 uint16_t *wptr; local
584 wptr = (uint16_t *)&ha->nvram;
588 *wptr = qla1280_get_nvram_word(ha, cnt);
589 chksum += *wptr & 0xff;
590 chksum += (*wptr >> 8) & 0xff;
591 wptr++;
600 *wptr = qla1280_get_nvram_word(ha, cnt);
601 chksum += *wptr & 0xff;
602 chksum += (*wptr >> 8) & 0xff;
603 wptr
3341 uint16_t *wptr; local
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/linux-master/drivers/gpu/drm/radeon/
H A Dcik_sdma.c87 * Get the current wptr from the hardware (CIK+).
108 * Write the wptr back to the hardware (CIK+).
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
139 u32 next_rptr = ring->wptr + 5;
151 while ((ring->wptr & 7) != 4)
410 ring->wptr = 0;
411 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
H A Dni.c1411 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1470 u32 wptr; local
1473 wptr = RREG32(CP_RB0_WPTR);
1475 wptr = RREG32(CP_RB1_WPTR);
1477 wptr = RREG32(CP_RB2_WPTR);
1479 return wptr;
1486 WREG32(CP_RB0_WPTR, ring->wptr);
1489 WREG32(CP_RB1_WPTR, ring->wptr);
1492 WREG32(CP_RB2_WPTR, ring->wptr);
1692 ring->wptr
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
H A Dr535.c101 u32 wptr = *gsp->msgq.wptr; local
103 used = wptr + gsp->msgq.cnt - rptr;
164 u32 wptr, size; local
180 wptr = *gsp->cmdq.wptr;
183 free = *gsp->cmdq.rptr + gsp->cmdq.cnt - wptr - 1;
197 cqe = (void *)((u8 *)gsp->shm.cmdq.ptr + 0x1000 + wptr * 0x1000);
198 size = min_t(u32, argc, (gsp->cmdq.cnt - wptr) * GSP_PAGE_SIZE);
201 wptr
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/linux-master/drivers/tty/
H A Dmoxa.c570 u16 rptr, wptr, mask, len; local
574 wptr = readw(ofsAddr + RXwptr);
576 len = (wptr - rptr) & mask;
2289 u16 rptr, wptr, mask; local
2292 wptr = readw(ofsAddr + TXwptr);
2294 return (wptr - rptr) & mask;
2300 u16 rptr, wptr, mask; local
2303 wptr = readw(ofsAddr + TXwptr);
2305 return mask - ((wptr - rptr) & mask);
2311 u16 rptr, wptr, mas local
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/linux-master/drivers/net/ethernet/tehuti/
H A Dtehuti.h145 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, member in struct:fifo
201 struct tx_map *wptr; /* points to the next element to write */ member in struct:txdb
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dgsp.h128 u32 *wptr; member in struct:nvkm_gsp::nvkm_gsp_cmdq
135 u32 *wptr; member in struct:nvkm_gsp::nvkm_gsp_msgq
/linux-master/fs/smb/server/
H A Dvfs.h42 char *wptr; member in struct:ksmbd_dir_info

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