Searched refs:timing (Results 76 - 100 of 317) sorted by relevance

1234567891011>>

/linux-master/sound/pci/
H A Dsis7019.c49 /* There are three timing modes for the voices.
82 struct voice *timing; member in struct:voice
121 * buffer for a timing channel.
327 if (!voice->timing)
389 if (voice->timing) {
391 voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING |
393 voice->timing = NULL;
441 * timing voice, as we can use the capture channel's interrupts
449 if (needed && !voice->timing) {
451 voice->timing
698 struct voice *timing = voice->timing; local
[all...]
/linux-master/drivers/nvmem/
H A Dimx-ocotp.c241 u32 timing; local
245 * fields with timing values to match the current frequency of the
261 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
262 * timing is not entirely clear the documentation says "This
263 * count value specifies the time to add to all default timing
266 * and STROBE_READ respectively. What the other timing parameters
281 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
282 timing |= strobe_prog & 0x00000FFF;
283 timing |= (relax << 12) & 0x0000F000;
284 timing |
293 u32 timing; local
[all...]
/linux-master/drivers/memory/tegra/
H A Dtegra20-emc.c259 struct emc_timing *timing = NULL; local
264 timing = &emc->timings[i];
269 if (!timing) {
270 dev_err(emc->dev, "no timing for rate %lu\n", rate);
274 return timing;
279 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); local
282 if (!timing)
285 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
286 __func__, timing->rate, rate);
289 for (i = 0; i < ARRAY_SIZE(timing
355 load_one_timing_from_dt(struct tegra_emc *emc, struct emc_timing *timing, struct device_node *node) argument
414 struct emc_timing *timing; local
680 struct emc_timing *timing = NULL; local
[all...]
H A Dtegra210-emc-core.c916 dev_warn(emc->dev, "timing update error: %d\n", err);
1225 const struct tegra210_emc_timing *timing; local
1228 timing = emc->last;
1230 timing = emc->next;
1232 cmd_pad = timing->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX];
1233 dq_pad = timing->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
1234 rfu1 = timing->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX];
1235 cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX];
1236 common_tx = timing->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX];
1443 void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing) argument
1492 tegra210_emc_adjust_timing(struct tegra210_emc *emc, struct tegra210_emc_timing *timing) argument
1532 struct tegra210_emc_timing *timing = NULL; local
1933 struct tegra210_emc_timing *timing = &emc->timings[i]; local
[all...]
/linux-master/drivers/mmc/host/
H A Dsdhci-xenon.c199 unsigned int timing)
206 if (timing == MMC_TIMING_MMC_HS200)
208 else if (timing == MMC_TIMING_UHS_SDR104)
210 else if (timing == MMC_TIMING_UHS_SDR12)
212 else if (timing == MMC_TIMING_UHS_SDR25)
214 else if (timing == MMC_TIMING_UHS_SDR50)
216 else if ((timing == MMC_TIMING_UHS_DDR50) ||
217 (timing == MMC_TIMING_MMC_DDR52))
219 else if (timing == MMC_TIMING_MMC_HS400)
292 if ((ios->timing
198 xenon_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) argument
[all...]
H A Ddw_mmc-k3.c216 static void dw_mci_hs_set_timing(struct dw_mci *host, int timing, argument
230 drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
231 smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
233 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
234 hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
236 switch (timing) {
263 /* We should delay 1ms wait for timing setting finished. */
315 dw_mci_hs_set_timing(host, ios->timing, -1);
380 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
394 dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmp
[all...]
H A Ddw_mmc-hi3798mv200.c39 struct mmc_clk_phase phase = priv->phase_map.phase[ios->timing];
43 if (ios->timing == MMC_TIMING_MMC_DDR52
44 || ios->timing == MMC_TIMING_UHS_DDR50)
51 if (ios->timing == MMC_TIMING_MMC_HS400)
72 "The phase entry for timing mode %d is missing in device tree.\n",
73 ios->timing);
160 * We don't care what timing we are tuning for,
161 * simply use the same phase for all timing needs tuning.
H A Ddw_mmc-starfive.c31 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
52 /* We should delay 1ms wait for timing setting finished. */
/linux-master/drivers/iio/light/
H A Dtcs3414.c55 u8 timing; member in struct:tcs3414_data
158 *val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000;
189 data->timing &= ~TCS3414_INTEG_MASK;
190 data->timing |= i;
193 data->timing);
328 data->timing = TCS3414_INTEG_12MS; /* free running */
330 data->timing);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c268 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument
270 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
272 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
273 && !timing->dsc_cfg.ycbcr422_simple);
303 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
312 m_vid_l *= param->timing.pix_clk_100hz / 10;
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c907 struct msm_dsi_dphy_timing *timing,
912 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
913 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
914 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
915 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
916 u32 prep_dly = clk_ln ? timing
906 dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing, int lane_idx) argument
946 struct msm_dsi_dphy_timing *timing = &phy->timing; local
[all...]
H A Ddsi_phy_28nm.c699 struct msm_dsi_dphy_timing *timing)
704 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
706 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
708 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
709 if (timing->clk_zero & BIT(8))
713 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
715 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
717 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
719 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
721 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing
698 dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) argument
781 struct msm_dsi_dphy_timing *timing = &phy->timing; local
[all...]
/linux-master/drivers/media/platform/ti/omap3isp/
H A Dispcsi2.c351 * csi2_timing_config - CSI2 timing configuration.
352 * @timing: csi2_timing_cfg structure
356 struct isp_csi2_timing_cfg *timing)
362 if (timing->force_rx_mode)
363 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
365 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
367 if (timing->stop_state_16x)
368 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
370 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
372 if (timing
354 csi2_timing_config(struct isp_device *isp, struct isp_csi2_device *csi2, struct isp_csi2_timing_cfg *timing) argument
551 struct isp_csi2_timing_cfg *timing = &csi2->timing[0]; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_dio.c85 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
90 &stream->timing,
97 &stream->timing,
103 &stream->timing,
109 &stream->timing);
/linux-master/drivers/ata/
H A Dpata_imx.c58 struct ata_timing timing; local
69 ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
75 writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
76 writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
77 writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
H A Dpata_legacy.c144 unsigned long timing; member in struct:legacy_data
392 /* Get the timing data in cycles. For now play safe at 50Mhz */
426 /* Get the timing data in cycles. For now play safe at 50Mhz */
502 /* Get the timing data in cycles */
505 /* Setup timing is shared */
517 /* Select the right timing bank for write timing */
537 /* Ensure the timing register mode is right */
581 /* Get the timing data in cycles */
584 /* Setup timing i
682 u8 timing; local
821 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h158 * struct timing_generator_funcs - Control timing generator on a given device.
162 const struct dc_crtc_timing *timing);
164 const struct dc_crtc_timing *timing,
235 bool enable, const struct dc_crtc_timing *timing);
256 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
275 * Configure CRCs for the given timing generator. Return false if TG is
282 * @get_crc: Get CRCs for the given timing generator. Return false if
309 struct dc_crtc_timing *timing);
H A Doptc.h36 * - OTG: It is Output Timing Generator. It generates display timing signals to
103 const struct dc_crtc_timing *timing);
181 const struct dc_crtc_timing *timing,
213 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
/linux-master/drivers/gpu/drm/sti/
H A Dsti_dvo.c58 struct awg_timing *timing);
117 struct awg_timing timing; local
122 timing.total_lines = mode->vtotal;
123 timing.active_lines = mode->vdisplay;
124 timing.blanking_lines = mode->vsync_start - mode->vdisplay;
125 timing.trailing_lines = mode->vtotal - mode->vsync_start;
126 timing.total_pixels = mode->htotal;
127 timing.active_pixels = mode->hdisplay;
128 timing.blanking_pixels = mode->hsync_start - mode->hdisplay;
129 timing
[all...]
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_psr.c161 stream->timing.pix_clk_100hz * 100),
162 stream->timing.v_total),
163 stream->timing.h_total);
H A Damdgpu_dm_mst_types.c782 struct dc_crtc_timing *timing; member in struct:dsc_mst_fairness_params
831 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
837 params[i].timing,
839 &params[i].timing->dsc_cfg)) {
840 params[i].timing->flags.DSC = 1;
843 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
848 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
851 params[i].timing
[all...]
/linux-master/drivers/media/rc/img-ir/
H A Dimg-ir-hw.c77 static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, argument
80 img_ir_timing_preprocess(&timing->pulse, unit);
81 img_ir_timing_preprocess(&timing->space, unit);
109 static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, argument
112 img_ir_timing_defaults(&timing->pulse, &defaults->pulse);
113 img_ir_timing_defaults(&timing->space, &defaults->space);
164 * @out: Output timing range in clock cycles with a shift.
165 * @in: Input timing range in microseconds.
194 * img_ir_symbol_timing() - Convert symbol timing struct to register value.
195 * @timing
203 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, unsigned int tolerance, unsigned long clock_hz, unsigned int pd_shift, unsigned int w_shift) argument
231 img_ir_free_timing(const struct img_ir_free_timing *timing, unsigned long clock_hz) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c591 out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
592 out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
593 out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
594 out->VFrontPorch[location] = in->timing
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c422 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
423 + pipe->stream->timing.v_border_bottom;
431 input->dest.htotal = pipe->stream->timing.h_total;
432 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
434 - pipe->stream->timing.h_addressable
435 - pipe->stream->timing.h_border_left
436 - pipe->stream->timing.h_border_right;
438 input->dest.vtotal = pipe->stream->timing.v_total;
439 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing
[all...]
/linux-master/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dtdls.h23 * struct iwl_tdls_channel_switch_timing - Switch timing in TDLS channel-switch
30 * @switch_time: switch time the peer sent in its channel switch timing IE
31 * @switch_timeout: switch timeout the peer sent in its channel switch timing IE
47 * @switch_time_offset: offset to the channel switch timing IE in the template
60 * @timing: timing related data for command
64 struct iwl_tdls_channel_switch_timing timing; member in struct:iwl_tdls_channel_switch_cmd_tail

Completed in 211 milliseconds

1234567891011>>