/linux-master/drivers/net/wireless/mediatek/mt76/ |
H A D | mt76.h | 905 struct mt76_mmio mmio; member in union:mt76_dev::__anon1199
|
H A D | mac80211.c | 1399 if (mtk_wed_device_active(&dev->mmio.wed))
|
H A D | dma.c | 692 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 730 if (mtk_wed_device_active(&dev->mmio.wed)) { 731 if ((mtk_wed_get_rx_capa(&dev->mmio.wed) && mt76_queue_is_wed_rro(q)) || 794 if (mtk_wed_device_active(&dev->mmio.wed) && 950 init_completion(&dev->mmio.wed_reset); 951 init_completion(&dev->mmio.wed_reset_complete); 1004 if (mtk_wed_device_active(&dev->mmio.wed) && 1014 if (mtk_wed_device_active(&dev->mmio.wed)) 1015 mtk_wed_device_detach(&dev->mmio.wed); 1017 if (mtk_wed_device_active(&dev->mmio [all...] |
/linux-master/drivers/net/fddi/ |
H A D | defxx.c | 258 #define dfx_use_mmio bp->mmio 495 static void dfx_register_res_err(const char *print_name, bool mmio, argument 499 print_name, mmio ? "MMIO" : "I/O", len, start); 572 bp->mmio = true; 577 bp->mmio = false; 585 bp->mmio = false;
|
/linux-master/drivers/net/ethernet/marvell/octeon_ep_vf/ |
H A D | octep_vf_main.c | 970 oct->mmio.hw_addr = ioremap(pci_resource_start(oct->pdev, 0), 972 if (!oct->mmio.hw_addr) { 979 oct->mmio.mapped = 1; 1011 iounmap(oct->mmio.hw_addr); 1028 if (oct->mmio.mapped) 1029 iounmap(oct->mmio.hw_addr);
|
/linux-master/drivers/net/ethernet/marvell/octeon_ep/ |
H A D | octep_main.c | 1260 oct->mmio[i].hw_addr = 1263 if (!oct->mmio[i].hw_addr) 1266 oct->mmio[i].mapped = 1; 1317 iounmap(oct->mmio[i].hw_addr); 1351 if (oct->mmio[i].mapped) 1352 iounmap(oct->mmio[i].hw_addr);
|
/linux-master/drivers/net/ethernet/amd/ |
H A D | amd8111e.h | 750 void __iomem *mmio; member in struct:amd8111e_priv
|
H A D | amd8111e.c | 101 void __iomem *mmio = lp->mmio; local 105 reg_val = readl(mmio + PHY_ACCESS); 107 reg_val = readl(mmio + PHY_ACCESS); 110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS); 112 reg_val = readl(mmio + PHY_ACCESS); 131 void __iomem *mmio = lp->mmio; local 134 reg_val = readl(mmio + PHY_ACCESS); 136 reg_val = readl(mmio 368 void __iomem *mmio = lp->mmio; local 424 void __iomem *mmio = lp->mmio; local 502 void __iomem *mmio = lp->mmio; local 686 void __iomem *mmio = lp->mmio; local 835 amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) argument 858 void __iomem *mmio = lp->mmio; local 1082 void __iomem *mmio = lp->mmio; local 1296 void __iomem *mmio = lp->mmio; local 1646 void __iomem *mmio = lp->mmio; local [all...] |
/linux-master/drivers/mmc/host/ |
H A D | sdhci-pci-core.c | 962 cq_host->mmio = host->ioaddr + 0x200;
|
/linux-master/drivers/hid/amd-sfh-hid/sfh1_1/ |
H A D | amd_sfh_init.c | 175 writel(0, privdata->mmio + amd_get_p2c_val(privdata, 0)); 311 u32 phy_base = readl(mp2->mmio + amd_get_c2p_val(mp2, 22)); 318 dev_dbg(dev, "can't reserve mmio registers\n");
|
H A D | amd_sfh_interface.c | 23 if (!readl_poll_timeout(mp2->mmio + amd_get_p2c_val(mp2, 0), cmd_resp.resp, 42 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); 55 writeq(0x0, privdata->mmio + amd_get_c2p_val(privdata, 1)); 56 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); 69 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0)); 100 hpdstatus.val = readl(emp2->mmio + amd_get_c2p_val(emp2, 4));
|
/linux-master/drivers/hid/amd-sfh-hid/ |
H A D | amd_sfh_pcie.c | 46 if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp, 69 writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1); 70 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); 84 writeq(0x0, privdata->mmio + AMD_C2P_MSG1); 85 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); 97 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); 102 if (readl(privdata->mmio + amd_get_p2c_val(privdata, 4))) { 103 writel(0, privdata->mmio + amd_get_p2c_val(privdata, 4)); 104 writel(0xf, privdata->mmio + amd_get_p2c_val(privdata, 5)); 140 return (readl(privdata->mmio [all...] |
/linux-master/drivers/gpio/ |
H A D | Makefile | 20 gpio-generic-$(CONFIG_GPIO_GENERIC) += gpio-mmio.o 26 obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o
|
/linux-master/drivers/bcma/ |
H A D | host_soc.c | 175 bus->mmio = ioremap(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1); 176 if (!bus->mmio) 197 iounmap(bus->mmio); 218 bus->mmio = of_iomap(np, 0); 219 if (!bus->mmio) 239 iounmap(bus->mmio); 248 iounmap(bus->mmio);
|
/linux-master/drivers/ata/ |
H A D | sata_nv.c | 601 void __iomem *mmio = pp->ctl_block; local 608 status = readw(mmio + NV_ADMA_STAT); 611 status = readw(mmio + NV_ADMA_STAT); 618 tmp = readw(mmio + NV_ADMA_CTL); 619 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); 622 status = readw(mmio + NV_ADMA_STAT); 625 status = readw(mmio + NV_ADMA_STAT); 639 void __iomem *mmio = pp->ctl_block; local 648 tmp = readw(mmio + NV_ADMA_CTL); 649 writew(tmp | NV_ADMA_CTL_GO, mmio 890 void __iomem *mmio = pp->ctl_block; local 1018 void __iomem *mmio = pp->ctl_block; local 1040 void __iomem *mmio = pp->ctl_block; local 1058 void __iomem *mmio = pp->ctl_block; local 1103 void __iomem *mmio; local 1193 void __iomem *mmio = pp->ctl_block; local 1202 void __iomem *mmio = pp->ctl_block; local 1219 void __iomem *mmio = pp->ctl_block; local 1253 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local 1397 void __iomem *mmio = pp->ctl_block; local 1632 void __iomem *mmio = pp->ctl_block; local 1812 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local 1831 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local 1851 void __iomem *mmio = host->iomap[NV_MMIO_BAR]; local 1924 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local [all...] |
H A D | sata_mv.c | 577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 581 void __iomem *mmio); 582 int (*reset_hc)(struct ata_host *host, void __iomem *mmio, 584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 585 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 608 void __iomem *mmio); 609 static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio, 881 mv5_phy_base(void __iomem *mmio, unsigned int port) argument 1064 void __iomem *mmio = hpriv->base, *hc_mmio; local 2852 void __iomem *mmio = hpriv->base, *hc_mmio; local 2914 mv_pci_error(struct ata_host *host, void __iomem *mmio) argument 3024 void __iomem *mmio = hpriv->base; local 3038 void __iomem *mmio = hpriv->base; local 3049 mv5_reset_bus(struct ata_host *host, void __iomem *mmio) argument 3065 mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3070 mv5_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument 3082 mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3095 mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument 3124 mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument 3148 mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int hc) argument 3166 mv5_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument 3185 mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) argument 3207 mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3228 mv6_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument 3283 mv6_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument 3303 mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3308 mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument 3386 mv_soc_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3392 mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument 3407 mv_soc_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument 3432 mv_soc_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3445 mv_soc_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument 3459 mv_soc_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument 3465 mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) argument 3470 mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument 3527 mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port_no) argument 3593 void __iomem *mmio = hpriv->base; local 3695 void __iomem *mmio = hpriv->base; local 3709 void __iomem *mmio = hpriv->base; local 3723 void __iomem *mmio = hpriv->base; local 3890 void __iomem *mmio = hpriv->base; local [all...] |
H A D | libata-sff.c | 133 * If we have an mmio device with no ctl and no altstatus 150 * If we have an mmio device with no ctl and no altstatus 265 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 2861 void __iomem *mmio = ap->ioaddr.bmdma_addr; local 2863 if (!mmio) 2866 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); 2916 * flush the mmio write. However, control also passes 2919 * we don't care when the mmio write flushes. 2946 void __iomem *mmio local [all...] |
H A D | ahci.h | 333 void __iomem * mmio; /* bus-independent mem map */ member in struct:ahci_host_priv 439 void __iomem *mmio = hpriv->mmio; local 441 return mmio + 0x100 + (port_no * 0x80);
|
/linux-master/arch/x86/kernel/ |
H A D | sev.c | 1532 enum insn_mmio_type mmio; local 1538 mmio = insn_decode_mmio(insn, &bytes); 1539 if (mmio == INSN_MMIO_DECODE_FAILED) 1542 if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) { 1551 switch (mmio) {
|
/linux-master/drivers/bus/ |
H A D | stm32_firewall.h | 31 * @mmio: Base address of the firewall controller 44 void __iomem *mmio; member in struct:stm32_firewall_controller
|
H A D | stm32_rifsc.c | 81 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; 96 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; 126 sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 127 cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); 191 void __iomem *mmio; local 198 mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 199 if (IS_ERR(mmio)) 200 return PTR_ERR(mmio); 203 rifsc_controller->mmio = mmio; [all...] |
H A D | stm32_etzpc.c | 58 sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK; 79 void __iomem *mmio; local 86 mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 87 if (IS_ERR(mmio)) 88 return PTR_ERR(mmio); 91 etzpc_controller->mmio = mmio; 99 readl(etzpc_controller->mmio + ETZPC_HWCFGR)); 101 readl(etzpc_controller->mmio + ETZPC_HWCFGR));
|
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_amdkfd_gpuvm.c | 647 bool mmio; local 651 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); 653 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio); 660 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length); 661 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr); 667 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr); 1939 /* If the SG is not NULL, it's one we created for a doorbell or mmio
|
/linux-master/drivers/soundwire/ |
H A D | amd_manager.c | 34 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 35 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 41 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 42 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 47 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 48 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 56 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 57 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 66 return readl_poll_timeout(amd_manager->mmio [all...] |
/linux-master/drivers/phy/rockchip/ |
H A D | phy-rockchip-naneng-combphy.c | 137 void __iomem *mmio; member in struct:rockchip_combphy_priv 156 temp = readl(priv->mmio + reg); 158 writel(temp, priv->mmio + reg); 338 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 339 if (IS_ERR(priv->mmio)) { 340 ret = PTR_ERR(priv->mmio); 407 val = readl(priv->mmio + PHYREG15); 409 writel(val, priv->mmio + PHYREG15); 417 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); 424 writel(PHYREG18_PLL_LOOP, priv->mmio [all...] |