Lines Matching refs:mmio
101 void __iomem *mmio = lp->mmio;
105 reg_val = readl(mmio + PHY_ACCESS);
107 reg_val = readl(mmio + PHY_ACCESS);
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS);
112 reg_val = readl(mmio + PHY_ACCESS);
131 void __iomem *mmio = lp->mmio;
134 reg_val = readl(mmio + PHY_ACCESS);
136 reg_val = readl(mmio + PHY_ACCESS);
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
142 reg_val = readl(mmio + PHY_ACCESS);
368 void __iomem *mmio = lp->mmio;
382 writel(VAL0|STINTEN, mmio+INTEN0);
384 timeout, mmio + DLY_INT_A);
396 writel(VAL0 | STINTEN, mmio + INTEN0);
398 timeout, mmio + DLY_INT_B);
402 writel(0, mmio + STVAL);
403 writel(STINTEN, mmio + INTEN0);
404 writel(0, mmio + DLY_INT_B);
405 writel(0, mmio + DLY_INT_A);
409 writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); /* 0.5 sec */
410 writel(VAL0 | STINTEN, mmio + INTEN0);
424 void __iomem *mmio = lp->mmio;
428 writel(RUN, mmio + CMD0);
434 writel((u32)VAL1 | EN_PMGR, mmio + CMD3);
435 writel((u32)XPHYANE | XPHYRST, mmio + CTRL2);
440 reg_val = readl(mmio + CTRL1);
442 writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
447 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
449 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
452 writel((u32)lp->tx_ring_dma_addr, mmio + XMT_RING_BASE_ADDR0);
453 writel((u32)lp->rx_ring_dma_addr, mmio + RCV_RING_BASE_ADDR0);
455 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
456 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
459 writew((u32)DEFAULT_IPG, mmio + IPG);
460 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
463 writel((u32)VAL2|JUMBO, mmio + CMD3);
465 writel(REX_UFLO, mmio + CMD2);
467 writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
469 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
470 writel((u32)JUMBO, mmio + CMD3);
474 writel((u32)VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
476 writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
480 writeb(dev->dev_addr[i], mmio + PADR + i);
489 writel(VAL2 | RDMD0, mmio + CMD0);
490 writel(VAL0 | INTREN | RUN, mmio + CMD0);
493 readl(mmio+CMD0);
502 void __iomem *mmio = lp->mmio;
506 writel(RUN, mmio + CMD0);
509 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
512 writel(0, mmio + RCV_RING_BASE_ADDR0);
515 writel(0, mmio + XMT_RING_BASE_ADDR0);
516 writel(0, mmio + XMT_RING_BASE_ADDR1);
517 writel(0, mmio + XMT_RING_BASE_ADDR2);
518 writel(0, mmio + XMT_RING_BASE_ADDR3);
521 writel(CMD0_CLEAR, mmio + CMD0);
524 writel(CMD2_CLEAR, mmio + CMD2);
527 writel(CMD7_CLEAR, mmio + CMD7);
530 writel(0x0, mmio + DLY_INT_A);
531 writel(0x0, mmio + DLY_INT_B);
534 writel(0x0, mmio + FLOW_CONTROL);
537 reg_val = readl(mmio + INT0);
538 writel(reg_val, mmio + INT0);
541 writel(0x0, mmio + STVAL);
544 writel(INTEN0_CLEAR, mmio + INTEN0);
547 writel(0x0, mmio + LADRF);
550 writel(0x80010, mmio + SRAM_SIZE);
553 writel(0x0, mmio + RCV_RING_LEN0);
556 writel(0x0, mmio + XMT_RING_LEN0);
557 writel(0x0, mmio + XMT_RING_LEN1);
558 writel(0x0, mmio + XMT_RING_LEN2);
559 writel(0x0, mmio + XMT_RING_LEN3);
562 writel(0x0, mmio + XMT_RING_LIMIT);
565 writew(MIB_CLEAR, mmio + MIB_ADDR);
568 amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
571 reg_val = readl(mmio + SRAM_SIZE);
574 writel(VAL2 | JUMBO, mmio + CMD3);
576 writel(VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
579 writel(CTRL1_DEFAULT, mmio + CTRL1);
582 readl(mmio + CMD2);
594 writel(INTREN, lp->mmio + CMD0);
597 intr0 = readl(lp->mmio + INT0);
598 writel(intr0, lp->mmio + INT0);
601 readl(lp->mmio + INT0);
608 writel(RUN, lp->mmio + CMD0);
611 readl(lp->mmio + CMD0);
686 void __iomem *mmio = lp->mmio;
783 writel(VAL0|RINTEN0, mmio + INTEN0);
784 writel(VAL2 | RDMD0, mmio + CMD0);
798 status0 = readl(lp->mmio + STAT0);
835 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
841 writew(MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
843 status = readw(mmio + MIB_ADDR);
848 data = readl(mmio + MIB_DATA);
858 void __iomem *mmio = lp->mmio;
867 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
868 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
869 amd8111e_read_mib(mmio, rcv_unicast_pkts);
872 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
875 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
878 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
882 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
883 amd8111e_read_mib(mmio, rcv_fragments)+
884 amd8111e_read_mib(mmio, rcv_jabbers)+
885 amd8111e_read_mib(mmio, rcv_alignment_errors)+
886 amd8111e_read_mib(mmio, rcv_fcs_errors)+
887 amd8111e_read_mib(mmio, rcv_miss_pkts)+
891 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
894 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
897 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
900 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
903 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
907 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
908 amd8111e_read_mib(mmio, rcv_oversize_pkts);
911 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
914 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
918 amd8111e_read_mib(mmio, rcv_alignment_errors);
921 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
924 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
928 amd8111e_read_mib(mmio, xmt_excessive_collision);
932 amd8111e_read_mib(mmio, xmt_loss_carrier);
935 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
939 amd8111e_read_mib(mmio, xmt_late_collision);
942 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1082 void __iomem *mmio = lp->mmio;
1092 writel(INTREN, mmio + CMD0);
1095 intr0 = readl(mmio + INT0);
1096 intren0 = readl(mmio + INTEN0);
1106 writel(intr0, mmio + INT0);
1112 writel(RINTEN0, mmio + INTEN0);
1118 writel(RINTEN0, mmio + INTEN0);
1135 writel(VAL0 | INTREN, mmio + CMD0);
1284 writel(VAL1 | TDMD0, lp->mmio + CMD0);
1285 writel(VAL2 | RDMD0, lp->mmio + CMD0);
1296 void __iomem *mmio = lp->mmio;
1298 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1299 buf[1] = readl(mmio + XMT_RING_LEN0);
1300 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1301 buf[3] = readl(mmio + RCV_RING_LEN0);
1302 buf[4] = readl(mmio + CMD0);
1303 buf[5] = readl(mmio + CMD2);
1304 buf[6] = readl(mmio + CMD3);
1305 buf[7] = readl(mmio + CMD7);
1306 buf[8] = readl(mmio + INT0);
1307 buf[9] = readl(mmio + INTEN0);
1308 buf[10] = readl(mmio + LADRF);
1309 buf[11] = readl(mmio + LADRF+4);
1310 buf[12] = readl(mmio + STAT0);
1325 writel(VAL2 | PROM, lp->mmio + CMD2);
1329 writel(PROM, lp->mmio + CMD2);
1335 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1342 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1344 writel(PROM, lp->mmio + CMD2);
1354 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1357 readl(lp->mmio + CMD2);
1506 writeb(dev->dev_addr[i], lp->mmio + PADR + i);
1532 writel(RUN, lp->mmio + CMD0);
1545 writel(VAL1 | MPPLBA, lp->mmio + CMD3);
1546 writel(VAL0 | MPEN_SW, lp->mmio + CMD7);
1549 readl(lp->mmio + CMD7);
1557 writel(VAL0 | LCMODE_SW, lp->mmio + CMD7);
1560 readl(lp->mmio + CMD7);
1646 void __iomem *mmio = lp->mmio;
1675 amd8111e_read_mib(mmio, xmt_collisions);
1694 writew((u32)tmp_ipg, mmio + IPG);
1695 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1803 lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1804 if (!lp->mmio) {
1812 addr[i] = readb(lp->mmio + PADR + i);
1863 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000) >> 28;