#
a30c6251 |
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02-Oct-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Switch to use acpi_evaluate_dsm_typed() The acpi_evaluate_dsm_typed() provides a way to check the type of the object evaluated by _DSM call. Use it instead of open coded variant. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20231002135103.2602847-1-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3d757ddb |
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10-Aug-2023 |
Chevron Li <chevron.li@bayhubtech.com> |
mmc: sdhci-pci-o2micro: add Bayhub new chip GG8 support for UHS-I Add Bayhub new chip GG8 support for UHS-I function Signed-off-by: Chevron Li <chevron.li@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230811033517.11532-1-chevron_li@126.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
f3a5b56c |
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09-Jun-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add Genesys Logic GL9767 support Add support for the GL9767 chipset. GL9767 supports SD3 mode likes UHS-I SDR50, SDR104. Enable MSI interrupt for GL9767. Some platform do not support PCI INTx and devices can not work without interrupt. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230609071441.451464-2-victorshihgli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8e0ec111 |
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13-Jan-2023 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Replace SDHCI_QUIRK_MISSING_CAPS for Ricoh controller SDHCI_QUIRK_MISSING_CAPS is not needed because __sdhci_read_caps() can be called instead. In preparation to get rid of SDHCI_QUIRK_MISSING_CAPS, replace SDHCI_QUIRK_MISSING_CAPS with __sdhci_read_caps() for Ricoh SDHCI controller. __sdhci_read_caps() is also called from sdhci_setup_host() via sdhci_read_caps(), however only the first call to __sdhci_read_caps() does anything because after that host->read_caps has been set to true. Note, __sdhci_read_caps() does more than just set host->caps, such as do a reset, so calling __sdhci_read_caps() earlier could have unforeseen side-effects. However the code flow has been reviewed with that in mind. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230113110011.129835-2-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
dc4e9e2a |
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28-Oct-2022 |
Brian Norris <briannorris@chromium.org> |
mmc: sdhci-pci: Set PROBE_PREFER_ASYNCHRONOUS This driver often takes on the order of 10ms to start, but in some cases as much as 190ms. It shouldn't have many cross-device dependencies to race with, nor racy access to shared state with other drivers, so this should be a relatively low risk change. We've done similarly with a variety of other MMC host drivers already. This driver was pinpointed as part of a survey of top slowest initcalls (i.e., are built in, and probing synchronously) on a lab of ChromeOS systems. Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20221028155633.1.I6c4bfb31e88fad934e7360242cb662e01612c1bb@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
08b863bb |
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26-Oct-2022 |
Brian Norris <briannorris@chromium.org> |
mmc: sdhci-*: Convert drivers to new sdhci_and_cqhci_reset() An earlier patch ("mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI") does these operations for us. I keep these as a separate patch, since the earlier patch is a prerequisite to some important bugfixes that need to be backported via linux-stable. Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20221026124150.v4.7.Ia91f031f5f770af7bd2ff3e28b398f277606d970@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
222cfa01 |
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14-Nov-2022 |
Xiongfeng Wang <wangxiongfeng2@huawei.com> |
mmc: sdhci-pci: Fix possible memory leak caused by missing pci_dev_put() pci_get_device() will increase the reference count for the returned pci_dev. We need to use pci_dev_put() to decrease the reference count before amd_probe() returns. There is no problem for the 'smbus_dev == NULL' branch because pci_dev_put() can also handle the NULL input parameter case. Fixes: 659c9bc114a8 ("mmc: sdhci-pci: Build o2micro support in the same module") Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221114083100.149200-1-wangxiongfeng2@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
9dc0033e |
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13-Oct-2022 |
Patrick Thompson <ptf@google.com> |
mmc: sdhci-pci-core: Disable ES for ASUS BIOS on Jasper Lake Enhanced Strobe (ES) does not work correctly on the ASUS 1100 series of devices. Jasper Lake eMMCs (pci_id 8086:4dc4) are supposed to support ES. There are also two system families under the series, thus this is being scoped to the ASUS BIOS. The failing ES prevents the installer from writing to disk. Falling back to HS400 without ES fixes the issue. Signed-off-by: Patrick Thompson <ptf@google.com> Fixes: 315e3bd7ac19 ("mmc: sdhci-pci: Add support for Intel JSL") Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221013210017.3751025-1-ptf@google.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6fbde9e9 |
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26-Sep-2022 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Get rid of SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS is used by only ENE controllers but can be replaced by driver code. Amend the ENE code to hook the ->set_ios() mmc host operation and do the reset there. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220926192022.85660-4-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a22f18bd |
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13-Jun-2022 |
Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
ACPI / MMC: PM: Unify fixing up device power Introduce acpi_device_fix_up_power_extended() for fixing up power of a device having an ACPI companion in a manner that takes the device's children into account and make the MMC code use it in two places instead of walking the list of the device ACPI companion's children directly. This will help to eliminate the children list head from struct acpi_device as it is redundant and it is used in questionable ways in some places (in particular, locking is needed for walking the list pointed to it safely, but it is often missing). Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e53e97f8 |
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24-Nov-2021 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add PCI ID for Intel ADL Add PCI ID for Intel ADL eMMC host controller. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20211124094850.1783220-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
976171c3 |
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14-Oct-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Remove dead code (rst_n_gpio et al) There is no user of this member. Remove the dead code for good. The removal is dependent on the previous removal of the struct sdhci_pci_data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211014132613.27861-6-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
67f7296e |
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14-Oct-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Remove dead code (cd_gpio, cd_irq et al) The last user of this struct gone couple of releases ago. Remove the dead code for good and encourage people to use MMC core functionality for that. The removal is dependent on the previous removal of the struct sdhci_pci_data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211014132613.27861-5-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5c67aa59 |
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14-Oct-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Remove dead code (struct sdhci_pci_data et al) The last user of this struct gone a couple of releases ago. Besides that there were not so many users of this API for more than 10 years: 1/ The one is Intel Merrifield, that had been added 2016-08-31 by the commit 3976b0380b31 ("x86/platform/intel-mid: Enable SD card detection on Merrifield") and removed 2021-02-11 by the commit 4590d98f5a4f ("sfi: Remove framework for deprecated firmware"). 2/ The other is Intel Sunrisepoint related, that had been added 2015-02-06 by the commit e1bfad6d936d ("mmc: sdhci-pci: Add support for drive strength selection for SPT") and removed 2017-03-20 by the commit 51ced59cc02e ("mmc: sdhci-pci: Use ACPI DSM to get driver strength for some Intel devices"). Effectively this is a revert of the commit 52c506f0bc72 ("mmc: sdhci-pci: add platform data"). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211014132613.27861-4-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2caa11bc |
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14-Oct-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci: Deduplicate sdhci_get_cd_nogpio() The analogue of the sdhci_get_cd_nogpio() is used in the sdhci-pci-core and sdhci-acpi modules. Deduplicate it by moving to sdhci and exporting. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211014132613.27861-2-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6ab4e2eb |
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13-Oct-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Read card detect from ACPI for Intel Merrifield Intel Merrifield platform had been converted to use ACPI enumeration. However, the driver missed an update to retrieve card detect GPIO. Fix it here. Unfortunately we can't rely on CD GPIO state because there are two different PCB designs in the wild that are using the opposite card detection sense and there is no way to distinguish those platforms, that's why ignore CD GPIO completely and use it only as an event. Fixes: 4590d98f5a4f ("sfi: Remove framework for deprecated firmware") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20211013201723.52212-2-andriy.shevchenko@linux.intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2970134b |
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31-Mar-2021 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix initialization of some SD cards for Intel BYT-based controllers Bus power may control card power, but the full reset done by SDHCI at initialization still may not reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. That might be needed to initialize correctly, if the card was left powered on previously. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210331081752.23621-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ee629112 |
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21-Mar-2021 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add PCI IDs for Intel LKF Add PCI IDs for Intel LKF eMMC and SD card host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210322055356.24923-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ba8734df |
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11-Mar-2021 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-pci: Avoid comma separated statements Use semicolons. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210311181432.6385cd2b@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
60d53566 |
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12-Nov-2020 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers A UHS setting of SDR25 can give better results for High Speed mode. This is because there is no setting corresponding to high speed. Currently SDHCI sets no value, which means zero which is also the setting for SDR12. There was an attempt to change this in sdhci.c but it caused problems for some drivers, so it was reverted and the change was made to sdhci-brcmstb in commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS mode"). Several other drivers also do this. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v5.4+ Link: https://lore.kernel.org/r/20201112133656.20317-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
afd7f308 |
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26-Sep-2020 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sdhci: Workaround broken command queuing on Intel GLK based IRBIS models Commit bedf9fc01ff1 ("mmc: sdhci: Workaround broken command queuing on Intel GLK"), disabled command-queuing on Intel GLK based LENOVO models because of it being broken due to what is believed to be a bug in the BIOS. It seems that the BIOS of some IRBIS models, including the IRBIS NB111 model has the same issue, so disable command queuing there too. Fixes: bedf9fc01ff1 ("mmc: sdhci: Workaround broken command queuing on Intel GLK") BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209397 Reported-and-tested-by: RussianNeuroMancer <russianneuromancer@ya.ru> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200927104821.5676-1-hdegoede@redhat.com Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
46f4a69e |
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18-Aug-2020 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Add LTR support for some Intel BYT based controllers Some Intel BYT based host controllers support the setting of latency tolerance. Accordingly, implement the PM QoS ->set_latency_tolerance() callback. The raw register values are also exposed via debugfs. Intel EHL controllers require this support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: cb3a7d4a0aec4e ("mmc: sdhci-pci: Add support for Intel EHL") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200818104508.7149-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
df57d732 |
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19-Aug-2020 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers For Intel controllers, SDHCI_RESET_ALL resets also CQHCI registers. Normally, SDHCI_RESET_ALL is not used while CQHCI is enabled, but that can happen on the error path. e.g. if mmc_cqe_recovery() fails, mmc_blk_reset() is called which, for a eMMC that does not support HW Reset, will cycle the bus power and the driver will perform SDHCI_RESET_ALL. So whenever performing SDHCI_RESET_ALL ensure CQHCI is deactivated. That will force the driver to reinitialize CQHCI when it is next used. A similar change was done already for sdhci-msm, and other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL. Fixes: 8ee82bda230fc9 ("mmc: sdhci-pci: Add CQHCI support for Intel GLK") Cc: stable@vger.kernel.org # 5.4.x: 0ffa6cfbd949: mmc: cqhci: Add cqhci_deactivate() Cc: stable@vger.kernel.org # 5.4+ Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200819121848.16967-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1ae1d2d6 |
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08-May-2020 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add Genesys Logic GL9763E support GL9763E supports High Speed SDR, High Speed DDR, HS200, HS400, Enhanced Strobe in HS400 mode, 1/4/8 bits data bus and 3.3/1.8V. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20200508064154.13473-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a8e809ec |
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08-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
mmc: sdhci: use FIELD_GET/PREP for capabilities bit masks Use FIELD_GET and FIELD_PREP to get access to the register fields. Delete the shift macros and use GENMASK() for the touched macros. Note that, this has the side-effect of changing the constants to 64-bit on 64-bit platforms. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200408072105.422-2-yamada.masahiro@socionext.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1a8eb6b3 |
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22-Apr-2020 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix eMMC driver strength for BYT-based controllers BIOS writers have begun the practice of setting 40 ohm eMMC driver strength even though the eMMC may not support it, on the assumption that the kernel will validate the value against the eMMC (Extended CSD DRIVER_STRENGTH [offset 197]) and revert to the default 50 ohm value if 40 ohm is invalid. This is done to avoid changing the value for different boards. Putting aside the merits of this approach, it is clear the eMMC's mask of supported driver strengths is more reliable than the value provided by BIOS. Add validation accordingly. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 51ced59cc02e ("mmc: sdhci-pci: Use ACPI DSM to get driver strength for some Intel devices") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200422111629.4899-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
bedf9fc0 |
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17-Dec-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Workaround broken command queuing on Intel GLK Command queuing has been reported broken on some Lenovo systems based on Intel GLK. This is likely a BIOS issue, so disable command queuing for Intel GLK if the BIOS vendor string is "LENOVO". Fixes: 8ee82bda230f ("mmc: sdhci-pci: Add CQHCI support for Intel GLK") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191217095349.14592-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d0052ad9 |
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10-Dec-2019 |
Michał Mirosław <mirq-linux@rere.qmqm.pl> |
mmc: core: Remove mmc_gpiod_request_*(invert_gpio) Now that invert_gpio arguments are unused, let's remove them. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/64d766d1f8af2e22bce32f4ffa453f7234207ad6.1576031637.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
315e3bd7a |
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10-Oct-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel JSL Add PCI Ids for Intel JSL. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
38413ce3 |
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04-Oct-2019 |
zhengbin <zhengbin13@huawei.com> |
mmc: sdhci-pci: Make function amd_sdhci_reset static Fix sparse warnings: drivers/mmc/host/sdhci-pci-core.c:1599:6: warning: symbol 'amd_sdhci_reset' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
7a869f00 |
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04-Sep-2019 |
Raul E Rangel <rrangel@chromium.org> |
mmc: sdhci-pci: Quirk for AMD SDHC Device 0x7906 AMD SDHC 0x7906 requires a hard reset to clear all internal state. Otherwise it can get into a bad state where the DATA lines are always read as zeros. This change requires firmware that can transition the device into D3Cold for it to work correctly. If the firmware does not support transitioning to D3Cold then the power state transitions are a no-op. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e51df6ce |
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11-Sep-2019 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: host: sdhci-pci: Add Genesys Logic GL975x support Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8f05eee6 |
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30-Jul-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add another Id for Intel CML Add another PCI Id for Intel CML. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
90b51e3c |
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23-Jul-2019 |
Chuhong Yuan <hslester96@gmail.com> |
mmc: sdhci-pci: Use dev_get_drvdata Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c6303c5d |
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24-Jul-2019 |
Baolin Wang <baolin.wang@linaro.org> |
mmc: sdhci-sprd: Fix the incorrect soft reset operation when runtime resuming The SD host controller specification defines 3 types software reset: software reset for data line, software reset for command line and software reset for all. Software reset for all means this reset affects the entire Host controller except for the card detection circuit. In sdhci_runtime_resume_host() we always do a software "reset for all", which causes the Spreadtrum variant controller to work abnormally after resuming. To fix the problem, let's do a software reset for the data and the command part, rather than "for all". However, as sdhci_runtime_resume() is a common sdhci function and we don't want to change the behaviour for other variants, let's introduce a new in-parameter for it. This enables the caller to decide if a "reset for all" shall be done or not. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
cb3a7d4a |
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19-Jun-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel EHL Add PCI Ids for Intel EHL. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
90298dc3 |
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30-May-2019 |
Colin Ian King <colin.king@canonical.com> |
mmc: sdhci-pci: remove redundant check of slots == 0 The calculation of slots results in a value in the range 1..8 and so slots can never be zero. The check for slots == 0 is always going to be false, hence it is redundant and can be removed. Addresses-Coverity: ("Logically dead code") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
0a49a619 |
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06-May-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix BYT OCP setting Some time ago, a fix was done for the sdhci-acpi driver, refer commit 6e1c7d6103fe ("mmc: sdhci-acpi: Reduce Baytrail eMMC/SD/SDIO hangs"). The same issue was not expected to affect the sdhci-pci driver, but there have been reports to the contrary, so make the same hardware setting change. This patch applies to v5.0+ but before that backports will be required. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
765c5967 |
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08-Apr-2019 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel CML Add PCI Ids for Intel CML. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
328be8be |
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03-Jan-2019 |
Ernest Zhang(WH) <ernest.zhang@bayhubtech.com> |
mmc: sdhci: Moving sdhci_o2 into sdhci-pci-o2micro.c Moving sdhci_o2 into sdhci-pci-o2micro.c Signed-off-by: Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
aeae6ad3 |
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11-Dec-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Disable LED control for Intel BYT-based controllers Intel BYT-based controllers do not have a LED signal line. Nevertheless sdhci_led_control() takes more than twice as long as sdhci_send_command(), even though it does nothing. Use the new SDHCI_QUIRK_NO_LED quirk to disable LED control for Intel BYT-based controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
809090e8 |
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27-Nov-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add max-frequency device property for Intel controllers Add support for the mmc max-frequency device property for Intel BYT-based host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5305ec6a |
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19-Nov-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Workaround GLK firmware failing to restore the tuning value GLK firmware can indicate that the tuning value will be restored after runtime suspend, but not actually do that. Add a workaround that detects such cases, and lets the driver do re-tuning instead. Reported-by: Anisse Astier <anisse@astier.eu> Tested-by: Anisse Astier <anisse@astier.eu> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
cdcefe6b |
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29-Oct-2018 |
Rajat Jain <rajatja@google.com> |
mmc: sdhci-pci: Try "cd" for card-detect lookup before using NULL Problem: The card detect IRQ does not work with modern BIOS (that want to use _DSD to provide the card detect GPIO to the driver). Details: The mmc core provides the mmc_gpiod_request_cd() API to let host drivers request the gpio descriptor for the "card detect" pin. This pin is specified in the ACPI for the SDHC device: * Either as a resource using _CRS. This is a method used by legacy BIOS. (The driver needs to tell which resource index). * Or as a named property ("cd-gpios"/"cd-gpio") in _DSD (which internally points to an entry in _CRS). This way, the driver can lookup using a string. This is what modern BIOS prefer to use. This API finally results in a call to the following code: struct gpio_desc *acpi_find_gpio(..., const char *con_id,...) { ... /* Lookup gpio (using "<con_id>-gpio") in the _DSD */ ... if (!acpi_can_fallback_to_crs(adev, con_id)) return ERR_PTR(-ENOENT); ... /* Falling back to _CRS is allowed, Lookup gpio in the _CRS */ ... } Note that this means that if the ACPI has _DSD properties, the kernel will never use _CRS for the lookup (Because acpi_can_fallback_to_crs() will always be false for any device hat has _DSD entries). The SDHCI driver is thus currently broken on a modern BIOS, even if BIOS provides both _CRS (for index based lookup) and _DSD entries (for string based lookup). Ironically, none of these will be used for the lookup currently because: * Since the con_id is NULL, acpi_find_gpio() does not find a matching entry in DSDT. (The _DSDT entry has the property name = "cd-gpios") * Because ACPI contains DSDT entries, thus acpi_can_fallback_to_crs() returns false (because device properties have been populated from _DSD), thus the _CRS is never used for the lookup. Fix: Try "cd" for lookup in the _DSD before falling back to using NULL so as to try looking up in the _CRS. I've tested this patch successfully with both Legacy BIOS (that provide only _CRS method) as well as modern BIOS (that provide both _CRS and _DSD). Also the use of "cd" appears to be fairly consistent across other users of this API (other MMC host controller drivers). Link: https://lkml.org/lkml/2018/9/25/1113 Signed-off-by: Rajat Jain <rajatja@google.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: f10e4bf6632b ("gpio: acpi: Even more tighten up ACPI GPIO lookups") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
152f8204 |
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11-Jul-2018 |
Prabu Thangamuthu <Prabu.T@synopsys.com> |
mmc: sdhci-pci-dwc-mshc: synopsys dwc mshc support Synopsys has DWC MSHC controller on HPAS-DX platform connected using PCIe interface with SD card slot and eMMC device slots. This patch is to enable SD cards connected on this platform. As Clock generation logic is implemented using MMCM module of HAPS-DX platform, we have separate functions to control the MMCM to generate required clocks with respect to speed mode. Signed-off-by: Prabu Thangamuthu <prabu.t@synopsys.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5637ffad |
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20-Jun-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel ICP Add PCI Ids for Intel ICP. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
be17355a |
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13-Apr-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix 3.3V voltage switch for some BYT-based Intel controllers Fix 3.3V voltage switch for some BYT-based Intel controllers by making use of the ACPI DSM. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
bb26b841 |
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13-Apr-2018 |
Kyle Roeschley <kyle.roeschley@ni.com> |
mmc: sdhci-pci: Avoid 3.3V signaling on some NI 904x On some NI 904x devices, using 3.3V signaling for extended periods of time will physically damage the pads connected to the SDHC, eventually causing complete failure of the controller. To work around this, require that we avoid 3.3V signaling. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Jennifer Dahm <jennifer.dahm@ni.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
300ad899 |
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06-Apr-2018 |
Daniel Kurtz <djkurtz@chromium.org> |
mmc: sdhci-pci: Only do AMD tuning for HS200 Commit c31165d7400b ("mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1") added a HS200 tuning method for use with AMD SDHCI controllers. As described in the commit subject, this tuning is specific for HS200. However, as implemented, this method is used for all host timings, because platform_execute_tuning, if it exists, is called unconditionally by sdhci_execute_tuning(). This breaks tuning when using the AMD controller with, for example, a DDR50 SD card. Instead, we can implement an amd execute_tuning wrapper callback, and then conditionally do the HS200 specific tuning for HS200, and otherwise call back to the standard sdhci_execute_tuning(). Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: c31165d7400b ("mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1") Cc: stable@vger.kernel.org # v4.11+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d56ee1ff |
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27-Feb-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Respect PM flags when enabling card detect GPIO IRQ wakeup Commit 03dbaa04a2e5 ("mmc: slot-gpio: Add support to enable irq wake on cd_irq") enabled wakeup at initialization. However, users also want to control it from sysfs power/wakeup attribute. That means the driver needs to check the PM flags before enabling it in the suspend callback. Add support for that in sdhci-pci, which is the only driver presently using the MMC_CAP_CD_WAKE flag, and remove the enabling in mmc_gpiod_request_cd_irq() Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
7b7d57fd |
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14-Feb-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Get rid of glk_cqe_enable() Now that tuning no longer leaves the Buffer Read Enable bit set (refer intel_execute_tuning()), glk_cqe_enable() is no longer needed. Get rid of it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
f8870ae6 |
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14-Feb-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix S0i3 for Intel BYT-based controllers Tuning can leave the IP in an active state (Buffer Read Enable bit set) which prevents the entry to low power states (i.e. S0i3). Data reset will clear it. Generally tuning is followed by a data transfer which will anyway sort out the state, so it is rare that S0i3 is actually prevented. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e92cc35d |
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09-Jan-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Use device wakeup capability to determine MMC_PM_WAKE_SDIO_IRQ capability PCI and ACPI determine if a device is wakeup capable, so use that to determine the MMC_PM_WAKE_SDIO_IRQ capability correctly. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5c3c6126 |
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09-Jan-2018 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Stop calling sdhci_enable_irq_wakeups() sdhci_enable_irq_wakeups() is already called by sdhci_suspend_host() so sdhci-pci should not need to call it. However sdhci_suspend_host() only calls it if wakeups are enabled, and sdhci-pci does not enable them until after calling sdhci_suspend_host(). So move the calls to sdhci_pci_init_wakeup() before calling sdhci_suspend_host(), and stop calling sdhci_enable_irq_wakeups(). That results in some simplification because sdhci_pci_suspend_host() and __sdhci_pci_suspend_host() no longer need to be separate functions. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2a609abe |
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11-Jan-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci: Advertise 2.0v supply on SDIO host controller On Intel Edison the Broadcom Wi-Fi card, which is connected to SDIO, requires 2.0v, while the host, according to Intel Merrifield TRM, supports 1.8v supply only. The card announces itself as mmc2: new ultra high speed DDR50 SDIO card at address 0001 Introduce a custom OCR mask for SDIO host controller on Intel Merrifield and add a special case to sdhci_set_power_noreg() to override 2.0v supply by enforcing 1.8v power choice. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d72d72cd |
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03-Jan-2018 |
Atul Garg <agarg@arasan.com> |
mmc:host:sdhci-pci:Addition of Arasan PCI Controller with integrated phy. The Arasan Controller is based on a FPGA platform and has integrated phy with specific registers used during initialization and management of different modes. The phy and the controller are integrated and registers are very specific to Arasan. Arasan being an IP provider, licenses these IPs to various companies for integration of IP in custom SOCs. The custom SOCs define own register map depending on how bits are tied inside the SOC for phy registers, depending on SOC memory plan and hence will require own platform drivers. If more details on phy registers are required, an interface document is hosted at https://arasan.com/NF/eMMC5.1 PHY Programming in Linux.pdf. Signed-off-by: Atul Garg <agarg@arasan.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8ee82bda |
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29-Nov-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add CQHCI support for Intel GLK Add CQHCI initialization and implement CQHCI operations for Intel GLK. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org>
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#
361eeda0 |
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19-Oct-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Tidy o2micro definitions We keep PCI Ids in sdhci-pci.h and the O2-specific definitions belong in sdhci-pci-o2micro.c. Move those definitions accordingly. Remove unused O2 definitions in sdhci-pci-core.c. The 3 o2micro external function declarations might as well be in sdhci-pci.h as well, so move them there and get rid of sdhci-pci-o2micro.h entirely. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
cdaba732 |
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18-Sep-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel CDF Add PCI Id for Intel CDF. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
eb701ce1 |
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09-Oct-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix default d3_retune for Intel host controllers The default for d3_retune is true, but that was not being set in all cases, which results in eMMC errors because re-tuning has not been done. Fix by initializing d3_retune to true. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: c959a6b00ff5 ("mmc: sdhci-pci: Don't re-tune with runtime pm for some Intel devices") Cc: stable@vger.kernel.org # v4.12+ Reported-and-tested-by: ojab <ojab@ojab.ru> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6ae03368 |
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18-Sep-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix voltage switch for some Intel host controllers Some Intel host controllers (e.g. CNP) use an ACPI device-specific method to ensure correct voltage switching. Fix voltage switch for those, by adding a call to the DSM. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
adc16398 |
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14-Aug-2017 |
Michał Mirosław <mirq-linux@rere.qmqm.pl> |
mmc: sdhci-pci: use generic sdhci_set_bus_width() Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
0e39220e |
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24-Jul-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci: pci: Fix up power if device has ACPI companion Fix up a power state in case PCI device has an ACPI companion. Do it only for Intel Merrifield for now. This is almost copy'n'paste of part of sdhci_acpi_probe() and might be split out to a helper function in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6cf4156c |
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13-Jun-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Enable card detect wake for Intel BYT-related SD controllers Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d2a47176 |
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08-Jun-2017 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: core: Remove MMC_CAP2_HC_ERASE_SZ The MMC_CAP2_HC_ERASE_SZ is used only by a few mmc host drivers. Its intent is to enable eMMC's high-capacity erase size, as to improve the behaviour of the erase operations. We should strive to avoid software configuration options that aren't necessary, but instead deploy common behaviours. For these reasons, let's remove the capability bit for MMC_CAP2_HC_ERASE_SZ and make it the default behaviour. Note that this change doesn't affect eMMCs supporting trim/discard, because these commands operates on sectors and takes precedence over erase commands. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
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#
bc55dcd8 |
|
31-May-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel CNP Add PCI ids and enhanced strobe support for Intel CNP. This is combined with GLK due to the pending CMDQ support which they both share. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c949c907 |
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15-May-2017 |
Matthias Kraemer <matthiasmartinsson@gmail.com> |
mmc: sdhci-pci: Use macros in pci_ids definition This patch applies customized PCI_DEVICE_ macros to specify the pci_ids instead of open-coding them within the sdhci-pci driver. By introducing device specific macros the pci_ids table becomes much shorter and easier to comprehend than it would be possible using the generic version of the PCI_DEVICE_ macros. Signed-off-by: Matthias Kraemer <matthiasmartinsson@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c37f69ff |
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19-Jun-2017 |
Colin Ian King <colin.king@canonical.com> |
mmc: sdhci-pci: make guid intel_dsm_guid static The guid intel_dsm_guid does not need to be in global scope, so make it static. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
94116f81 |
|
05-Jun-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
ACPI: Switch to use generic guid_t in acpi_evaluate_dsm() acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16 bytes. Instead we convert them to use guid_t type. At the same time we convert current users. acpi_str_to_uuid() becomes useless after the conversion and it's safe to get rid of it. Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Borislav Petkov <bp@suse.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Cc: Amir Goldstein <amir73il@gmail.com> Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Cc: Ben Skeggs <bskeggs@redhat.com> Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: Joerg Roedel <jroedel@suse.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
|
#
a72016a4 |
|
19-Apr-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Allow for 3 bytes from Intel DSM The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c2c49a2e |
|
29-Mar-2017 |
Azhar Shaikh <azhar.shaikh@intel.com> |
mmc: sdhci-pci: Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel controllers Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel SD card controllers. Signed-off-by: Azhar Shaikh <azhar.shaikh@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
48d685a2 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Move a function to avoid later forward declaration Move a function to avoid having to forward declare it in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
966d696a |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add runtime suspend/resume callbacks Add runtime suspend/resume callbacks to match suspend/resume callbacks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
30cf2803 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Let suspend/resume callbacks replace default callbacks The suspend / resume callbacks lack the flexibility to allow a device to specify a different function entirely. Change them around so that device functions are called directly and they in turn can call the default implementations if needed. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
b7813f0f |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Conditionally compile pm sleep functions It is confusing to have some parts of suspend / resume under conditional compilation and some parts not. Use conditional compilation everywhere. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
1cb0a58e |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Do not use suspend/resume callbacks with runtime pm Do not use suspend/resume callbacks with runtime pm. It doesn't make sense and isn't being used, so remove. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
61c951de |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Let devices define how to add the host SDHCI provides more flexibility than simply calling sdhci_add_host(). Make that available by allowing devices to specify their own ->add_host() function. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
d1e4f74f |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Do not use spin lock in set_ios paths The spin lock is not necessary in set_ios. Anything that is racing with changes to the I/O state is already broken. The mmc core already provides synchronization via "claiming" the host. So remove spin_lock and friends from sdhci_set_ios and related callbacks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
0c62e675 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Remove ->select_drive_strength() callback Drivers can use the host operation directly, so remove this now unused callback. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
51ced59c |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Use ACPI DSM to get driver strength for some Intel devices Make use of an Intel ACPI _DSM that provides eMMC driver strength. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
c959a6b0 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Don't re-tune with runtime pm for some Intel devices Make use of an Intel ACPI _DSM that indicates if re-tuning is needed after D3. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
ac9f67b5 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Let devices define their own private data Let devices define their own private data to facilitate device-specific operations. The size of the private structure is specified in the sdhci_pci_fixes structure, then sdhci_pci_probe_slot() will allocate extra space for it, and sdhci_pci_priv() can be used to get a reference to it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
d38dcad4 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Let drivers decide whether to use mmc_retune_needed() with pm Devices might save and restore tuning values so that re-tuning might not be needed after a pm transition. Let drivers decide by pushing the mmc_retune_needed() logic down to them. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
027fb89e |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Do not disable interrupts in sdhci_intel_set_power Disabling interrupts for even a millisecond can cause problems for some devices. That can happen when Intel host controllers wait for the present state to propagate. The spin lock is not necessary here. Anything that is racing with changes to the I/O state is already broken. The mmc core already provides synchronization via "claiming" the host. Although the spin lock probably should be removed from the code paths that lead to this point, such a patch would touch too much code to be suitable for stable trees. Consequently, for this patch, just drop the spin lock while waiting. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v4.9+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
c31165d7 |
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12-Jan-2017 |
Shyam Sundar S K <ssundark@amd.com> |
mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1 This patch adds support for HS200 tuning mode on AMD eMMC-4.5.1 Reviewed-by: Sen, Pankaj <Pankaj.Sen@amd.com> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com> Reviewed-by: Agrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6ac9b837 |
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02-Jan-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Remove unused member cd_con_id cd_con_id is not used and always NULL. Remove it to make code a bit more cleaner. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3f23df72 |
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28-Nov-2016 |
Zach Brown <zach.brown@ni.com> |
mmc: sdhci-pci: Use ACPI to get max frequency for Intel NI byt sdio On NI 9037 boards the max SDIO frequency is limited by trace lengths and other layout choices. The max SDIO frequency is stored in an ACPI table. The driver reads the ACPI entry MXFQ during sdio_probe_slot and sets the f_max field of the host. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Reviewed-by: Jaeden Amero <jaeden.amero@ni.com> Reviewed-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Zach Brown <zach.brown@ni.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
42b06496 |
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28-Nov-2016 |
Zach Brown <zach.brown@ni.com> |
mmc: sdhci-pci: Add PCI ID for Intel NI byt sdio Add PCI ID for Intel byt sdio host controller sub-vended by NI. The controller has different behavior because of the board layout NI puts it on. Signed-off-by: Zach Brown <zach.brown@ni.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8f743d03 |
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22-Nov-2016 |
David E. Box <david.e.box@linux.intel.com> |
mmc: sdhci-pci: Allow deferred probe for sd card detect gpio With commit f35bbf61ab77 ("gpio / ACPI: Return -EPROBE_DEFER if the gpiochip was not found"), a gpio descriptor request can now be deferred if the providing gpio host controller driver hasn't been loaded yet. Allow use in mmc slot probe in order to prevent card detect gpio setup from failing in this case. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2d1956d0 |
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22-Nov-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support for Intel GLK Add support for eMMC/SD/SDIO Intel GLK host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
fee686b7 |
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04-Oct-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix bus power failing to enable for some Intel controllers Some Intel controllers (e.g. BXT) might fail to set bus power after a D3 -> D0 transition due to the present state not yet having propagated. Retry for up to 2 milliseconds. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6bc09063 |
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04-Oct-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Let devices define their own sdhci_ops Let devices define their own sdhci_ops so that device-specific variations can be implemented without adding quirks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
32828857 |
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16-Aug-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Set MMC_CAP_CMD_DURING_TFR for Intel eMMC controllers Set MMC_CAP_CMD_DURING_TFR for Intel BYT and related eMMC host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
4674b6c8 |
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28-Aug-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci-pci: enable SD card interface on Merrifield Intel Merrifield provides an interface to an external SD card. Enable it here. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d5565577 |
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28-Aug-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci-pci: enable SDIO interface on Intel Merrifield Intel Merrifield is known to have an SDIO interface and on Intel Edison board a WiFi card is wired to it. Enable the interface here to allow WiFi card enumeration. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2e57bbe2 |
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28-Aug-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci-pci: refactor intel_mrfld_mmc_probe_slot() Refactor intel_mrfld_mmc_probe_slot() to use switch case. The change allows to add a support for SD and SDIO interfaces without any pain. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c10bc372 |
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18-Aug-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Convert to use managed functions (part2) The commit 52ac7acf412b ("mmc: sdhci-pci: Convert to use managed functions pcim_* and devm_*") converted ->probe() / ->remove() functions to use device managed resource API. Here is a follow up to cover sdhci_pci_probe_slot() and sdhci_pci_remove_slot(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
f9900f15 |
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27-Jul-2016 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: sdhci-pci-core: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS Convert to define the system PM callbacks to be build for CONFIG_PM_SLEEP and use the SET_SYSTEM_SLEEP_PM_OPS. In this way the code becomes cleaner. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1f64cec2 |
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12-Jul-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
sdhci-pci: Use MRFLD as abbreviation of Merrifield Everywhere else in the code MRFLD abbreviation is used for Intel Merrifield. Do the same for sdhci-pci. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
52ac7acf |
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09-Jul-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mmc: sdhci-pci: Convert to use managed functions pcim_* and devm_* This makes the error handling much more simpler than open-coding everything and in addition makes the probe function smaller an tidier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
00884b61 |
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29-Jun-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Do not runtime suspend at the end of sdhci_pci_probe() At the successful conclusion of sdhci_pci_probe(), if runtime pm was allowed, the device would be runtime suspended. That wastes a lot of time during initialization. Instead leave the device active until the mmc core scans for a card. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
82296936 |
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20-May-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Remove MMC_CAP_BUS_WIDTH_TEST for Intel controllers The CMD19/CMD14 bus width test has been found to be unreliable in some cases. It is not essential, so simply remove it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e8ef5176 |
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12-Apr-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Set MMC_CAP_AGGRESSIVE_PM for Broxton controllers Set MMC_CAP_AGGRESSIVE_PM for Broxton host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c8037e79 |
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21-Mar-2016 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: sdhci-pci: Remove redundant runtime PM calls Commit 9250aea76bfc ("mmc: core: Enable runtime PM management of host devices"), made some calls to the runtime PM API from the driver redundant. Especially those which deals with runtime PM reference counting, so let's remove them. Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
01d6b2a4 |
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03-Apr-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add support and PCI IDs for more Broxton host controllers Add support and PCI IDs for more Broxton host controllers Other BXT IDs were added in v4.4 so cc'ing stable. This patch is dependent on commit 163cbe31e516 ("mmc: sdhci-pci: Fix card detect race for Intel BXT/APL") but that is already in stable since v4.4.4. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v4.4+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
bd9ff18b |
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06-Mar-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
mmc: sdhci-pci: Do not set DMA mask in enable_dma() DMA mask will already be set by sdhci_set_dma_mask(), which is equivalent to the removed code since pci_set_dma_mask() expands to its DMA-API counterpart. There should also be no reason to set the DMA mask after probe. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
163cbe31 |
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09-Feb-2016 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Fix card detect race for Intel BXT/APL Intel BXT/APL use a card detect GPIO however the host controller will not enable bus power unless it's card detect also reflects the presence of a card. Unfortunately those 2 things race which can result in commands not starting, after which the controller does nothing and there is a 10 second wait for the driver's 10-second timer to timeout. That is fixed by having the driver look also at the present state register to determine if the card is present. Consequently, provide a 'get_cd' mmc host operation for BXT/APL that does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v4.4+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
923a231c |
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27-Dec-2015 |
Geliang Tang <geliangtang@163.com> |
mmc: sdhci-pci: use to_pci_dev() Use to_pci_dev() instead of open-coding it. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1ca89685 |
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26-Nov-2015 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Do not default to 33 Ohm driver strength for Intel SPT In some cases, the stronger 33 Ohm driver strength must not be used so it is not a suitable default. Change it to the standard default 50 Ohm value. The patch applies to v4.2+ except the file name changed. It is drivers/mmc/host/sdhci-pci.c prior to v.4.4. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v4.2+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
4fd4c065 |
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21-Oct-2015 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add more PCI IDs for Intel controllers Add PCI IDs for Intel host controllers Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
06bf9c56 |
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06-Oct-2015 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-pci: Add another PCI ID for an Intel eMMC host controller Add another PCI ID for an Intel eMMC host controller. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
7582041f |
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05-Oct-2015 |
kbuild test robot <lkp@intel.com> |
mmc: sdhci-pci: fix simple_return.cocci warnings drivers/mmc/host/sdhci-pci-core.c:447:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
659c9bc1 |
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05-Oct-2015 |
Ben Hutchings <ben@decadent.org.uk> |
mmc: sdhci-pci: Build o2micro support in the same module sdhci-pci-o2micro.c contains no initialisation and its functions are only called from shdci-pci.c, so there is no reason for it to be a separate module, let alone or for it to always be built-in. - Rename sdhci-pci.c to sdhci-pci-core.c so that the sdhci-pci module can be built from multiple source files - Add sdhci-pci-o2micro.c to it - Remove redundant exports Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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