/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_hdmi.c | 2152 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 3211 * @src_fraction_bpp: fractional bpp supported by the source 3215 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3233 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3234 * Start with the max bpp and keep on decrementing with 3235 * fractional bpp, if supported by PCON DSC encoder 3237 * for each bpp we check if no of bytes can be supported by HDMI sink 3257 * Transport with bpp_target settings above 12 bpp unless 3282 /* src does not support fractional bpp implie 3289 int bpp; local [all...] |
H A D | intel_dsi.c | 34 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); local 36 if (WARN_ON(bpp < 0)) 37 bpp = 16; 39 return intel_dsi->pclk * bpp / intel_dsi->lane_count;
|
H A D | intel_dp_mst.c | 173 int bpp, slots = -EINVAL; local 197 drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n", 202 drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", 205 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { 211 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); [all...] |
H A D | intel_dp.c | 387 * The required data bandwidth for a mode with given pixel clock and bpp. This 394 intel_dp_link_required(int pixel_clock, int bpp) argument 396 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 397 return DIV_ROUND_UP(pixel_clock * bpp, 8); 741 * lane DP link, with 2 DSC slices and 8 bpp color depth). 757 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) argument 759 u32 bits_per_pixel = bpp; 762 /* Error out if the max bpp is less than smallest allowed valid bpp */ 769 /* From XE_LPD onwards we support from bpc upto uncompressed bpp 1058 intel_dp_output_bpp(enum intel_output_format output_format, int bpp) argument 1167 int bpp = intel_dp_mode_min_output_bpp(connector, mode); local 1493 int bpp, bpc; local 1537 int bpp = 3 * intel_dp->compliance.test_data.bpc; local 1598 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); local 2394 int bpp = crtc_state->dsc.compression_enable ? local [all...] |
H A D | intel_dp.h | 30 /* Uncompressed DSC input or link output bpp in 1 bpp units */ 34 /* Compressed or uncompressed link output bpp in 1/16 bpp units */ 118 int intel_dp_link_required(int pixel_clock, int bpp); 172 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp); 190 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
|
H A D | intel_display_types.h | 327 int bpp; member in struct:intel_vbt_panel_data::__anon595 1131 * Enable dithering, used when the selected pipe bpp doesn't match the 1132 * plane bpp. 1137 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 1140 * 18bpp. 1152 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1182 int max_link_bpp_x16; /* in 1/16 bpp units */ 1183 int pipe_bpp; /* in 1 bpp units */ 2154 static inline int to_bpp_x16(int bpp) argument 2156 return bpp << [all...] |
H A D | intel_display.h | 409 void intel_link_compute_m_n(u16 bpp, int nlanes, 476 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
|
H A D | intel_display.c | 2904 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3295 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) argument 3302 u32 bps = target_clock * bpp * 21 / 20; 3897 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3899 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4320 int bpp; local 4324 bpp = 6 * 3; 4327 bpp = 8 * 3; 4330 bpp = 10 * 3; 4333 bpp 4364 int bpp, i; local [all...] |
H A D | intel_bios.c | 1402 panel->vbt.edp.bpp = 18; 1405 panel->vbt.edp.bpp = 24; 1408 panel->vbt.edp.bpp = 30;
|
H A D | icl_dsi.c | 330 int bpp; local 333 bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 337 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 860 * compressed and non-compressed bpp. 884 int bpp, line_time_us, byte_clk_period_ns; local 887 bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 889 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 892 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
|
/linux-master/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_g2d.c | 603 unsigned long bpp; local 608 bpp = 4; 615 bpp = 2; 618 bpp = 3; 621 bpp = 1; 625 return bpp; 634 unsigned long bpp, last_pos; local 658 bpp = g2d_get_buf_bpp(buf_desc->format); 663 (unsigned long)buf_desc->right_x * bpp - 1;
|
/linux-master/drivers/gpu/drm/ |
H A D | drm_modes.c | 1937 unsigned int bpp; local 1943 bpp = simple_strtol(str, end_ptr, 10); 1947 mode->bpp = bpp; 2345 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd] 2385 /* Try to locate the bpp and refresh specifiers, if any */ 2468 * Locate the end of the bpp / refresh, and parse the extras
|
H A D | drm_gem_vram_helper.c | 478 pitch = args->width * DIV_ROUND_UP(args->bpp, 8);
|
H A D | drm_gem_shmem_helper.c | 493 u32 min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
|
H A D | drm_client.c | 297 dumb_args.bpp = drm_format_info_bpp(info, 0);
|
/linux-master/drivers/gpu/drm/display/ |
H A D | drm_dp_mst_topology.c | 4744 * @bpp: bpp as .4 binary fixed point 4748 int drm_dp_calc_pbn_mode(int clock, int bpp) argument 4755 * peak_kbps = clock * bpp / 16 4767 int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp, 4771 return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
|
/linux-master/drivers/gpu/drm/bridge/cadence/ |
H A D | cdns-mhdp8546-core.c | 1569 u32 bpp; local 1577 bpp = fmt->bpc * 3; 1580 bpp = fmt->bpc * 2; 1583 bpp = fmt->bpc * 3 / 2; 1586 bpp = fmt->bpc * 3; 1589 return bpp; 1597 u32 max_bw, req_bw, bpp; local 1600 * mode->clock is expressed in kHz. Multiplying by bpp and dividing by 8 1606 bpp = cdns_mhdp_get_bpp(&mhdp->display_fmt); 1607 req_bw = mode->clock * bpp / 1779 u32 bpp, bpc, pxlfmt, framer; local 1948 u32 bpp; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
H A D | dcn315_resource.c | 1699 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); local 1702 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 2220 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); local 2223 if (bpp == 64)
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
H A D | dcn10_resource.c | 1226 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); local 1230 if (bpp == 64)
|
/linux-master/drivers/gpu/drm/amd/display/dc/dsc/ |
H A D | dc_dsc.c | 35 /* default DSC policy target bitrate limit is 16bpp */ 64 struct fixed31_32 bpp; local 67 bpp = dc_fixpt_from_int(kbps); 68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); 70 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) 74 overhead_factor = dc_fixpt_mul(overhead_factor, bpp); 290 // Mask bpp increment dpcd field to avoid reading other fields 611 * The range output includes decided min/max target bpp, the respective bandwidth requirements 637 /* apply max bpp limitatio 1119 struct fixed31_32 bpp; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 828 int pix_clk_100hz, int bpp, int seg_size_kb) 833 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp 826 dcn_get_approx_det_segs_required_for_pstate( struct _vcs_dpi_soc_bounding_box_st *soc, int pix_clk_100hz, int bpp, int seg_size_kb) argument
|
H A D | dcn31_fpu.h | 53 int pix_clk_100hz, int bpp, int seg_size_kb);
|
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 7158 int clock, bpp = 0; local 7184 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7186 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
|
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v8_0.c | 816 fixed20_12 bpp; local 825 bpp.full = dfixed_const(wm->bytes_per_pixel); 827 bandwidth.full = dfixed_mul(src_width, bpp);
|