Searched refs:uint32_t (Results 476 - 500 of 3101) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table_helper.h44 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
55 uint32_t *ref_clk_src_id);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dprocesspptables.h48 uint32_t *vol_rep_time, uint32_t *bb_rep_time);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega12_smumgr.h31 uint32_t version;
32 uint32_t size;
/linux-master/drivers/misc/cb710/
H A Dsgbuf2.c25 static uint32_t sg_dwiter_read_buffer(struct sg_mapping_iter *miter)
28 uint32_t data;
54 static bool sg_dwiter_get_next_block(struct sg_mapping_iter *miter, uint32_t **ptr)
90 uint32_t cb710_sg_dwiter_read_next_block(struct sg_mapping_iter *miter)
92 uint32_t *ptr = NULL;
101 static void sg_dwiter_write_slow(struct sg_mapping_iter *miter, uint32_t data)
131 void cb710_sg_dwiter_write_next_block(struct sg_mapping_iter *miter, uint32_t data)
133 uint32_t *ptr = NULL;
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_osd_afbcd.h22 int (*fmt_to_blk_mode)(u64 modifier, uint32_t format);
23 bool (*supported_fmt)(u64 modifier, uint32_t format);
/linux-master/drivers/net/ethernet/intel/e1000e/
H A De1000e_trace.h22 TP_PROTO(uint32_t reg),
24 TP_STRUCT__entry(__field(uint32_t, reg)),
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h215 uint32_t WB_ENABLE;
216 uint32_t WB_EC_CONFIG;
217 uint32_t CNV_MODE;
218 uint32_t WB_SOFT_RESET;
219 uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
220 uint32_t MCIF_WB_BUF_PITCH;
221 uint32_t MCIF_WB_ARBITRATION_CONTROL;
222 uint32_t MCIF_WB_SCLK_CHANGE;
223 uint32_t MCIF_WB_BUF_1_ADDR_Y;
224 uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSE
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H A Ddcn10_stream_encoder.h106 uint32_t AFMT_CNTL;
107 uint32_t AFMT_AVI_INFO0;
108 uint32_t AFMT_AVI_INFO1;
109 uint32_t AFMT_AVI_INFO2;
110 uint32_t AFMT_AVI_INFO3;
111 uint32_t AFMT_GENERIC_0;
112 uint32_t AFMT_GENERIC_1;
113 uint32_t AFMT_GENERIC_2;
114 uint32_t AFMT_GENERIC_3;
115 uint32_t AFMT_GENERIC_
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/linux-master/drivers/gpu/drm/amd/include/
H A Damd_pcie_helpers.h28 static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
36 static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
45 static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
48 uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
50 uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
76 static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
/linux-master/arch/arm/include/asm/
H A Dstring.h35 extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t);
36 static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n)
42 extern void *__memset64(uint64_t *, uint32_t low, __kernel_size_t, uint32_t hi);
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.h203 DMCU_REG_FIELD_LIST(uint32_t);
207 uint32_t DMCU_CTRL;
208 uint32_t DMCU_STATUS;
209 uint32_t DMCU_RAM_ACCESS_CTRL;
210 uint32_t DCI_MEM_PWR_STATUS;
211 uint32_t DMU_MEM_PWR_CNTL;
212 uint32_t DMCU_IRAM_WR_CTRL;
213 uint32_t DMCU_IRAM_WR_DATA;
215 uint32_t MASTER_COMM_DATA_REG1;
216 uint32_t MASTER_COMM_DATA_REG
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/linux-master/include/linux/
H A Dxz.h194 XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max);
276 uint32_t dict_size);
293 uint32_t comp_size, uint32_t uncomp_size,
368 XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc);
/linux-master/include/keys/
H A Dtrusted-type.h38 uint32_t keyhandle;
40 uint32_t blobauth_len;
42 uint32_t pcrinfo_len;
45 uint32_t hash;
46 uint32_t policydigest_len;
48 uint32_t policyhandle;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_apg.h40 uint32_t APG_CONTROL;
41 uint32_t APG_CONTROL2;
42 uint32_t APG_MEM_PWR;
43 uint32_t APG_DBG_GEN_CONTROL;
68 APG_DCN31_REG_FIELD_LIST(uint32_t);
105 uint32_t inst,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras_eeprom.h47 uint32_t header;
48 uint32_t version;
49 uint32_t first_rec_offset;
50 uint32_t tbl_size;
51 uint32_t checksum;
145 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control);
H A Datom.h121 u32 reg, uint32_t val); /* filled by driver */
122 uint32_t (*reg_read)(struct card_info *info, uint32_t reg); /* filled by driver */
124 u32 reg, uint32_t val); /* filled by driver */
125 uint32_t (*mc_read)(struct card_info *info, uint32_t reg); /* filled by driver */
127 u32 reg, uint32_t val); /* filled by driver */
128 uint32_t (*pll_read)(struct card_info *info, uint32_t reg); /* filled by driver */
135 uint32_t cmd_tabl
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhpd_regs.h65 uint32_t int_status;
66 uint32_t toggle_filt_cntl;
71 uint32_t DC_HPD_SENSE_DELAYED;
72 uint32_t DC_HPD_SENSE;
74 uint32_t DC_HPD_CONNECT_INT_DELAY;
75 uint32_t DC_HPD_DISCONNECT_INT_DELAY;
/linux-master/drivers/scsi/qla4xxx/
H A Dql4_def.h274 uint32_t mbox_cmd;
276 uint32_t pid;
283 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
300 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
306 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
307 struct ddb_entry *ddb_entry, uint32_t state);
321 uint32_t default_time2wait; /* Default Min time between
377 uint32_t data_size;
381 uint32_t status;
382 uint32_t pi
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H A Dql4_fw.h199 static inline uint32_t set_rmask(uint32_t val)
205 static inline uint32_t clr_rmask(uint32_t val)
277 uint32_t Asuint32_t;
311 uint32_t block_size;
312 uint32_t alt_block_size;
313 uint32_t flash_size;
314 uint32_t wrt_enable_data;
355 uint32_t cod
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/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h77 uint32_t dmdata_size;
85 uint32_t dmdata_qos_level;
89 uint32_t dmdata_dl_delta;
91 uint32_t *dmdata_sw_data;
128 uint32_t mst_stream_bw; // new mst bandwidth in kbps
133 uint32_t scaling:1;
134 uint32_t out_tf:1;
135 uint32_t out_csc:1;
136 uint32_t abm_level:1;
137 uint32_t dpms_of
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/linux-master/arch/parisc/kernel/
H A Dperf.c181 static int perf_config(uint32_t *image_ptr);
189 static int perf_stop_counters(uint32_t *raddr);
190 static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
191 static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
192 static int perf_rdr_clear(uint32_t rdr_num);
194 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
197 extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
198 extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
199 extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
200 extern void perf_rdr_shift_out_U (uint32_t rdr_nu
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/linux-master/include/xen/interface/
H A Dxen.h490 uint32_t version;
491 uint32_t pad0;
500 uint32_t tsc_to_system_mul;
585 uint32_t wc_sec_hi;
625 uint32_t flags; /* SIF_xxx flags. */
627 uint32_t store_evtchn; /* Event channel for store communication. */
631 uint32_t evtchn; /* Event channel for console page. */
634 uint32_t info_off; /* Offset of console_info struct. */
635 uint32_t info_size; /* Size of console_info struct from start.*/
675 uint32_t mod_star
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/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_mode.h122 uint32_t mask_clk_reg;
123 uint32_t mask_data_reg;
124 uint32_t a_clk_reg;
125 uint32_t a_data_reg;
126 uint32_t en_clk_reg;
127 uint32_t en_data_reg;
128 uint32_t y_clk_reg;
129 uint32_t y_data_reg;
130 uint32_t mask_clk_mask;
131 uint32_t mask_data_mas
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/linux-master/fs/udf/
H A Dpartition.c25 uint32_t udf_get_pblock(struct super_block *sb, uint32_t block,
26 uint16_t partition, uint32_t offset)
42 uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block,
43 uint16_t partition, uint32_t offset)
46 uint32_t newblock;
47 uint32_t index;
48 uint32_t loc;
69 index = (sb->s_blocksize - vdata->s_start_offset) / sizeof(uint32_t);
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v11_0_7_pptable.h137 uint32_t feature_count; //Total number of supported features
138 uint32_t setting_count; //Total number of supported settings
140 uint32_t max[SMU_11_0_7_MAX_ODSETTING]; //default maximum settings
141 uint32_t min[SMU_11_0_7_MAX_ODSETTING]; //default minimum settings
167 uint32_t count; //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT
168 uint32_t max[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
169 uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
177 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base
178 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base
180 uint32_t platform_cap
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