scsi/qla4xxx/ql4_def.h

274 	uint32_t mbox_cmd;
276 	uint32_t pid;
283         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
300 	uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
306 	int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
307 			  struct ddb_entry *ddb_entry, uint32_t state);
321 	uint32_t default_time2wait;	  /* Default Min time between
377 			uint32_t data_size;
381 			uint32_t status;
382 			uint32_t pid;
383 			uint32_t data_size;
391 	uint32_t flash_conf_off;
392 	uint32_t flash_data_off;
394 	uint32_t fdt_wrt_disable;
395 	uint32_t fdt_erase_cmd;
396 	uint32_t fdt_block_size;
397 	uint32_t fdt_unprotect_sec_cmd;
398 	uint32_t fdt_protect_sec_cmd;
400 	uint32_t flt_region_flt;
401 	uint32_t flt_region_fdt;
402 	uint32_t flt_region_boot;
403 	uint32_t flt_region_bootload;
404 	uint32_t flt_region_fw;
406 	uint32_t flt_iscsi_param;
407 	uint32_t flt_region_chap;
408 	uint32_t flt_chap_size;
409 	uint32_t flt_region_ddb;
410 	uint32_t flt_ddb_size;
414 	uint32_t int_vec_bit;
415 	uint32_t tgt_status_reg;
416 	uint32_t tgt_mask_reg;
417 	uint32_t pci_int_reg;
434 	void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
443 	uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
444 	void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
445 	int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
446 	int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
450 	void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
455 	uint32_t size;
456 	uint32_t size_cmask_02;
457 	uint32_t size_cmask_04;
458 	uint32_t size_cmask_08;
459 	uint32_t size_cmask_10;
460 	uint32_t size_cmask_FF;
461 	uint32_t version;
473 	uint32_t ipv6_options;
474 	uint32_t ipv6_addl_options;
502 	uint32_t ipv6_nd_reach_time;
503 	uint32_t ipv6_nd_rexmit_timer;
504 	uint32_t ipv6_nd_stale_timeout;
506 	uint32_t ipv6_gw_advrt_mtu;
603 	uint32_t tot_ddbs;
627 	uint32_t eeprom_cmd_data;
637 	uint32_t bytes_xfered;
638 	uint32_t spurious_int_count;
639 	uint32_t aborted_io_count;
640 	uint32_t io_timeout_count;
641 	uint32_t mailbox_timeout_count;
642 	uint32_t seconds_since_last_intr;
643 	uint32_t seconds_since_last_heartbeat;
644 	uint32_t mac_index;
648 	uint32_t firmware_version[2];
649 	uint32_t patch_number;
650 	uint32_t build_number;
651 	uint32_t board_id;
665 	uint32_t firmware_state;
666 	uint32_t addl_fw_state;
674 	uint32_t timer_active;
678 	uint32_t retry_reset_ha_cnt;
679 	uint32_t isp_reset_timer;	/* reset test timer */
680 	uint32_t nic_reset_timer;	/* simulated nic reset test timer */
723 	volatile uint32_t mbox_status[MBOX_REG_COUNT];
741 	uint32_t crb_win;
742 	uint32_t curr_window;
743 	uint32_t ddr_mn_window;
755 	uint32_t fw_heartbeat_counter;
760 	uint32_t nx_dev_init_timeout;
761 	uint32_t nx_reset_timeout;
763 	uint32_t fw_dump_size;
764 	uint32_t fw_dump_capture_mask;
766 	uint32_t fw_dump_tmplt_size;
767 	uint32_t fw_dump_skip_size;
778 	uint32_t fw_uptime_secs;  /* seconds elapsed since fw bootup */
779 	uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
782 	uint32_t flash_state;
815 	uint32_t mrb_index;
817 	uint32_t *reg_tbl;
822 	uint32_t pf_bit;
838 	uint32_t req_len;
841 	uint32_t resp_len;
1055 				      const uint32_t crb_reg)
1061 				       const uint32_t crb_reg,
1062 				       const uint32_t value)