1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22#ifndef SMU_11_0_7_PPTABLE_H 23#define SMU_11_0_7_PPTABLE_H 24 25#pragma pack(push, 1) 26 27#define SMU_11_0_7_TABLE_FORMAT_REVISION 15 28 29//// POWERPLAYTABLE::ulPlatformCaps 30#define SMU_11_0_7_PP_PLATFORM_CAP_POWERPLAY 0x1 // This cap indicates whether CCC need to show Powerplay page. 31#define SMU_11_0_7_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS. 32#define SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly. 33#define SMU_11_0_7_PP_PLATFORM_CAP_BACO 0x8 // This cap indicates whether board supports the BACO circuitry. 34#define SMU_11_0_7_PP_PLATFORM_CAP_MACO 0x10 // This cap indicates whether board supports the MACO circuitry. 35#define SMU_11_0_7_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 // This cap indicates whether board supports the Shadow Pstate. 36 37// SMU_11_0_7_PP_THERMALCONTROLLER - Thermal Controller Type 38#define SMU_11_0_7_PP_THERMALCONTROLLER_NONE 0 39#define SMU_11_0_7_PP_THERMALCONTROLLER_SIENNA_CICHLID 28 40 41#define SMU_11_0_7_PP_OVERDRIVE_VERSION 0x81 // OverDrive 8 Table Version 0.2 42#define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 43 44enum SMU_11_0_7_ODFEATURE_CAP { 45 SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0, 46 SMU_11_0_7_ODCAP_GFXCLK_CURVE, 47 SMU_11_0_7_ODCAP_UCLK_LIMITS, 48 SMU_11_0_7_ODCAP_POWER_LIMIT, 49 SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, 50 SMU_11_0_7_ODCAP_FAN_SPEED_MIN, 51 SMU_11_0_7_ODCAP_TEMPERATURE_FAN, 52 SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, 53 SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, 54 SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, 55 SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, 56 SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, 57 SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, 58 SMU_11_0_7_ODCAP_FAN_CURVE, 59 SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, 60 SMU_11_0_7_ODCAP_POWER_MODE, 61 SMU_11_0_7_ODCAP_COUNT, 62}; 63 64enum SMU_11_0_7_ODFEATURE_ID { 65 SMU_11_0_7_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_11_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature 66 SMU_11_0_7_ODFEATURE_GFXCLK_CURVE = 1 << SMU_11_0_7_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature 67 SMU_11_0_7_ODFEATURE_UCLK_LIMITS = 1 << SMU_11_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature 68 SMU_11_0_7_ODFEATURE_POWER_LIMIT = 1 << SMU_11_0_7_ODCAP_POWER_LIMIT, //Power Limit feature 69 SMU_11_0_7_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature 70 SMU_11_0_7_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_11_0_7_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature 71 SMU_11_0_7_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature 72 SMU_11_0_7_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature 73 SMU_11_0_7_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature 74 SMU_11_0_7_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature 75 SMU_11_0_7_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature 76 SMU_11_0_7_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature 77 SMU_11_0_7_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature 78 SMU_11_0_7_ODFEATURE_FAN_CURVE = 1 << SMU_11_0_7_ODCAP_FAN_CURVE, //Fan Curve feature 79 SMU_11_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature 80 SMU_11_0_7_ODFEATURE_POWER_MODE = 1 << SMU_11_0_7_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature 81 SMU_11_0_7_ODFEATURE_COUNT = 16, 82}; 83 84#define SMU_11_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features 85 86enum SMU_11_0_7_ODSETTING_ID { 87 SMU_11_0_7_ODSETTING_GFXCLKFMAX = 0, 88 SMU_11_0_7_ODSETTING_GFXCLKFMIN, 89 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_A, 90 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_B, 91 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_C, 92 SMU_11_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMIN, 93 SMU_11_0_7_ODSETTING_UCLKFMIN, 94 SMU_11_0_7_ODSETTING_UCLKFMAX, 95 SMU_11_0_7_ODSETTING_POWERPERCENTAGE, 96 SMU_11_0_7_ODSETTING_FANRPMMIN, 97 SMU_11_0_7_ODSETTING_FANRPMACOUSTICLIMIT, 98 SMU_11_0_7_ODSETTING_FANTARGETTEMPERATURE, 99 SMU_11_0_7_ODSETTING_OPERATINGTEMPMAX, 100 SMU_11_0_7_ODSETTING_ACTIMING, 101 SMU_11_0_7_ODSETTING_FAN_ZERO_RPM_CONTROL, 102 SMU_11_0_7_ODSETTING_AUTOUVENGINE, 103 SMU_11_0_7_ODSETTING_AUTOOCENGINE, 104 SMU_11_0_7_ODSETTING_AUTOOCMEMORY, 105 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1, 106 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_1, 107 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2, 108 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_2, 109 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3, 110 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_3, 111 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4, 112 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_4, 113 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_5, 114 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_5, 115 SMU_11_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT, 116 SMU_11_0_7_ODSETTING_POWER_MODE, 117 SMU_11_0_7_ODSETTING_COUNT, 118}; 119#define SMU_11_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings 120 121enum SMU_11_0_7_PWRMODE_SETTING { 122 SMU_11_0_7_PMSETTING_POWER_LIMIT_QUIET = 0, 123 SMU_11_0_7_PMSETTING_POWER_LIMIT_BALANCE, 124 SMU_11_0_7_PMSETTING_POWER_LIMIT_TURBO, 125 SMU_11_0_7_PMSETTING_POWER_LIMIT_RAGE, 126 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_QUIET, 127 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_BALANCE, 128 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_TURBO, 129 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_RAGE, 130}; 131#define SMU_11_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings 132 133struct smu_11_0_7_overdrive_table 134{ 135 uint8_t revision; //Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION 136 uint8_t reserve[3]; //Zero filled field reserved for future use 137 uint32_t feature_count; //Total number of supported features 138 uint32_t setting_count; //Total number of supported settings 139 uint8_t cap[SMU_11_0_7_MAX_ODFEATURE]; //OD feature support flags 140 uint32_t max[SMU_11_0_7_MAX_ODSETTING]; //default maximum settings 141 uint32_t min[SMU_11_0_7_MAX_ODSETTING]; //default minimum settings 142 int16_t pm_setting[SMU_11_0_7_MAX_PMSETTING]; //Optimized power mode feature settings 143}; 144 145enum SMU_11_0_7_PPCLOCK_ID { 146 SMU_11_0_7_PPCLOCK_GFXCLK = 0, 147 SMU_11_0_7_PPCLOCK_SOCCLK, 148 SMU_11_0_7_PPCLOCK_UCLK, 149 SMU_11_0_7_PPCLOCK_FCLK, 150 SMU_11_0_7_PPCLOCK_DCLK_0, 151 SMU_11_0_7_PPCLOCK_VCLK_0, 152 SMU_11_0_7_PPCLOCK_DCLK_1, 153 SMU_11_0_7_PPCLOCK_VCLK_1, 154 SMU_11_0_7_PPCLOCK_DCEFCLK, 155 SMU_11_0_7_PPCLOCK_DISPCLK, 156 SMU_11_0_7_PPCLOCK_PIXCLK, 157 SMU_11_0_7_PPCLOCK_PHYCLK, 158 SMU_11_0_7_PPCLOCK_DTBCLK, 159 SMU_11_0_7_PPCLOCK_COUNT, 160}; 161#define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks 162 163struct smu_11_0_7_power_saving_clock_table 164{ 165 uint8_t revision; //Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 166 uint8_t reserve[3]; //Zero filled field reserved for future use 167 uint32_t count; //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT 168 uint32_t max[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz 169 uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz 170}; 171 172struct smu_11_0_7_powerplay_table 173{ 174 struct atom_common_table_header header; //For sienna_cichlid, header.format_revision = 15, header.content_revision = 0 175 uint8_t table_revision; //For sienna_cichlid, table_revision = 2 176 uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size 177 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base 178 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base 179 uint16_t format_id; //PPGen use only: PPTable for different ASICs. For sienna_cichlid this should be 0x80 180 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps 181 182 uint8_t thermal_controller_type; //one of SMU_11_0_7_PP_THERMALCONTROLLER 183 184 uint16_t small_power_limit1; 185 uint16_t small_power_limit2; 186 uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit. 187 uint16_t software_shutdown_temp; 188 189 uint16_t reserve[8]; //Zero filled field reserved for future use 190 191 struct smu_11_0_7_power_saving_clock_table power_saving_clock; 192 struct smu_11_0_7_overdrive_table overdrive_table; 193 194 PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h 195}; 196 197#pragma pack(pop) 198 199#endif 200