drm/radeon/radeon_mode.h

122 	uint32_t mask_clk_reg;
123 	uint32_t mask_data_reg;
124 	uint32_t a_clk_reg;
125 	uint32_t a_data_reg;
126 	uint32_t en_clk_reg;
127 	uint32_t en_data_reg;
128 	uint32_t y_clk_reg;
129 	uint32_t y_data_reg;
130 	uint32_t mask_clk_mask;
131 	uint32_t mask_data_mask;
132 	uint32_t a_clk_mask;
133 	uint32_t a_data_mask;
134 	uint32_t en_clk_mask;
135 	uint32_t en_data_mask;
136 	uint32_t y_clk_mask;
137 	uint32_t y_data_mask;
141     uint32_t freq;
142     uint32_t value;
166 	uint32_t reference_freq;
169 	uint32_t reference_div;
170 	uint32_t post_div;
173 	uint32_t pll_in_min;
174 	uint32_t pll_in_max;
175 	uint32_t pll_out_min;
176 	uint32_t pll_out_max;
177 	uint32_t lcd_pll_out_min;
178 	uint32_t lcd_pll_out_max;
179 	uint32_t best_vco;
182 	uint32_t min_ref_div;
183 	uint32_t max_ref_div;
184 	uint32_t min_post_div;
185 	uint32_t max_post_div;
186 	uint32_t min_feedback_div;
187 	uint32_t max_feedback_div;
188 	uint32_t min_frac_feedback_div;
189 	uint32_t max_frac_feedback_div;
192 	uint32_t flags;
195 	uint32_t id;
274 	uint32_t active_encoders;
290 	uint32_t tv_uv_adr;
291 	uint32_t timing_cntl;
292 	uint32_t hrestart;
293 	uint32_t vrestart;
294 	uint32_t frestart;
324 	uint32_t crtc_offset;
335 	uint32_t legacy_display_base_addr;
368 	uint32_t ps2_pdac_adj;
381 	uint32_t lvds_gen_cntl;
391 	uint32_t ps2_tvdac_adj;
392 	uint32_t ntsc_tvdac_adj;
393 	uint32_t pal_tvdac_adj;
423 	uint32_t lcd_misc;
425 	uint32_t lcd_ss_id;
442 	uint32_t encoder_enum;
443 	uint32_t encoder_id;
444 	uint32_t devices;
445 	uint32_t active_device;
446 	uint32_t flags;
447 	uint32_t pixel_clock;
450 	uint32_t underscan_hborder;
451 	uint32_t underscan_vborder;
460 	uint32_t offset;
464 	uint32_t igp_lane_info;
516 	uint32_t connector_id;
517 	uint32_t devices;
655 			  uint32_t connector_id,
656 			  uint32_t supported_device,
659 			  uint32_t igp_lane_info,
665 			    uint32_t connector_id,
666 			    uint32_t supported_device,
671 extern uint32_t
672 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
774 				      uint32_t *dot_clock_p,
775 				      uint32_t *fb_div_p,
776 				      uint32_t *frac_fb_div_p,
777 				      uint32_t *ref_div_p,
778 				      uint32_t *post_div_p);
827 				   uint32_t handle,
828 				   uint32_t width,
829 				   uint32_t height,
920 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
921 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
923 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
924 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
926 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
927 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);