Searched refs:uint32_t (Results 426 - 450 of 3101) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v8_7.c35 const uint32_t
43 static inline uint32_t get_umc_v8_7_reg_offset(struct amdgpu_device *adev,
44 uint32_t umc_inst,
45 uint32_t ch_inst)
51 uint32_t umc_inst, uint32_t ch_inst,
55 uint32_t eccinfo_table_idx;
70 uint32_t umc_inst, uint32_t ch_inst,
74 uint32_t eccinfo_table_id
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H A Damdgpu_csa.h30 uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
33 u32 domain, uint32_t size);
36 uint64_t csa_addr, uint32_t size);
H A Damdgpu_sdma.h56 uint32_t fw_version;
57 uint32_t feature_version;
62 uint32_t aid_id;
108 uint32_t sdma_mask;
110 uint32_t srbm_soft_reset;
122 uint32_t copy_max_bytes;
134 uint32_t byte_count,
135 uint32_t copy_flags);
138 uint32_t fill_max_bytes;
146 uint32_t src_dat
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H A Damdgpu_amdkfd_gfx_v8.c42 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
43 uint32_t queue, uint32_t vmid)
45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
57 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
58 uint32_t queue_id)
60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
71 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmi
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_opp.h34 uint32_t OPP_TOP_CLK_CONTROL
55 OPP_DCN35_REG_FIELD_LIST(uint32_t);
60 uint32_t inst,
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_migrate.h43 int svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,
45 struct mm_struct *mm, uint32_t trigger);
49 uint32_t trigger, struct page *fault_page);
H A Dkfd_mqd_manager.c85 mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
99 const uint32_t *cu_mask, uint32_t cu_mask_count,
100 uint32_t *se_mask, uint32_t inst)
104 uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
106 uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
108 uint32_t cu_active_per_node;
207 uint32_t pipe_id, uint32_t queue_i
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_services.c55 void dm_trace_smu_msg(uint32_t msg_id, uint32_t param_in, struct dc_context *ctx)
59 void dm_trace_smu_delay(uint32_t delay, struct dc_context *ctx)
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dlink_encoder.h57 uint32_t IS_HBR2_CAPABLE:1;
58 uint32_t IS_HBR3_CAPABLE:1;
59 uint32_t IS_TPS3_CAPABLE:1;
60 uint32_t IS_TPS4_CAPABLE:1;
61 uint32_t HDMI_6GB_EN:1;
62 uint32_t IS_DP2_CAPABLE:1;
63 uint32_t IS_UHBR10_CAPABLE:1;
64 uint32_t IS_UHBR13_5_CAPABLE:1;
65 uint32_t IS_UHBR20_CAPABLE:1;
66 uint32_t DP_IS_USB_
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H A Dhubp.h87 uint32_t DCSURF_SURFACE_CONTROL;
88 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
89 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
90 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
91 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
92 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
93 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
94 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
95 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
96 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIG
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h221 uint32_t Spare[8];
222 uint32_t MmHubPadding[8]; // SMU internal use
226 uint32_t a; // store in IEEE float format in this variable
227 uint32_t b; // store in IEEE float format in this variable
228 uint32_t c; // store in IEEE float format in this variable
232 uint32_t m; // store in IEEE float format in this variable
233 uint32_t b; // store in IEEE float format in this variable
274 uint32_t Version;
277 uint32_t FeaturesToRun[2];
302 uint32_t FidTableFcl
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H A Dsmu13_driver_if_v13_0_4.h34 uint32_t numFractionalBits;
75 uint32_t MmHubPadding[7]; // SMU internal use
113 uint32_t FClk;
114 uint32_t MemClk;
115 uint32_t Voltage;
123 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
124 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
125 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
126 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
127 uint32_t VClock
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/linux-master/drivers/scsi/megaraid/
H A Dmegaraid_ioctl.h121 uint32_t opcode;
122 uint32_t adapno;
124 uint32_t xferlen;
125 uint32_t data_dir;
131 uint32_t user_data_len;
134 uint32_t pad_for_64bit_align;
190 uint32_t unique_id;
191 uint32_t host_no;
222 uint32_t uid;
240 uint32_t buf_siz
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/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_common.c29 static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
31 uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
59 static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
61 uint32_t bios_enum_id =
95 static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)
100 static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
102 uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
173 uint32_t bios_object_id)
175 uint32_t bios_connector_i
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.h89 uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
90 uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
91 uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
92 uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
93 uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
94 uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
95 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
96 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
97 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
98 uint32_t MPCC_OGAM_RAMA_END_CNTL1_
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h47 uint32_t padding[7];
52 uint32_t **pptable_info_array,
53 const uint32_t *pptable_array,
54 uint32_t power_saving_clock_count);
58 uint32_t **pptable_info_array,
59 const uint32_t *pptable_array,
60 uint32_t od_setting_count);
63 uint32_t index,
64 uint32_t value, uint32_t mas
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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.h102 uint32_t OTG_GLOBAL_CONTROL1;
103 uint32_t OTG_GLOBAL_CONTROL2;
104 uint32_t OTG_VERT_SYNC_CONTROL;
105 uint32_t OTG_MASTER_UPDATE_MODE;
106 uint32_t OTG_GSL_CONTROL;
107 uint32_t OTG_VSTARTUP_PARAM;
108 uint32_t OTG_VUPDATE_PARAM;
109 uint32_t OTG_VREADY_PARAM;
110 uint32_t OTG_BLANK_CONTROL;
111 uint32_t OTG_MASTER_UPDATE_LOC
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/linux-master/drivers/scsi/qla2xxx/
H A Dqla_gbl.h35 extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *);
36 extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *);
37 extern int qla81xx_load_risc(scsi_qla_host_t *, uint32_t *);
70 extern int qla2x00_async_tm_cmd(fc_port_t *, uint32_t, uint64_t, uint32_t);
83 extern int __qla83xx_set_idc_control(scsi_qla_host_t *, uint32_t);
84 extern int __qla83xx_get_idc_control(scsi_qla_host_t *, uint32_t *);
127 extern bool qla24xx_risc_firmware_invalid(uint32_t *);
305 extern uint32_t qla2xxx_get_next_handle(struct req_que *req);
312 extern int qla2x00_start_bidir(srb_t *, struct scsi_qla_host *, uint32_t);
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/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_compressor.h34 uint32_t dcp_offset;
35 uint32_t dmif_offset;
59 uint32_t fbc_trigger);
66 uint32_t *fbc_mapped_crtc_id);
/linux-master/drivers/media/pci/cobalt/
H A Dm00235_fdma_packer_memmap_package.h15 uint32_t control; /* Reg 0x0000, Default=0x0 */
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-scratch.h75 static inline uint32_t cvmx_scratch_read32(uint64_t address)
77 return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
124 *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
125 (uint32_t) value;
/linux-master/arch/powerpc/boot/
H A Dxz_config.h14 static inline uint32_t swab32p(void *p)
16 uint32_t *q = p;
22 #define get_le32(p) (*((uint32_t *) (p)))
37 static inline uint32_t get_unaligned_be32(const void *p)
/linux-master/arch/x86/include/asm/
H A Dolpc.h11 uint32_t boardrev;
28 static inline uint32_t olpc_board(uint8_t id)
33 static inline uint32_t olpc_board_pre(uint8_t id)
60 static inline int olpc_board_at_least(uint32_t rev)
/linux-master/drivers/staging/media/atomisp/pci/runtime/event/interface/
H A Dia_css_event.h25 uint32_t *out);
/linux-master/include/linux/platform_data/
H A Dmtd-davinci.h43 uint32_t mask_ale;
44 uint32_t mask_cle;
54 uint32_t core_chipsel;
57 uint32_t mask_chipsel;

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