1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26#include "amdgpu_ras.h"
27
28/* max number of IP instances */
29#define AMDGPU_MAX_SDMA_INSTANCES		16
30
31enum amdgpu_sdma_irq {
32	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
33	AMDGPU_SDMA_IRQ_INSTANCE1,
34	AMDGPU_SDMA_IRQ_INSTANCE2,
35	AMDGPU_SDMA_IRQ_INSTANCE3,
36	AMDGPU_SDMA_IRQ_INSTANCE4,
37	AMDGPU_SDMA_IRQ_INSTANCE5,
38	AMDGPU_SDMA_IRQ_INSTANCE6,
39	AMDGPU_SDMA_IRQ_INSTANCE7,
40	AMDGPU_SDMA_IRQ_INSTANCE8,
41	AMDGPU_SDMA_IRQ_INSTANCE9,
42	AMDGPU_SDMA_IRQ_INSTANCE10,
43	AMDGPU_SDMA_IRQ_INSTANCE11,
44	AMDGPU_SDMA_IRQ_INSTANCE12,
45	AMDGPU_SDMA_IRQ_INSTANCE13,
46	AMDGPU_SDMA_IRQ_INSTANCE14,
47	AMDGPU_SDMA_IRQ_INSTANCE15,
48	AMDGPU_SDMA_IRQ_LAST
49};
50
51#define NUM_SDMA(x) hweight32(x)
52
53struct amdgpu_sdma_instance {
54	/* SDMA firmware */
55	const struct firmware	*fw;
56	uint32_t		fw_version;
57	uint32_t		feature_version;
58
59	struct amdgpu_ring	ring;
60	struct amdgpu_ring	page;
61	bool			burst_nop;
62	uint32_t		aid_id;
63};
64
65enum amdgpu_sdma_ras_memory_id {
66	AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
67	AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
68	AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
69	AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
70	AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
71	AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
72	AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
73	AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
74	AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
75	AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
76	AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
77	AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
78	AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
79	AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
80	AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
81	AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
82	AMDGPU_SDMA_UCODE_BUF = 17,
83	AMDGPU_SDMA_RB_CMD_BUF = 18,
84	AMDGPU_SDMA_IB_CMD_BUF = 19,
85	AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
86	AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
87	AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
88	AMDGPU_SDMA_DATA_LUT_FIFO = 23,
89	AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
90	AMDGPU_SDMA_MEMORY_BLOCK_LAST,
91};
92
93struct amdgpu_sdma_ras {
94	struct amdgpu_ras_block_object ras_block;
95};
96
97struct amdgpu_sdma {
98	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
99	struct amdgpu_irq_src	trap_irq;
100	struct amdgpu_irq_src	illegal_inst_irq;
101	struct amdgpu_irq_src	ecc_irq;
102	struct amdgpu_irq_src	vm_hole_irq;
103	struct amdgpu_irq_src	doorbell_invalid_irq;
104	struct amdgpu_irq_src	pool_timeout_irq;
105	struct amdgpu_irq_src	srbm_write_irq;
106
107	int			num_instances;
108	uint32_t 		sdma_mask;
109	int			num_inst_per_aid;
110	uint32_t                    srbm_soft_reset;
111	bool			has_page_queue;
112	struct ras_common_if	*ras_if;
113	struct amdgpu_sdma_ras	*ras;
114};
115
116/*
117 * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
118 * But currently, we use sdma to move data.
119 */
120struct amdgpu_buffer_funcs {
121	/* maximum bytes in a single operation */
122	uint32_t	copy_max_bytes;
123
124	/* number of dw to reserve per operation */
125	unsigned	copy_num_dw;
126
127	/* used for buffer migration */
128	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
129				 /* src addr in bytes */
130				 uint64_t src_offset,
131				 /* dst addr in bytes */
132				 uint64_t dst_offset,
133				 /* number of byte to transfer */
134				 uint32_t byte_count,
135				 bool tmz);
136
137	/* maximum bytes in a single operation */
138	uint32_t	fill_max_bytes;
139
140	/* number of dw to reserve per operation */
141	unsigned	fill_num_dw;
142
143	/* used for buffer clearing */
144	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
145				 /* value to write to memory */
146				 uint32_t src_data,
147				 /* dst addr in bytes */
148				 uint64_t dst_offset,
149				 /* number of byte to fill */
150				 uint32_t byte_count);
151};
152
153#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
154#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
155
156struct amdgpu_sdma_instance *
157amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
158int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
159uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
160int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
161			      struct ras_common_if *ras_block);
162int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
163		void *err_data,
164		struct amdgpu_iv_entry *entry);
165int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
166				      struct amdgpu_irq_src *source,
167				      struct amdgpu_iv_entry *entry);
168int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
169			       bool duplicate);
170void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
171        bool duplicate);
172int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
173
174#endif
175