/haiku/src/add-ons/kernel/drivers/audio/emuxki/ |
H A D | emuxkireg.h | 55 #define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))
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/haiku/headers/private/graphics/radeon_hd/ |
H A D | si_reg.h | 762 #define SI_PACKET0(reg, n) ((PACKET_TYPE0 << 30) \ 763 | (((reg) >> 2) & 0xFFFF) \
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/ |
H A D | e1000_api.c | 1369 * @reg: 32bit register offset 1376 s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset, argument 1379 return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/ |
H A D | ar9300_power.c | 57 u_int32_t reg, val; local 65 reg = high32 ? AR_MCAST_FIL1 : AR_MCAST_FIL0; 68 val = OS_REG_READ(ah, reg); 76 OS_REG_WRITE(ah, reg, val);
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H A D | ar9300.h | 963 BB_powertx_rate9 reg 967 BB_powertx_rate9 reg 1068 BB_powertx_rate9 reg 1072 BB_powertx_rate9 reg 1164 POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1166 * BB_powertx_rate9 reg 1217 HAL_INT_MITIGATION reg, u_int32_t value); 1219 HAL_INT_MITIGATION reg); 1544 extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1545 extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_ [all...] |
H A D | ar9300_mci.c | 1364 u_int32_t reg; local 1366 reg = OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); 1367 return ((reg & ints) == ints);
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ |
H A D | ar5212_misc.c | 35 #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 304 uint32_t reg; local 321 reg = OS_REG_READ(ah, AR_STA_ID1); 323 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 325 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
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H A D | ar5212_reset.c | 85 uint32_t reg = V(r, 0); local 88 if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 89 OS_REG_WRITE(ah, reg, V(r, 1)); 368 /* Clear reg to alllow RX_CLEAR line debug */ 484 * Disable: reg val 2743 uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); local 2748 OS_REG_WRITE(ah, reg, 2755 reg += rt->info[i].shortPreamble << 2; 2756 OS_REG_WRITE(ah, reg,
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/haiku/src/add-ons/kernel/drivers/audio/ice1712/ |
H A D | multi.cpp | 341 uint8 reg; local 347 reg = read_mt_uint8(card, MT_SAMPLING_RATE_SELECT); 349 if (reg == 0x10)
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/haiku/src/add-ons/kernel/drivers/network/wlan/idualwifi7260/dev/pci/ |
H A D | if_iwmreg.h | 323 /* One-time-programmable memory general purpose reg */ 1663 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 4093 * reg change 6821 #define IWM_READ(sc, reg) \ 6822 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6824 #define IWM_WRITE(sc, reg, val) \ 6825 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6827 #define IWM_WRITE_1(sc, reg, val) \ 6828 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6830 #define IWM_SETBITS(sc, reg, mas [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/ |
H A D | if_nfe.c | 369 int error = 0, i, msic, phyloc, reg, rid; local 389 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 392 v = pci_read_config(dev, reg + 0x08, 2); 396 pci_write_config(dev, reg + 0x08, v, 2); 398 v = pci_read_config(dev, reg + 0x0c, 2); 401 width = pci_read_config(dev, reg + 0x12, 2); 621 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 1026 nfe_miibus_readreg(device_t dev, int phy, int reg) argument 1039 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1060 DPRINTFN(sc, 2, "mii read phy %d reg 1067 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/intel22x/dev/igc/ |
H A D | igc_i225.c | 865 u32 i, reg; local 870 reg = IGC_READ_REG(hw, IGC_EECD); 871 if (reg & IGC_EECD_FLUDONE_I225) {
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H A D | igc_defines.h | 637 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */ 1104 #define M88IGC_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1157 #define GG82563_REG(page, reg) \ 1158 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
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/haiku/src/add-ons/kernel/drivers/network/wlan/iaxwifi200/dev/pci/ |
H A D | if_iwxreg.h | 2499 * @write_ptr_reg: the addr of the reg of the write pointer 2500 * @wrap_count: the addr of the reg of the wrap_count 2501 * @base_shift: shift right of the base addr reg 2502 * @end_shift: shift right of the end addr reg 4527 * reg change 7888 #define IWX_READ(sc, reg) \ 7889 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 7891 #define IWX_WRITE(sc, reg, val) \ 7892 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7894 #define IWX_WRITE_1(sc, reg, va [all...] |
H A D | if_iwx.c | 1748 iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask, argument 1752 if ((IWX_READ(sc, reg) & mask) == (bits & mask)) { 1808 iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits, argument 1814 val = iwx_read_prph(sc, reg) & mask; 1816 iwx_write_prph(sc, reg, val); 1824 iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits) argument 1826 return iwx_set_bits_mask_prph(sc, reg, bits, ~0); 1830 iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits) argument 1832 return iwx_set_bits_mask_prph(sc, reg, 0, ~bits); 9564 printf("%s: 0x%08X | isr status reg\ 11012 pcireg_t reg, memtype; local 11498 pcireg_t reg; local [all...] |
/haiku/src/add-ons/kernel/busses/virtio/virtio_pci/ |
H A D | virtio_pci.cpp | 85 uint32 reg[8]; member in union:regs 91 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4); 103 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4);
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/haiku/src/add-ons/kernel/drivers/network/ether/broadcom570x/dev/bge/ |
H A D | if_bge.c | 1104 bge_miibus_readreg(device_t dev, int phy, int reg) argument 1123 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1138 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1139 phy, reg, val); 1158 bge_miibus_writereg(device_t dev, int phy, int reg, int val) argument 1166 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1180 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1201 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1202 phy, reg, va 3313 int capmask, error, reg, rid, trys; local 5965 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) argument [all...] |
/haiku/src/add-ons/kernel/bus_managers/firewire/ |
H A D | firewire.cpp | 1556 struct csrreg *reg; local 1565 reg = (struct csrreg *)&fwdev->csrrom[offset/sizeof(uint32_t)]; 1567 (uint32_t *)reg, dir->crc_len); 1581 if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_D) 1583 else if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_L) 1588 off = offset + reg[i].val * sizeof(uint32_t);
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/haiku/src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/ |
H A D | if_vr.c | 244 vr_miibus_readreg(device_t dev, int phy, int reg) argument 252 CSR_WRITE_1(sc, VR_MIIADDR, reg); 261 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 267 vr_miibus_writereg(device_t dev, int phy, int reg, int data) argument 275 CSR_WRITE_1(sc, VR_MIIADDR, reg); 286 reg);
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ |
H A D | ar5211_reset.c | 333 uint32_t reg = ar5211Common[i][0]; local 335 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000))) 336 OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | overlay.c | 26 uint16 reg; member in struct:__anon7 89 OUTREG( regs, std_gamma[i].reg,
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ |
H A D | ah_internal.h | 418 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 419 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 617 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 619 extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 853 u_int offset; /* reg offset */ 854 uint32_t val; /* reg value */
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/haiku/src/libs/compat/freebsd_wlan/net80211/ |
H A D | ieee80211_ioctl.c | 2185 struct ieee80211_regdomain_req *reg; local 2196 reg = (struct ieee80211_regdomain_req *) 2199 if (reg == NULL) { 2204 error = copyin(ireq->i_data, reg, IEEE80211_REGDOMAIN_SIZE(nchans)); 2207 if (reg->chaninfo.ic_nchans != nchans) { 2210 reg->chaninfo.ic_nchans, nchans); 2213 error = ieee80211_setregdomain(vap, reg); 2215 IEEE80211_FREE(reg, M_TEMP);
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/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/pci/ |
H A D | rtwn_pci_attach.c | 494 uint16_t reg, int mlen) 499 rtwn_pci_write_1(sc, reg++, buf[i]); 493 rtwn_pci_fw_write_block(struct rtwn_softc *sc, const uint8_t *buf, uint16_t reg, int mlen) argument
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/haiku/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/ |
H A D | mwlhal.c | 2237 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val) argument 2244 pCmd->Offset = htole16(reg); 2256 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val) argument 2263 pCmd->Offset = htole16(reg);
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