1/* 2 * Emuxki BeOS Driver for Creative Labs SBLive!/Audigy series 3 * 4 * Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr) 5 * 6 * Copyright (c) 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Yannick Montulet. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#ifndef _DEV_PCI_EMUXKIREG_H_ 42#define _DEV_PCI_EMUXKIREG_H_ 43 44/* 45 * Register values for Creative EMU10000. The register values have been 46 * taken from GPLed SBLive! header file published by Creative. The comments 47 * have been stripped to avoid GPL pollution in kernel. The Creative version 48 * including comments is available in Linux 2.4.* kernel as file 49 * drivers/sound/emu10k1/8010.h 50 */ 51 52// Audigy specific registers contain a 'A_' 53// Audigy(2) specific registers contain a 'A2_' 54 55#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg)) 56 57#define EMU_PTR 0x00 58#define EMU_PTR_CHNO_MASK 0x0000003f 59#define EMU_PTR_ADDR_MASK 0x07ff0000 60#define EMU_A_PTR_ADDR_MASK 0x0fff0000 61 62#define EMU_DATA 0x04 63 64#define EMU_IPR 0x08 65#define EMU_IPR_A_MIDITRANSBUFE2 0x10000000 66#define EMU_IPR_A_MIDIRECVBUFE2 0x08000000 67#define EMU_IPR_RATETRCHANGE 0x01000000 68#define EMU_IPR_FXDSP 0x00800000 69#define EMU_IPR_FORCEINT 0x00400000 70#define EMU_PCIERROR 0x00200000 71#define EMU_IPR_VOLINCR 0x00100000 72#define EMU_IPR_VOLDECR 0x00080000 73#define EMU_IPR_MUTE 0x00040000 74#define EMU_IPR_MICBUFFULL 0x00020000 75#define EMU_IPR_MICBUFHALFFULL 0x00010000 76#define EMU_IPR_ADCBUFFULL 0x00008000 77#define EMU_IPR_ADCBUFHALFFULL 0x00004000 78#define EMU_IPR_EFXBUFFULL 0x00002000 79#define EMU_IPR_EFXBUFHALFFULL 0x00001000 80#define EMU_IPR_GPSPDIFSTCHANGE 0x00000800 81#define EMU_IPR_CDROMSTCHANGE 0x00000400 82#define EMU_IPR_INTERVALTIMER 0x00000200 83#define EMU_IPR_MIDITRANSBUFE 0x00000100 84#define EMU_IPR_MIDIRECVBUFE 0x00000080 85#define EMU_IPR_CHANNELLOOP 0x00000040 86#define EMU_IPR_CHNOMASK 0x0000003f 87 88#define EMU_INTE 0x0c 89 90#define EMU_INTE_VSB_MASK 0xc0000000 91#define EMU_INTE_VSB_220 0x00000000 92#define EMU_INTE_VSB_240 0x40000000 93#define EMU_INTE_VSB_260 0x80000000 94#define EMU_INTE_VSB_280 0xc0000000 95 96#define EMU_INTE_VMPU_MASK 0x30000000 97#define EMU_INTE_VMPU_300 0x00000000 98#define EMU_INTE_VMPU_310 0x10000000 99#define EMU_INTE_VMPU_320 0x20000000 100#define EMU_INTE_VMPU_330 0x30000000 101#define EMU_INTE_MDMAENABLE 0x08000000 102#define EMU_INTE_SDMAENABLE 0x04000000 103#define EMU_INTE_MPICENABLE 0x02000000 104#define EMU_INTE_SPICENABLE 0x01000000 105#define EMU_INTE_VSBENABLE 0x00800000 106#define EMU_INTE_ADLIBENABLE 0x00400000 107#define EMU_INTE_MPUENABLE 0x00200000 108#define EMU_INTE_FORCEINT 0x00100000 109#define EMU_INTE_MRHANDENABLE 0x00080000 110#define EMU_INTE_SAMPLERATER 0x00002000 111#define EMU_INTE_FXDSPENABLE 0x00001000 112#define EMU_INTE_PCIERRENABLE 0x00000800 113#define EMU_INTE_VOLINCRENABLE 0x00000400 114#define EMU_INTE_VOLDECRENABLE 0x00000200 115#define EMU_INTE_MUTEENABLE 0x00000100 116#define EMU_INTE_MICBUFENABLE 0x00000080 117#define EMU_INTE_ADCBUFENABLE 0x00000040 118#define EMU_INTE_EFXBUFENABLE 0x00000020 119#define EMU_INTE_GPSPDIFENABLE 0x00000010 120#define EMU_INTE_CDSPDIFENABLE 0x00000008 121#define EMU_INTE_INTERTIMERENB 0x00000004 122#define EMU_INTE_MIDITXENABLE 0x00000002 123#define EMU_INTE_MIDIRXENABLE 0x00000001 124#define EMU_INTE_A_MIDITXENABLE2 0x00020000 125#define EMU_INTE_A_MIDIRXENABLE2 0x00010000 126 127#define EMU_WC 0x10 128#define EMU_WC_SAMPLECOUNTER_MASK 0x03FFFFC0 129#define EMU_WC_SAMPLECOUNTER EMU_MKSUBREG(20, 6, EMU_WC) 130#define EMU_WC_CURRENTCHANNEL 0x0000003F 131 132#define EMU_HCFG 0x14 133#define EMU_HCFG_LEGACYFUNC_MASK 0xe0000000 134#define EMU_HCFG_LEGACYFUNC_MPU 0x00000000 135#define EMU_HCFG_LEGACYFUNC_SB 0x40000000 136#define EMU_HCFG_LEGACYFUNC_AD 0x60000000 137#define EMU_HCFG_LEGACYFUNC_MPIC 0x80000000 138#define EMU_HCFG_LEGACYFUNC_MDMA 0xa0000000 139#define EMU_HCFG_LEGACYFUNC_SPCI 0xc0000000 140#define EMU_HCFG_LEGACYFUNC_SDMA 0xe0000000 141#define EMU_HCFG_IOCAPTUREADDR 0x1f000000 142#define EMU_HCFG_LEGACYWRITE 0x00800000 143#define EMU_HCFG_LEGACYWORD 0x00400000 144#define EMU_HCFG_LEGACYINT 0x00200000 145 146#define EMU_HCFG_CODECFMT_MASK 0x00070000 147#define EMU_HCFG_CODECFMT_AC97 0x00000000 148#define EMU_HCFG_CODECFMT_I2S 0x00010000 149#define EMU_HCFG_GPINPUT0 0x00004000 150#define EMU_HCFG_GPINPUT1 0x00002000 151#define EMU_HCFG_GPOUTPUT_MASK 0x00001c00 152#define EMU_HCFG_GPOUTPUT0 0x00001000 153#define EMU_HCFG_JOYENABLE 0x00000200 154#define EMU_HCFG_PHASETRACKENABLE 0x00000100 155#define EMU_HCFG_AC3ENABLE_MASK 0x000000e0 156#define EMU_HCFG_AC3ENABLE_ZVIDEO 0x00000080 157#define EMU_HCFG_AC3ENABLE_CDSPDIF 0x00000040 158#define EMU_HCFG_AC3ENABLE_GPSPDIF 0x00000020 159#define EMU_HCFG_AUTOMUTE 0x00000010 160#define EMU_HCFG_LOCKSOUNDCACHE 0x00000008 161#define EMU_HCFG_LOCKTANKCACHE_MASK 0x00000004 162#define EMU_HCFG_LOCKTANKCACHE EMU_MKSUBREG(1, 2, EMU_HCFG) 163#define EMU_HCFG_MUTEBUTTONENABLE 0x00000002 164#define EMU_HCFG_AUDIOENABLE 0x00000001 165 166#define EMU_MUDATA 0x18 167#define EMU_MUCMD 0x19 168#define EMU_MUCMD_RESET 0xff 169#define EMU_MUCMD_ENTERUARTMODE 0x3f 170 171#define EMU_MUSTAT EMU_MUCMD 172#define EMU_MUSTAT_IRDYN 0x80 173#define EMU_MUSTAT_ORDYN 0x40 174 175#define EMU_A_IOCFG 0x18 176#define EMU_A_GPINPUT_MASK 0xff00 177#define EMU_A_GPOUTPUT_MASK 0x00ff 178#define EMU_A_IOCFG_GPOUT0 0x0040 179#define EMU_A_IOCFG_GPOUT1 0x0004 180 181#define EMU_TIMER 0x1a 182#define EMU_TIMER_RATE_MASK 0x000003ff 183#define EMU_TIMER_RATE EMU_MKSUBREG(10, 0, EMU_TIMER) 184 185#define EMU_AC97DATA 0x1c 186#define EMU_AC97ADDR 0x1e 187#define EMU_AC97ADDR_RDY 0x80 188#define EMU_AC97ADDR_ADDR 0x7f 189 190#define EMU_A2_PTR 0x20 191#define EMU_A2_DATA 0x24 192#define EMU_A2_IPR2 0x28 193#define EMU_A2_INTE2 0x2c 194#define EMU_A2_HCFG2 0x34 195#define EMU_A2_IPR3 0x38 196#define EMU_A2_INTE3 0x3c 197 198#define EMU_A2_SRCSEL 0x60 199#define EMU_A2_SRCSEL_ENABLE_SPDIF 0x00000004 200#define EMU_A2_SRCSEL_ENABLE_SRCMULTI 0x00000010 201#define EMU_A2_SRCMULTI 0x6e 202#define EMU_A2_SRCMULTI_ENABLE_INPUT 0xff00ff00 203#define EMU_A2_P17V_SPDIF 0x7a 204#define EMU_A2_P17V_SPDIF_ENABLE 0xff000000 205#define EMU_A2_P17V_I2S 0x7b 206#define EMU_A2_P17V_I2S_ENABLE 0xff000000 207 208/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 209 210#define EMU_CHAN_CPF 0x00 211 212#define EMU_CHAN_CPF_PITCH_MASK 0xffff0000 213#define EMU_CHAN_CPF_PITCH EMU_MKSUBREG(16, 16, EMU_CHAN_CPF) 214#define EMU_CHAN_CPF_STEREO_MASK 0x00008000 215#define EMU_CHAN_CPF_STEREO EMU_MKSUBREG(1, 15, EMU_CHAN_CPF) 216#define EMU_CHAN_CPF_STOP_MASK 0x00004000 217#define EMU_CHAN_CPF_FRACADDRESS_MASK 0x00003fff 218 219 220#define EMU_CHAN_PTRX 0x01 221#define EMU_CHAN_PTRX_PITCHTARGET_MASK 0xffff0000 222#define EMU_CHAN_PTRX_PITCHTARGET EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX) 223#define EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 224#define EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX) 225#define EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK 0x000000ff 226#define EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX) 227 228#define EMU_CHAN_CVCF 0x02 229#define EMU_CHAN_CVCF_CURRVOL_MASK 0xffff0000 230#define EMU_CHAN_CVCF_CURRVOL EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF) 231#define EMU_CHAN_CVCF_CURRFILTER_MASK 0x0000ffff 232#define EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF) 233 234#define EMU_CHAN_VTFT 0x03 235#define EMU_CHAN_VTFT_VOLUMETARGET_MASK 0xffff0000 236#define EMU_CHAN_VTFT_VOLUMETARGET EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT) 237#define EMU_CHAN_VTFT_FILTERTARGET_MASK 0x0000ffff 238#define EMU_CHAN_VTFT_FILTERTARGET EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT) 239 240#define EMU_CHAN_Z1 0x05 241#define EMU_CHAN_Z2 0x04 242 243#define EMU_CHAN_PSST 0x06 244#define EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK 0xff000000 245#define EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST) 246#define EMU_CHAN_PSST_LOOPSTARTADDR_MASK 0x00ffffff 247#define EMU_CHAN_PSST_LOOPSTARTADDR EMU_MKSUBREG(24, 0, EMU_CHAN_PSST) 248 249#define EMU_CHAN_DSL 0x07 250#define EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK 0xff000000 251#define EMU_CHAN_DSL_FXSENDAMOUNT_D EMU_MKSUBREG(8, 24, EMU_CHAN_DSL) 252#define EMU_CHAN_DSL_LOOPENDADDR_MASK 0x00ffffff 253#define EMU_CHAN_DSL_LOOPENDADDR EMU_MKSUBREG(24, 0, EMU_CHAN_DSL) 254 255#define EMU_CHAN_CCCA 0x08 256#define EMU_CHAN_CCCA_RESONANCE 0xf0000000 257#define EMU_CHAN_CCCA_INTERPROMMASK 0x0e000000 258#define EMU_CHAN_CCCA_INTERPROM_0 0x00000000 259#define EMU_CHAN_CCCA_INTERPROM_1 0x02000000 260#define EMU_CHAN_CCCA_INTERPROM_2 0x04000000 261#define EMU_CHAN_CCCA_INTERPROM_3 0x06000000 262#define EMU_CHAN_CCCA_INTERPROM_4 0x08000000 263#define EMU_CHAN_CCCA_INTERPROM_5 0x0a000000 264#define EMU_CHAN_CCCA_INTERPROM_6 0x0c000000 265#define EMU_CHAN_CCCA_INTERPROM_7 0x0e000000 266#define EMU_CHAN_CCCA_8BITSELECT 0x01000000 267#define EMU_CHAN_CCCA_CURRADDR_MASK 0x00ffffff 268#define EMU_CHAN_CCCA_CURRADDR EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA) 269 270#define EMU_CHAN_CCR 0x09 271#define EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK 0xfe000000 272#define EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR) 273#define EMU_CHAN_CCR_CACHELOOPFLAG 0x01000000 274#define EMU_CHAN_CCR_INTERLEAVEDSAMPLES 0x00800000 275#define EMU_CHAN_CCR_WORDSIZEDSAMPLES 0x00400000 276#define EMU_CHAN_CCR_READADDRESS_MASK 0x003f0000 277#define EMU_CHAN_CCR_READADDRESS EMU_MKSUBREG(6, 16, EMU_CHAN_CCR) 278#define EMU_CHAN_CCR_LOOPINVALSIZE 0x0000fe00 279#define EMU_CHAN_CCR_LOOPFLAG 0x00000100 280#define EMU_CHAN_CCR_CACHELOOPADDRHI 0x000000ff 281 282#define EMU_CHAN_CLP 0x0a 283#define EMU_CHAN_CLP_CACHELOOPADDR 0x0000ffff 284 285#define EMU_CHAN_FXRT 0x0b 286#define EMU_CHAN_FXRT_CHANNELA 0x000f0000 287#define EMU_CHAN_FXRT_CHANNELB 0x00f00000 288#define EMU_CHAN_FXRT_CHANNELC 0x0f000000 289#define EMU_CHAN_FXRT_CHANNELD 0xf0000000 290 291#define EMU_CHAN_MAPA 0x0c 292#define EMU_CHAN_MAPB 0x0d 293 294#define EMU_CHAN_MAP_PTE_MASK 0xffffe000 295#define EMU_CHAN_MAP_PTI_MASK 0x00001fff 296 297 298#define EMU_CHAN_ENVVOL 0x10 299#define EMU_CHAN_ENVVOL_MASK 0x0000ffff 300 301 302#define EMU_CHAN_ATKHLDV 0x11 303#define EMU_CHAN_ATKHLDV_PHASE0 0x00008000 304#define EMU_CHAN_ATKHLDV_HOLDTIME_MASK 0x00007f00 305#define EMU_CHAN_ATKHLDV_ATTACKTIME_MASK 0x0000007f 306 307 308#define EMU_CHAN_DCYSUSV 0x12 309#define EMU_CHAN_DCYSUSV_PHASE1_MASK 0x00008000 310#define EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 311#define EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 0x00000080 312#define EMU_CHAN_DCYSUSV_DECAYTIME_MASK 0x0000007f 313 314 315#define EMU_CHAN_LFOVAL1 0x13 316#define EMU_CHAN_LFOVAL_MASK 0x0000ffff 317 318#define EMU_CHAN_ENVVAL 0x14 319#define EMU_CHAN_ENVVAL_MASK 0x0000ffff 320 321#define EMU_CHAN_ATKHLDM 0x15 322#define EMU_CHAN_ATKHLDM_PHASE0 0x00008000 323#define EMU_CHAN_ATKHLDM_HOLDTIME 0x00007f00 324#define EMU_CHAN_ATKHLDM_ATTACKTIME 0x0000007f 325 326#define EMU_CHAN_DCYSUSM 0x16 327#define EMU_CHAN_DCYSUSM_PHASE1_MASK 0x00008000 328#define EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 329#define EMU_CHAN_DCYSUSM_DECAYTIME_MASK 0x0000007f 330 331#define EMU_CHAN_LFOVAL2 0x17 332#define EMU_CHAN_LFOVAL2_MASK 0x0000ffff 333 334#define EMU_CHAN_IP 0x18 335#define EMU_CHAN_IP_MASK 0x0000ffff 336#define EMU_CHAN_IP_UNITY 0x0000e000 337 338#define EMU_CHAN_IFATN 0x19 339#define EMU_CHAN_IFATN_FILTERCUTOFF_MASK 0x0000ff00 340#define EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8, EMU_CHAN_IFATN) 341#define EMU_CHAN_IFATN_ATTENUATION_MASK 0x000000ff 342#define EMU_CHAN_IFATN_ATTENUATION EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN) 343 344#define EMU_CHAN_PEFE 0x1a 345#define EMU_CHAN_PEFE_PITCHAMOUNT_MASK 0x0000ff00 346#define EMU_CHAN_PEFE_PITCHAMOUNT EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE) 347#define EMU_CHAN_PEFE_FILTERAMOUNT_MASK 0x000000ff 348#define EMU_CHAN_PEFE_FILTERAMOUNT EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE) 349 350#define EMU_CHAN_FMMOD 0x1b 351#define EMU_CHAN_FMMOD_MODVIBRATO 0x0000ff00 352#define EMU_CHAN_FMMOD_MOFILTER 0x000000ff 353 354#define EMU_CHAN_TREMFRQ 0x1c 355#define EMU_CHAN_TREMFRQ_DEPTH 0x0000ff00 356 357#define EMU_CHAN_FM2FRQ2 0x1d 358#define EMU_CHAN_FM2FRQ2_DEPTH 0x0000ff00 359#define EMU_CHAN_FM2FRQ2_FREQUENCY 0x000000ff 360 361#define EMU_CHAN_TEMPENV 0x1e 362#define EMU_CHAN_TEMPENV_MASK 0x0000ffff 363 364#define EMU_CHAN_CD0 0x20 365#define EMU_CHAN_CD1 0x21 366#define EMU_CHAN_CD2 0x22 367#define EMU_CHAN_CD3 0x23 368#define EMU_CHAN_CD4 0x24 369#define EMU_CHAN_CD5 0x25 370#define EMU_CHAN_CD6 0x26 371#define EMU_CHAN_CD7 0x27 372#define EMU_CHAN_CD8 0x28 373#define EMU_CHAN_CD9 0x29 374#define EMU_CHAN_CDA 0x2a 375#define EMU_CHAN_CDB 0x2b 376#define EMU_CHAN_CDC 0x2c 377#define EMU_CHAN_CDD 0x2d 378#define EMU_CHAN_CDE 0x2e 379#define EMU_CHAN_CDF 0x2f 380 381/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 382 383#define EMU_PTB 0x40 384#define EMU_PTB_MASK 0xfffff000 385 386#define EMU_TCB 0x41 387#define EMU_TCB_MASK 0xfffff000 388 389#define EMU_ADCCR 0x42 390#define EMU_ADCCR_RCHANENABLE 0x00000010 391#define EMU_ADCCR_LCHANENABLE 0x00000008 392#define EMU_ADCCR_SAMPLERATE_MASK 0x00000007 393#define EMU_A_ADCCR_RCHANENABLE 0x00000020 394#define EMU_A_ADCCR_LCHANENABLE 0x00000010 395#define EMU_A_ADCCR_SAMPLERATE_MASK 0x0000000F 396#define EMU_ADCCR_SAMPLERATE_48 0x00000000 397#define EMU_ADCCR_SAMPLERATE_44 0x00000001 398#define EMU_ADCCR_SAMPLERATE_32 0x00000002 399#define EMU_ADCCR_SAMPLERATE_24 0x00000003 400#define EMU_ADCCR_SAMPLERATE_22 0x00000004 401#define EMU_ADCCR_SAMPLERATE_16 0x00000005 402#define EMU_ADCCR_SAMPLERATE_11 0x00000006 403#define EMU_ADCCR_SAMPLERATE_8 0x00000007 404#define EMU_A_ADCCR_SAMPLERATE_12 0x00000006 405#define EMU_A_ADCCR_SAMPLERATE_11 0x00000007 406#define EMU_A_ADCCR_SAMPLERATE_8 0x00000008 407 408#define EMU_FXWC 0x43 409#define EMU_TCBS 0x44 410#define EMU_TCBS_MASK 0x00000007 411#define EMU_TCBS_BUFFSIZE_16K 0x00000000 412#define EMU_TCBS_BUFFSIZE_32K 0x00000001 413#define EMU_TCBS_BUFFSIZE_64K 0x00000002 414#define EMU_TCBS_BUFFSIZE_128K 0x00000003 415#define EMU_TCBS_BUFFSIZE_256K 0x00000004 416#define EMU_TCBS_BUFFSIZE_512K 0x00000005 417#define EMU_TCBS_BUFFSIZE_1024K 0x00000006 418#define EMU_TCBS_BUFFSIZE_2048K 0x00000007 419 420#define EMU_MICBA 0x45 421#define EMU_ADCBA 0x46 422#define EMU_FXBA 0x47 423#define EMU_RECBA_MASK 0xfffff000 424 425#define EMU_MICBS 0x49 426#define EMU_ADCBS 0x4a 427#define EMU_FXBS 0x4b 428#define EMU_RECBS_BUFSIZE_NONE 0x00000000 429#define EMU_RECBS_BUFSIZE_384 0x00000001 430#define EMU_RECBS_BUFSIZE_448 0x00000002 431#define EMU_RECBS_BUFSIZE_512 0x00000003 432#define EMU_RECBS_BUFSIZE_640 0x00000004 433#define EMU_RECBS_BUFSIZE_768 0x00000005 434#define EMU_RECBS_BUFSIZE_896 0x00000006 435#define EMU_RECBS_BUFSIZE_1024 0x00000007 436#define EMU_RECBS_BUFSIZE_1280 0x00000008 437#define EMU_RECBS_BUFSIZE_1536 0x00000009 438#define EMU_RECBS_BUFSIZE_1792 0x0000000a 439#define EMU_RECBS_BUFSIZE_2048 0x0000000b 440#define EMU_RECBS_BUFSIZE_2560 0x0000000c 441#define EMU_RECBS_BUFSIZE_3072 0x0000000d 442#define EMU_RECBS_BUFSIZE_3584 0x0000000e 443#define EMU_RECBS_BUFSIZE_4096 0x0000000f 444#define EMU_RECBS_BUFSIZE_5120 0x00000010 445#define EMU_RECBS_BUFSIZE_6144 0x00000011 446#define EMU_RECBS_BUFSIZE_7168 0x00000012 447#define EMU_RECBS_BUFSIZE_8192 0x00000013 448#define EMU_RECBS_BUFSIZE_10240 0x00000014 449#define EMU_RECBS_BUFSIZE_12288 0x00000015 450#define EMU_RECBS_BUFSIZE_14366 0x00000016 451#define EMU_RECBS_BUFSIZE_16384 0x00000017 452#define EMU_RECBS_BUFSIZE_20480 0x00000018 453#define EMU_RECBS_BUFSIZE_24576 0x00000019 454#define EMU_RECBS_BUFSIZE_28672 0x0000001a 455#define EMU_RECBS_BUFSIZE_32768 0x0000001b 456#define EMU_RECBS_BUFSIZE_40960 0x0000001c 457#define EMU_RECBS_BUFSIZE_49152 0x0000001d 458#define EMU_RECBS_BUFSIZE_57344 0x0000001e 459#define EMU_RECBS_BUFSIZE_65536 0x0000001f 460 461#define EMU_CDCS 0x50 462#define EMU_GPSCS 0x51 463 464#define EMU_DBG 0x52 465#define EMU_DBG_ZC 0x80000000 466#define EMU_DBG_SATURATION_OCCURED 0x02000000 467#define EMU_DBG_SATURATION_ADDR 0x01ff0000 468#define EMU_DBG_SINGLE_STEP 0x00008000 469#define EMU_DBG_STEP 0x00004000 470#define EMU_DBG_CONDITION_CODE 0x00003e00 471#define EMU_DBG_SINGLE_STEP_ADDR 0x000001ff 472#define EMU_REG53 0x53 473 474#define EMU_A_DBG 0x53 475#define EMU_A_DBG_SINGLE_STEP 0x00020000 476#define EMU_A_DBG_ZC 0x40000000 477#define EMU_A_DBG_STEP_ADDR 0x000003ff 478#define EMU_A_DBG_SATURATION_OCCRD 0x20000000 479#define EMU_A_DBG_SATURATION_ADDR 0x0ffc0000 480 481#define EMU_SPCS0 0x54 482#define EMU_SPCS1 0x55 483#define EMU_SPCS2 0x56 484#define EMU_SPCS_CLKACCYMASK 0x30000000 485#define EMU_SPCS_CLKACCY_1000PPM 0x00000000 486#define EMU_SPCS_CLKACCY_50PPM 0x10000000 487#define EMU_SPCS_CLKACCY_VARIABLE 0x20000000 488#define EMU_SPCS_SAMPLERATEMASK 0x0f000000 489#define EMU_SPCS_SAMPLERATE_44 0x00000000 490#define EMU_SPCS_SAMPLERATE_48 0x02000000 491#define EMU_SPCS_SAMPLERATE_32 0x03000000 492#define EMU_SPCS_CHANNELNUMMASK 0x00f00000 493#define EMU_SPCS_CHANNELNUM_UNSPEC 0x00000000 494#define EMU_SPCS_CHANNELNUM_LEFT 0x00100000 495#define EMU_SPCS_CHANNELNUM_RIGHT 0x00200000 496#define EMU_SPCS_SOURCENUMMASK 0x000f0000 497#define EMU_SPCS_SOURCENUM_UNSPEC 0x00000000 498#define EMU_SPCS_GENERATIONSTATUS 0x00008000 499#define EMU_SPCS_CATEGORYCODEMASK 0x00007f00 500#define EMU_SPCS_MODEMASK 0x000000c0 501#define EMU_SPCS_EMPHASISMASK 0x00000038 502#define EMU_SPCS_EMPHASIS_NONE 0x00000000 503#define EMU_SPCS_EMPHASIS_50_15 0x00000008 504#define EMU_SPCS_COPYRIGHT 0x00000004 505#define EMU_SPCS_NOTAUDIODATA 0x00000002 506#define EMU_SPCS_PROFESSIONAL 0x00000001 507 508#define EMU_CLIEL 0x58 509#define EMU_CLIEH 0x59 510#define EMU_CLIPL 0x5a 511#define EMU_CLIPH 0x5b 512#define EMU_SOLEL 0x5c 513#define EMU_SOLEH 0x5d 514 515#define EMU_SPBYPASS 0x5e 516#define EMU_SPBYPASS_ENABLE 0x00000001 517#define EMU_SPBYPASS_24_BITS 0x00000f00 518 519#define EMU_AC97SLOT 0x5f 520#define EMU_AC97SLOT_CENTER 0x00000010 521#define EMU_AC97SLOT_LFE 0x00000020 522 523#define EMU_CDSRCS 0x60 524#define EMU_GPSRCS 0x61 525#define EMU_ZVSRCS 0x62 526#define EMU_SRCS_SPDIFLOCKED 0x02000000 527#define EMU_SRCS_RATELOCKED 0x01000000 528#define EMU_SRCS_ESTSAMPLERATE 0x0007ffff 529 530#define EMU_MICIDX 0x63 531#define EMU_A_MICIDX 0x64 532#define EMU_ADCIDX 0x64 533#define EMU_A_ADCIDX 0x63 534#define EMU_FXIDX 0x65 535#define EMU_RECIDX_MASK 0x0000ffff 536#define EMU_RECIDX(idxreg) (0x10000000|(idxreg)) 537 538#define EMU_A_MUDATA1 0x70 539#define EMU_A_MUCMD1 0x71 540#define EMU_A_MUSTAT1 EMU_A_MUCMD1 541 542#define EMU_A_MUDATA2 0x72 543#define EMU_A_MUCMD2 0x73 544#define EMU_A_MUSTAT2 EMU_A_MUCMD2 545 546#define EMU_A_FXWC1 0x74 547#define EMU_A_FXWC2 0x75 548 549#define EMU_A_SPDIF_SAMPLERATE 0x76 550#define EMU_A_SPDIF_48000 0x00000080 551#define EMU_A_SPDIF_44100 0x00000000 552#define EMU_A_SPDIF_96000 0x00000040 553#define EMU_A2_SPDIF_SAMPLERATE EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE) 554#define EMU_A2_SPDIF_MASK 0x00000e00 555#define EMU_A2_SPDIF_UNKNOWN 0x2 556 557#define EMU_A_CHAN_FXRT2 0x7c 558#define EMU_A_CHAN_FXRT_CHANNELE 0x0000003f 559#define EMU_A_CHAN_FXRT_CHANNELF 0x00003f00 560#define EMU_A_CHAN_FXRT_CHANNELG 0x003f0000 561#define EMU_A_CHAN_FXRT_CHANNELH 0x3f000000 562 563#define EMU_A_CHAN_SENDAMOUNTS 0x7d 564#define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK 0xff000000 565#define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK 0x00ff0000 566#define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK 0x0000ff00 567#define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK 0x000000ff 568 569#define EMU_A_CHAN_FXRT1 0x7e 570#define EMU_A_CHAN_FXRT_CHANNELA 0x0000003f 571#define EMU_A_CHAN_FXRT_CHANNELB 0x00003f00 572#define EMU_A_CHAN_FXRT_CHANNELC 0x003f0000 573#define EMU_A_CHAN_FXRT_CHANNELD 0x3f000000 574 575#define EMU_FXGPREGBASE 0x100 576#define EMU_A_FXGPREGBASE 0x400 577 578#define EMU_TANKMEMDATAREGBASE 0x200 579#define EMU_TANKMEMDATAREG_MASK 0x000fffff 580 581#define EMU_TANKMEMADDRREGBASE 0x300 582#define EMU_TANKMEMADDRREG_ADDR_MASK 0x000fffff 583#define EMU_TANKMEMADDRREG_CLEAR 0x00800000 584#define EMU_TANKMEMADDRREG_ALIGN 0x00400000 585#define EMU_TANKMEMADDRREG_WRITE 0x00200000 586#define EMU_TANKMEMADDRREG_READ 0x00100000 587 588#define EMU_MICROCODEBASE 0x400 589#define EMU_DSP_LOWORD_OPX_MASK 0x000ffc00 590#define EMU_DSP_LOWORD_OPY_MASK 0x000003ff 591#define EMU_DSP_HIWORD_OPCODE_MASK 0x00f00000 592#define EMU_DSP_HIWORD_RESULT_MASK 0x000ffc00 593#define EMU_DSP_HIWORD_OPA_MASK 0x000003ff 594 595#define EMU_A_MICROCODEBASE 0x600 596#define EMU_A_DSP_LOWORD_OPX_MASK 0x007ff000 597#define EMU_A_DSP_LOWORD_OPY_MASK 0x000007ff 598#define EMU_A_DSP_HIWORD_OPCODE_MASK 0x0f000000 599#define EMU_A_DSP_HIWORD_RESULT_MASK 0x007ff000 600#define EMU_A_DSP_HIWORD_OPA_MASK 0x000007ff 601 602#define EMU_DSP_OP_MACS 0x0 603#define EMU_DSP_OP_MACS1 0x1 604#define EMU_DSP_OP_MACW 0x2 605#define EMU_DSP_OP_MACW1 0x3 606#define EMU_DSP_OP_MACINTS 0x4 607#define EMU_DSP_OP_MACINTW 0x5 608#define EMU_DSP_OP_ACC3 0x6 609#define EMU_DSP_OP_MACMV 0x7 610#define EMU_DSP_OP_ANDXOR 0x8 611#define EMU_DSP_OP_TSTNEG 0x9 612#define EMU_DSP_OP_LIMIT 0xa 613#define EMU_DSP_OP_LIMIT1 0xb 614#define EMU_DSP_OP_LOG 0xc 615#define EMU_DSP_OP_EXP 0xd 616#define EMU_DSP_OP_INTERP 0xe 617#define EMU_DSP_OP_SKIP 0xf 618 619 620#define EMU_DSP_FX(num) (num) 621 622#define EMU_DSP_IOL(base, num) (base + (num << 1)) 623#define EMU_DSP_IOR(base, num) (EMU_DSP_IOL(base, num) + 1) 624 625#define EMU_DSP_INL_BASE 0x010 626#define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num)) 627#define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num)) 628#define EMU_DSP_IN_AC97 0 629#define EMU_DSP_IN_CDSPDIF 1 630#define EMU_DSP_IN_ZOOM 2 631#define EMU_DSP_IN_TOSOPT 3 632#define EMU_DSP_IN_LVDLM1 4 633#define EMU_DSP_IN_LVDCOS 5 634#define EMU_DSP_IN_LVDLM2 6 635#define EMU_DSP_IN_UNKOWN 7 636 637#define EMU_A_DSP_INL_BASE 0x040 638#define EMU_A_DSP_INL(num) (EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num)) 639#define EMU_A_DSP_INR(num) (EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num)) 640 641#define EMU_DSP_OUTL_BASE 0x020 642#define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num)) 643#define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num)) 644#define EMU_DSP_OUT_A_FRONT 0 645#define EMU_DSP_OUT_D_FRONT 1 // not tested 646#define EMU_DSP_OUT_D_CENTER 2 // not tested 647#define EMU_DSP_OUT_DRIVE_HP 3 // not tested 648#define EMU_DSP_OUT_AD_REAR 4 649#define EMU_DSP_OUT_ADC 5 650#define EMU_DSP_OUTL_MIC 6 651#define EMU_DSP_OUT_A_CENTER (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, 8)) // Live 5.1 only 652#define EMU_DSP_OUT_A_SUB (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, 9)) // Live 5.1 only 653 654#define EMU_A_DSP_OUTL_BASE 0x060 655#define EMU_A_DSP_OUTL(num) (EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num)) 656#define EMU_A_DSP_OUTR(num) (EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num)) 657#define EMU_A_DSP_OUT_D_FRONT 0 // not tested 658#define EMU_A_DSP_OUT_D_CENTER 1 // not tested 659#define EMU_A_DSP_OUT_DRIVE_HP 2 // not tested 660#define EMU_A_DSP_OUT_D_REAR 3 // not tested 661#define EMU_A_DSP_OUT_A_FRONT 4 662#define EMU_A_DSP_OUT_A_CENTER 5 663#define EMU_A_DSP_OUT_A_REAR 7 664#define EMU_A_DSP_OUT_ADC 11 665 666 667#define EMU_DSP_CST_BASE 0x40 668#define EMU_A_DSP_CST_BASE 0xc0 669#define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num) 670#define EMU_A_DSP_CST(num) (EMU_A_DSP_CST_BASE + num) 671/* 67200 = 0x00000000 67301 = 0x00000001 67402 = 0x00000002 67503 = 0x00000003 67604 = 0x00000004 67705 = 0x00000008 67806 = 0x00000010 67907 = 0x00000020 68008 = 0x00000100 68109 = 0x00010000 6820A = 0x00080000 6830B = 0x10000000 6840C = 0x20000000 6850D = 0x40000000 6860E = 0x80000000 6870F = 0x7FFFFFFF 68810 = 0xFFFFFFFF 68911 = 0xFFFFFFFE 69012 = 0xC0000000 69113 = 0x4F1BBCDC 69214 = 0x5A7EF9DB 69315 = 0x00100000 694*/ 695 696#define EMU_DSP_HWR_ACC 0x056 697#define EMU_DSP_HWR_CCR 0x057 698#define EMU_DSP_HWR_CCR_S 0x04 699#define EMU_DSP_HWR_CCR_Z 0x03 700#define EMU_DSP_HWR_CCR_M 0x02 701#define EMU_DSP_HWR_CCR_N 0x01 702#define EMU_DSP_HWR_CCR_B 0x00 703#define EMU_DSP_HWR_NOISE0 0x058 704#define EMU_DSP_HWR_NOISE1 0x059 705#define EMU_DSP_HWR_INTR 0x05A 706#define EMU_DSP_HWR_DBAC 0x05B 707 708#define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num) 709#define EMU_A_DSP_GPR(num) (EMU_A_FXGPREGBASE + num) 710 711#endif /* _DEV_PCI_EMUXKIREG_H_ */ 712