1/* $OpenBSD: if_iwmreg.h,v 1.68 2022/03/19 10:26:52 stsp Exp $ */ 2 3/****************************************************************************** 4 * 5 * This file is provided under a dual BSD/GPLv2 license. When using or 6 * redistributing this file, you may do so under either license. 7 * 8 * GPL LICENSE SUMMARY 9 * 10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <ilw@linux.intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 66/* 67 * CSR (control and status registers) 68 * 69 * CSR registers are mapped directly into PCI bus space, and are accessible 70 * whenever platform supplies power to device, even when device is in 71 * low power states due to driver-invoked device resets 72 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 73 * 74 * Use iwl_write32() and iwl_read32() family to access these registers; 75 * these provide simple PCI bus access, without waking up the MAC. 76 * Do not use iwl_write_direct32() family for these registers; 77 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 78 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 79 * the CSR registers. 80 * 81 * NOTE: Device does need to be awake in order to read this memory 82 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 83 */ 84#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 85#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 86#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 87#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 88#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 89#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 90#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 91#define IWM_CSR_GP_CNTRL (0x024) 92 93/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 94#define IWM_CSR_INT_PERIODIC_REG (0x005) 95 96/* 97 * Hardware revision info 98 * Bit fields: 99 * 31-16: Reserved 100 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 101 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 102 * 1-0: "Dash" (-) value, as in A-1, etc. 103 */ 104#define IWM_CSR_HW_REV (0x028) 105 106/* 107 * EEPROM and OTP (one-time-programmable) memory reads 108 * 109 * NOTE: Device must be awake, initialized via apm_ops.init(), 110 * in order to read. 111 */ 112#define IWM_CSR_EEPROM_REG (0x02c) 113#define IWM_CSR_EEPROM_GP (0x030) 114#define IWM_CSR_OTP_GP_REG (0x034) 115 116#define IWM_CSR_GIO_REG (0x03C) 117#define IWM_CSR_GP_UCODE_REG (0x048) 118#define IWM_CSR_GP_DRIVER_REG (0x050) 119 120/* 121 * UCODE-DRIVER GP (general purpose) mailbox registers. 122 * SET/CLR registers set/clear bit(s) if "1" is written. 123 */ 124#define IWM_CSR_UCODE_DRV_GP1 (0x054) 125#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 126#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 127#define IWM_CSR_UCODE_DRV_GP2 (0x060) 128 129#define IWM_CSR_MBOX_SET_REG (0x088) 130#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 131 132#define IWM_CSR_LED_REG (0x094) 133#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 134#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 135 136 137/* GIO Chicken Bits (PCI Express bus link power management) */ 138#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 139 140/* Analog phase-lock-loop configuration */ 141#define IWM_CSR_ANA_PLL_CFG (0x20c) 142 143/* 144 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 145 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 146 * See also IWM_CSR_HW_REV register. 147 * Bit fields: 148 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 149 * 1-0: "Dash" (-) value, as in C-1, etc. 150 */ 151#define IWM_CSR_HW_REV_WA_REG (0x22C) 152 153#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 154#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 155 156/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 157#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 158#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 159#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 160#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 161#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 162#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 163#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 164#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 165 166#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 167#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 168#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 169#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 170#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 171#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 172 173#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 174#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 175#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 176#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 177#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 178#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 179#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 180 181#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 182#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 183 184/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 185 * acknowledged (reset) by host writing "1" to flagged bits. */ 186#define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 187#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 188#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 189#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 190#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 191#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 192#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 193#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 194#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 195#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 196#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 197 198#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 199 IWM_CSR_INT_BIT_HW_ERR | \ 200 IWM_CSR_INT_BIT_FH_TX | \ 201 IWM_CSR_INT_BIT_SW_ERR | \ 202 IWM_CSR_INT_BIT_RF_KILL | \ 203 IWM_CSR_INT_BIT_SW_RX | \ 204 IWM_CSR_INT_BIT_WAKEUP | \ 205 IWM_CSR_INT_BIT_ALIVE | \ 206 IWM_CSR_INT_BIT_RX_PERIODIC) 207 208/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 209#define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 210#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 211#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 212#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 213#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 214#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 215 216#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 217 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 218 IWM_CSR_FH_INT_BIT_RX_CHNL0) 219 220#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 221 IWM_CSR_FH_INT_BIT_TX_CHNL0) 222 223/* GPIO */ 224#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 225#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 226#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 227 228/* RESET */ 229#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 230#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 231#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 232#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 233#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 234#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 235 236/* 237 * GP (general purpose) CONTROL REGISTER 238 * Bit fields: 239 * 27: HW_RF_KILL_SW 240 * Indicates state of (platform's) hardware RF-Kill switch 241 * 26-24: POWER_SAVE_TYPE 242 * Indicates current power-saving mode: 243 * 000 -- No power saving 244 * 001 -- MAC power-down 245 * 010 -- PHY (radio) power-down 246 * 011 -- Error 247 * 9-6: SYS_CONFIG 248 * Indicates current system configuration, reflecting pins on chip 249 * as forced high/low by device circuit board. 250 * 4: GOING_TO_SLEEP 251 * Indicates MAC is entering a power-saving sleep power-down. 252 * Not a good time to access device-internal resources. 253 * 3: MAC_ACCESS_REQ 254 * Host sets this to request and maintain MAC wakeup, to allow host 255 * access to device-internal resources. Host must wait for 256 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 257 * device registers. 258 * 2: INIT_DONE 259 * Host sets this to put device into fully operational D0 power mode. 260 * Host resets this after SW_RESET to put device into low power mode. 261 * 0: MAC_CLOCK_READY 262 * Indicates MAC (ucode processor, etc.) is powered up and can run. 263 * Internal resources are accessible. 264 * NOTE: This does not indicate that the processor is actually running. 265 * NOTE: This does not indicate that device has completed 266 * init or post-power-down restore of internal SRAM memory. 267 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 268 * SRAM is restored and uCode is in normal operation mode. 269 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 270 * do not need to save/restore it. 271 * NOTE: After device reset, this bit remains "0" until host sets 272 * INIT_DONE 273 */ 274#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 275#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 276#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 277#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 278 279#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 280 281#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 282#define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 283#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 284 285 286/* HW REV */ 287#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 288#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 289 290#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 291#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 292#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 293#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 294#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 295#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 296#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 297#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 298#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 299#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 300#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 301#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 302#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 303#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 304#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 305#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 306#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 307#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 308 309/* EEPROM REG */ 310#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 311#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 312#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 313#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 314 315/* EEPROM GP */ 316#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 317#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 318#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 319#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 320#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 321#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 322 323/* One-time-programmable memory general purpose reg */ 324#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 325#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 326#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 327#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 328 329/* GP REG */ 330#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 331#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 332#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 333#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 334#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 335 336 337/* CSR GIO */ 338#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 339 340/* 341 * UCODE-DRIVER GP (general purpose) mailbox register 1 342 * Host driver and uCode write and/or read this register to communicate with 343 * each other. 344 * Bit fields: 345 * 4: UCODE_DISABLE 346 * Host sets this to request permanent halt of uCode, same as 347 * sending CARD_STATE command with "halt" bit set. 348 * 3: CT_KILL_EXIT 349 * Host sets this to request exit from CT_KILL state, i.e. host thinks 350 * device temperature is low enough to continue normal operation. 351 * 2: CMD_BLOCKED 352 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 353 * to release uCode to clear all Tx and command queues, enter 354 * unassociated mode, and power down. 355 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 356 * 1: SW_BIT_RFKILL 357 * Host sets this when issuing CARD_STATE command to request 358 * device sleep. 359 * 0: MAC_SLEEP 360 * uCode sets this when preparing a power-saving power-down. 361 * uCode resets this when power-up is complete and SRAM is sane. 362 * NOTE: device saves internal SRAM data to host when powering down, 363 * and must restore this data after powering back up. 364 * MAC_SLEEP is the best indication that restore is complete. 365 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 366 * do not need to save/restore it. 367 */ 368#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 369#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 370#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 371#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 372#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 373 374/* GP Driver */ 375#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 376#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 377#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 378#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 379#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 380#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 381 382#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 383 384/* GIO Chicken Bits (PCI Express bus link power management) */ 385#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 386#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 387 388/* LED */ 389#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 390#define IWM_CSR_LED_REG_TURN_ON (0x60) 391#define IWM_CSR_LED_REG_TURN_OFF (0x20) 392 393/* ANA_PLL */ 394#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 395 396/* HPET MEM debug */ 397#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 398 399/* DRAM INT TABLE */ 400#define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 401#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 402#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 403 404/* SECURE boot registers */ 405#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 406#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001 407#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002 408#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 409#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 410#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003 411#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002 412#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004 413#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008 414#define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010 415 416#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 417 418#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 419 420/* 9000 rx series registers */ 421 422#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 423#define IWM_RFH_Q_FRBDCB_BA_LSB(q) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 424/* Write index table */ 425#define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080 426#define IWM_RFH_Q_FRBDCB_WIDX(q) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4) 427/* Write index table - shadow registers */ 428#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 429#define IWM_RFH_Q_FRBDCB_WIDX_TRG(q) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 430/* Read index table */ 431#define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0 432#define IWM_RFH_Q_FRBDCB_RIDX(q) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4) 433/* Used list table */ 434#define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 435#define IWM_RFH_Q_URBDCB_BA_LSB(q) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 436/* Write index table */ 437#define IWM_RFH_Q0_URBDCB_WIDX 0xA08180 438#define IWM_RFH_Q_URBDCB_WIDX(q) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4) 439#define IWM_RFH_Q0_URBDCB_VAID 0xA081C0 440#define IWM_RFH_Q_URBDCB_VAID(q) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4) 441/* stts */ 442#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 443#define IWM_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 444 445#define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280 446#define IWM_RFH_Q_ORB_WPTR_LSB(q) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 447#define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300 448#define IWM_RFH_RBDBUF_RBD_LSB(q) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8) 449 450/** 451 * RFH Status Register 452 * 453 * Bit fields: 454 * 455 * Bit 29: RBD_FETCH_IDLE 456 * This status flag is set by the RFH when there is no active RBD fetch from 457 * DRAM. 458 * Once the RFH RBD controller starts fetching (or when there is a pending 459 * RBD read response from DRAM), this flag is immediately turned off. 460 * 461 * Bit 30: SRAM_DMA_IDLE 462 * This status flag is set by the RFH when there is no active transaction from 463 * SRAM to DRAM. 464 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 465 * 466 * Bit 31: RXF_DMA_IDLE 467 * This status flag is set by the RFH when there is no active transaction from 468 * RXF to DRAM. 469 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 470 */ 471#define IWM_RFH_GEN_STATUS 0xA09808 472#define IWM_RFH_GEN_STATUS_GEN3 0xA07824 473#define IWM_RBD_FETCH_IDLE (1 << 29) 474#define IWM_SRAM_DMA_IDLE (1 << 30) 475#define IWM_RXF_DMA_IDLE (1U << 31) 476 477/* DMA configuration */ 478#define IWM_RFH_RXF_DMA_CFG 0xA09820 479#define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880 480/* RB size */ 481#define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 482#define IWM_RFH_RXF_DMA_RB_SIZE_POS 16 483#define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 484#define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 485#define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 486#define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 487#define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 488#define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS) 489#define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS) 490#define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS) 491#define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS) 492#define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS) 493/* RB Circular Buffer size:defines the table sizes in RBD units */ 494#define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 495#define IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20 496#define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 497#define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 498#define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 499#define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 500#define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 501#define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 502#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 503#define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 504#define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 505#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 506#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 507#define IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS) 508#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 509#define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 510#define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 511#define IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31) 512 513#define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C 514 515#define IWM_RFH_GEN_CFG 0xA09800 516#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 517#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 518#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 519#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 520/* the driver assumes everywhere that the default RXQ is 0 */ 521#define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 522 523/* end of 9000 rx series registers */ 524 525#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 526#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 527 528#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 529#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 530 531#define IWM_CSR_SECURE_TIME_OUT (100) 532 533/* extended range in FW SRAM */ 534#define IWM_FW_MEM_EXTENDED_START 0x40000 535#define IWM_FW_MEM_EXTENDED_END 0x57FFF 536 537/* FW chicken bits */ 538#define IWM_LMPM_CHICK 0xa01ff8 539#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 540 541#define IWM_FH_TCSR_0_REG0 (0x1D00) 542 543/* 544 * HBUS (Host-side Bus) 545 * 546 * HBUS registers are mapped directly into PCI bus space, but are used 547 * to indirectly access device's internal memory or registers that 548 * may be powered-down. 549 * 550 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 551 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 552 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 553 * internal resources. 554 * 555 * Do not use iwl_write32()/iwl_read32() family to access these registers; 556 * these provide only simple PCI bus access, without waking up the MAC. 557 */ 558#define IWM_HBUS_BASE (0x400) 559 560/* 561 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 562 * structures, error log, event log, verifying uCode load). 563 * First write to address register, then read from or write to data register 564 * to complete the job. Once the address register is set up, accesses to 565 * data registers auto-increment the address by one dword. 566 * Bit usage for address registers (read or write): 567 * 0-31: memory address within device 568 */ 569#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 570#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 571#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 572#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 573 574/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 575#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 576#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 577 578/* 579 * Registers for accessing device's internal peripheral registers 580 * (e.g. SCD, BSM, etc.). First write to address register, 581 * then read from or write to data register to complete the job. 582 * Bit usage for address registers (read or write): 583 * 0-15: register address (offset) within device 584 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 585 */ 586#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 587#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 588#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 589#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 590 591/* enable the ID buf for read */ 592#define IWM_WFPM_PS_CTL_CLR 0xa0300c 593#define IWM_WFMP_MAC_ADDR_0 0xa03080 594#define IWM_WFMP_MAC_ADDR_1 0xa03084 595#define IWM_LMPM_PMG_EN 0xa01cec 596#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 597#define IWM_RFIC_REG_RD 0xad0470 598#define IWM_WFPM_CTRL_REG 0xa03030 599#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 600#define IWM_ENABLE_WFPM 0x80000000 601 602#define IWM_AUX_MISC_REG 0xa200b0 603#define IWM_HW_STEP_LOCATION_BITS 24 604 605#define IWM_AUX_MISC_MASTER1_EN 0xa20818 606#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 607#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 608#define IWM_RSA_ENABLE 0xa24b08 609#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 610#define IWM_PREG_PRPH_WPROT_9000 0xa04ce0 611#define IWM_PREG_PRPH_WPROT_22000 0xa04d00 612#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 613#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 614#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 615#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 616#define IWM_SB_CPU_1_STATUS 0xa01e30 617#define IWM_SB_CPU_2_STATUS 0Xa01e34 618 619#define IWM_UREG_CHICK 0xa05c00 620#define IWM_UREG_CHICK_MSI_ENABLE (1 << 24) 621#define IWM_UREG_CHICK_MSIX_ENABLE (1 << 25) 622 623#define IWM_HPM_DEBUG 0xa03440 624#define IWM_HPM_PERSISTENCE_BIT (1 << 12) 625#define IWM_PREG_WFPM_ACCESS (1 << 12) 626 627/* Used to enable DBGM */ 628#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 629 630/* 631 * Per-Tx-queue write pointer (index, really!) 632 * Indicates index to next TFD that driver will fill (1 past latest filled). 633 * Bit usage: 634 * 0-7: queue write index 635 * 11-8: queue selector 636 */ 637#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 638 639/********************************************************** 640 * CSR values 641 **********************************************************/ 642 /* 643 * host interrupt timeout value 644 * used with setting interrupt coalescing timer 645 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 646 * 647 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 648 */ 649#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 650#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 651#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 652#define IWM_HOST_INT_OPER_MODE (1U << 31) 653 654/***************************************************************************** 655 * 7000/3000 series SHR DTS addresses * 656 *****************************************************************************/ 657 658/* Diode Results Register Structure: */ 659#define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */ 660#define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */ 661#define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */ 662#define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */ 663#define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */ 664#define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */ 665/* Those are the masks INSIDE the flags bit-field: */ 666#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0 667#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */ 668#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7 669#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */ 670 671/***************************************************************************** 672 * MSIX related registers * 673 *****************************************************************************/ 674 675#define IWM_CSR_MSIX_BASE (0x2000) 676#define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800) 677#define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804) 678#define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808) 679#define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C) 680#define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810) 681#define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880) 682#define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890) 683#define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000) 684#define IWM_CSR_MSIX_RX_IVAR(cause) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 685#define IWM_CSR_MSIX_IVAR(cause) (IWM_CSR_MSIX_IVAR_AD_REG + (cause)) 686 687/* 688 * Causes for the FH register interrupts 689 */ 690enum msix_fh_int_causes { 691 IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 692 IWM_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 693 IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 694 IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 695 IWM_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 696 IWM_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 697}; 698 699/* 700 * Causes for the HW register interrupts 701 */ 702enum msix_hw_int_causes { 703 IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 704 IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 705 IWM_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1), 706 IWM_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2), 707 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 708 IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 709 IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 710 IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 711 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 712 IWM_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 713 IWM_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 714 IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 715 IWM_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 716}; 717 718/* 719 * Registers to map causes to vectors 720 */ 721enum msix_ivar_for_cause { 722 IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 723 IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 724 IWM_MSIX_IVAR_CAUSE_S2D = 0x3, 725 IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 726 IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 727 IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 728 IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12, 729 IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 730 IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 731 IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 732 IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 733 IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 734 IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 735 IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 736 IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 737}; 738 739#define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 740#define IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 741 742/** 743 * uCode API flags 744 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 745 * was a separate TLV but moved here to save space. 746 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 747 * treats good CRC threshold as a boolean 748 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 749 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 750 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 751 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 752 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 753 * offload profile config command. 754 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 755 * (rather than two) IPv6 addresses 756 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 757 * from the probe request template. 758 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 759 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 760 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 761 * single bound interface). 762 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 763 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 764 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 765 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 766 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 767 * 768 */ 769#define IWM_UCODE_TLV_FLAGS_PAN (1 << 0) 770#define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 771#define IWM_UCODE_TLV_FLAGS_MFP (1 << 2) 772#define IWM_UCODE_TLV_FLAGS_P2P (1 << 3) 773#define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 774#define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 775#define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 776#define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 777#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 778#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 779#define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 780#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 781#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 782#define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 783#define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 784#define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 785#define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 786#define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 787#define IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 788 789#define IWM_UCODE_TLV_FLAG_BITS \ 790 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 791 792/** 793 * uCode TLV api 794 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 795 * longer than the passive one, which is essential for fragmented scan. 796 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 797 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 798 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 799 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format 800 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 801 * (command version 3) that supports per-chain limits 802 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 803 * iteration complete notification, and the timestamp reported for RX 804 * received during scan, are reported in TSF of the mac specified in the 805 * scan request. 806 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 807 * ADD_MODIFY_STA_KEY_API_S_VER_2. 808 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment. 809 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 810 * instead of 3. 811 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 812 * 813 * @IWM_NUM_UCODE_TLV_API: number of bits used 814 */ 815#define IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8 816#define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9 817#define IWM_UCODE_TLV_API_WIDE_CMD_HDR 14 818#define IWM_UCODE_TLV_API_LQ_SS_PARAMS 18 819#define IWM_UCODE_TLV_API_NEW_VERSION 20 820#define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 821#define IWM_UCODE_TLV_API_TX_POWER_CHAIN 27 822#define IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28 823#define IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29 824#define IWM_UCODE_TLV_API_STA_TYPE 30 825#define IWM_UCODE_TLV_API_NAN2_VER2 31 826#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32 827#define IWM_UCODE_TLV_API_NEW_RX_STATS 35 828#define IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38 829#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 830#define IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 831#define IWM_NUM_UCODE_TLV_API 128 832 833#define IWM_UCODE_TLV_API_BITS \ 834 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 835 836/** 837 * uCode capabilities 838 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 839 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 840 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 841 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 842 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 843 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 844 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 845 * tx power value into TPC Report action frame and Link Measurement Report 846 * action frame 847 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 848 * channel in DS parameter set element in probe requests. 849 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 850 * probe requests. 851 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 852 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 853 * which also implies support for the scheduler configuration command 854 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 855 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 856 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 857 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 858 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 859 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 860 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 861 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 862 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 863 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 864 * sources for the MCC. This TLV bit is a future replacement to 865 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 866 * is supported. 867 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 868 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 869 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 870 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 871 * 0=no support) 872 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 873 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 874 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 875 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 876 * antenna the beacon should be transmitted 877 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 878 * from AP and will send it upon d0i3 exit. 879 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 880 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 881 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 882 * thresholds reporting 883 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 884 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 885 * regular image. 886 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 887 * memory addresses from the firmware. 888 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 889 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 890 * 0=no support) 891 * 892 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 893 */ 894#define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0 895#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1 896#define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2 897#define IWM_UCODE_TLV_CAPA_BEAMFORMER 3 898#define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5 899#define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6 900#define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 901#define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 902#define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 903#define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 904#define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12 905#define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 906#define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 907#define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 908#define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 909#define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 910#define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21 911#define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 912#define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 913#define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28 914#define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 915#define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30 916#define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 917#define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34 918#define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35 919#define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37 920#define IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 921#define IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40 922#define IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 923#define IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 924#define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 925#define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 926#define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 927#define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 928#define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 929#define IWM_UCODE_TLV_CAPA_BEACON_STORING 72 930#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V3 73 931#define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 932#define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 933#define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76 934#define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 935#define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79 936#define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 937#define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81 938 939#define IWM_NUM_UCODE_TLV_CAPA 128 940 941/* The default calibrate table size if not specified by firmware file */ 942#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 943#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 944#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 945 946/* The default max probe length if not specified by the firmware file */ 947#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 948 949/* 950 * For 16.0 uCode and above, there is no differentiation between sections, 951 * just an offset to the HW address. 952 */ 953#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 954#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 955 956/* uCode version contains 4 values: Major/Minor/API/Serial */ 957#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 958#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 959#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 960#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 961 962/* 963 * Calibration control struct. 964 * Sent as part of the phy configuration command. 965 * @flow_trigger: bitmap for which calibrations to perform according to 966 * flow triggers. 967 * @event_trigger: bitmap for which calibrations to perform according to 968 * event triggers. 969 */ 970struct iwm_tlv_calib_ctrl { 971 uint32_t flow_trigger; 972 uint32_t event_trigger; 973} __packed; 974 975#define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0 976#define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS) 977#define IWM_FW_PHY_CFG_RADIO_STEP_POS 2 978#define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS) 979#define IWM_FW_PHY_CFG_RADIO_DASH_POS 4 980#define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS) 981#define IWM_FW_PHY_CFG_TX_CHAIN_POS 16 982#define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS) 983#define IWM_FW_PHY_CFG_RX_CHAIN_POS 20 984#define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS) 985#define IWM_FW_PHY_CFG_SHARED_CLK (1U << 31) 986 987#define IWM_UCODE_MAX_CS 1 988 989/** 990 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 991 * @cipher: a cipher suite selector 992 * @flags: cipher scheme flags (currently reserved for a future use) 993 * @hdr_len: a size of MPDU security header 994 * @pn_len: a size of PN 995 * @pn_off: an offset of pn from the beginning of the security header 996 * @key_idx_off: an offset of key index byte in the security header 997 * @key_idx_mask: a bit mask of key_idx bits 998 * @key_idx_shift: bit shift needed to get key_idx 999 * @mic_len: mic length in bytes 1000 * @hw_cipher: a HW cipher index used in host commands 1001 */ 1002struct iwm_fw_cipher_scheme { 1003 uint32_t cipher; 1004 uint8_t flags; 1005 uint8_t hdr_len; 1006 uint8_t pn_len; 1007 uint8_t pn_off; 1008 uint8_t key_idx_off; 1009 uint8_t key_idx_mask; 1010 uint8_t key_idx_shift; 1011 uint8_t mic_len; 1012 uint8_t hw_cipher; 1013} __packed; 1014 1015/** 1016 * struct iwm_fw_cscheme_list - a cipher scheme list 1017 * @size: a number of entries 1018 * @cs: cipher scheme entries 1019 */ 1020struct iwm_fw_cscheme_list { 1021 uint8_t size; 1022 struct iwm_fw_cipher_scheme cs[]; 1023} __packed; 1024 1025/* v1/v2 uCode file layout */ 1026struct iwm_ucode_header { 1027 uint32_t ver; /* major/minor/API/serial */ 1028 union { 1029 struct { 1030 uint32_t inst_size; /* bytes of runtime code */ 1031 uint32_t data_size; /* bytes of runtime data */ 1032 uint32_t init_size; /* bytes of init code */ 1033 uint32_t init_data_size; /* bytes of init data */ 1034 uint32_t boot_size; /* bytes of bootstrap code */ 1035 uint8_t data[0]; /* in same order as sizes */ 1036 } v1; 1037 struct { 1038 uint32_t build; /* build number */ 1039 uint32_t inst_size; /* bytes of runtime code */ 1040 uint32_t data_size; /* bytes of runtime data */ 1041 uint32_t init_size; /* bytes of init code */ 1042 uint32_t init_data_size; /* bytes of init data */ 1043 uint32_t boot_size; /* bytes of bootstrap code */ 1044 uint8_t data[0]; /* in same order as sizes */ 1045 } v2; 1046 } u; 1047}; 1048 1049/* 1050 * new TLV uCode file layout 1051 * 1052 * The new TLV file format contains TLVs, that each specify 1053 * some piece of data. 1054 */ 1055 1056#define IWM_UCODE_TLV_INVALID 0 /* unused */ 1057#define IWM_UCODE_TLV_INST 1 1058#define IWM_UCODE_TLV_DATA 2 1059#define IWM_UCODE_TLV_INIT 3 1060#define IWM_UCODE_TLV_INIT_DATA 4 1061#define IWM_UCODE_TLV_BOOT 5 1062#define IWM_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 1063#define IWM_UCODE_TLV_PAN 7 1064#define IWM_UCODE_TLV_RUNT_EVTLOG_PTR 8 1065#define IWM_UCODE_TLV_RUNT_EVTLOG_SIZE 9 1066#define IWM_UCODE_TLV_RUNT_ERRLOG_PTR 10 1067#define IWM_UCODE_TLV_INIT_EVTLOG_PTR 11 1068#define IWM_UCODE_TLV_INIT_EVTLOG_SIZE 12 1069#define IWM_UCODE_TLV_INIT_ERRLOG_PTR 13 1070#define IWM_UCODE_TLV_ENHANCE_SENS_TBL 14 1071#define IWM_UCODE_TLV_PHY_CALIBRATION_SIZE 15 1072#define IWM_UCODE_TLV_WOWLAN_INST 16 1073#define IWM_UCODE_TLV_WOWLAN_DATA 17 1074#define IWM_UCODE_TLV_FLAGS 18 1075#define IWM_UCODE_TLV_SEC_RT 19 1076#define IWM_UCODE_TLV_SEC_INIT 20 1077#define IWM_UCODE_TLV_SEC_WOWLAN 21 1078#define IWM_UCODE_TLV_DEF_CALIB 22 1079#define IWM_UCODE_TLV_PHY_SKU 23 1080#define IWM_UCODE_TLV_SECURE_SEC_RT 24 1081#define IWM_UCODE_TLV_SECURE_SEC_INIT 25 1082#define IWM_UCODE_TLV_SECURE_SEC_WOWLAN 26 1083#define IWM_UCODE_TLV_NUM_OF_CPU 27 1084#define IWM_UCODE_TLV_CSCHEME 28 1085 1086 /* 1087 * Following two are not in our base tag, but allow 1088 * handling ucode version 9. 1089 */ 1090#define IWM_UCODE_TLV_API_CHANGES_SET 29 1091#define IWM_UCODE_TLV_ENABLED_CAPABILITIES 30 1092#define IWM_UCODE_TLV_N_SCAN_CHANNELS 31 1093#define IWM_UCODE_TLV_PAGING 32 1094#define IWM_UCODE_TLV_SEC_RT_USNIFFER 34 1095#define IWM_UCODE_TLV_SDIO_ADMA_ADDR 35 1096#define IWM_UCODE_TLV_FW_VERSION 36 1097#define IWM_UCODE_TLV_FW_DBG_DEST 38 1098#define IWM_UCODE_TLV_FW_DBG_CONF 39 1099#define IWM_UCODE_TLV_FW_DBG_TRIGGER 40 1100#define IWM_UCODE_TLV_CMD_VERSIONS 48 1101#define IWM_UCODE_TLV_FW_GSCAN_CAPA 50 1102#define IWM_UCODE_TLV_FW_MEM_SEG 51 1103#define IWM_UCODE_TLV_UMAC_DEBUG_ADDRS 54 1104#define IWM_UCODE_TLV_LMAC_DEBUG_ADDRS 55 1105#define IWM_UCODE_TLV_HW_TYPE 58 1106 1107#define IWM_UCODE_TLV_DEBUG_BASE 0x1000005 1108#define IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0) 1109#define IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWM_UCODE_TLV_DEBUG_BASE + 1) 1110#define IWM_UCODE_TLV_TYPE_HCMD (IWM_UCODE_TLV_DEBUG_BASE + 2) 1111#define IWM_UCODE_TLV_TYPE_REGIONS (IWM_UCODE_TLV_DEBUG_BASE + 3) 1112#define IWM_UCODE_TLV_TYPE_TRIGGERS (IWM_UCODE_TLV_DEBUG_BASE + 4) 1113#define IWM_UCODE_TLV_DEBUG_MAX IWM_UCODE_TLV_TYPE_TRIGGERS 1114 1115struct iwm_ucode_tlv { 1116 uint32_t type; /* see above */ 1117 uint32_t length; /* not including type/length fields */ 1118 uint8_t data[0]; 1119}; 1120 1121struct iwm_ucode_api { 1122 uint32_t api_index; 1123 uint32_t api_flags; 1124} __packed; 1125 1126struct iwm_ucode_capa { 1127 uint32_t api_index; 1128 uint32_t api_capa; 1129} __packed; 1130 1131#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1132 1133struct iwm_tlv_ucode_header { 1134 /* 1135 * The TLV style ucode header is distinguished from 1136 * the v1/v2 style header by first four bytes being 1137 * zero, as such is an invalid combination of 1138 * major/minor/API/serial versions. 1139 */ 1140 uint32_t zero; 1141 uint32_t magic; 1142 uint8_t human_readable[64]; 1143 uint32_t ver; /* major/minor/API/serial */ 1144 uint32_t build; 1145 uint64_t ignore; 1146 /* 1147 * The data contained herein has a TLV layout, 1148 * see above for the TLV header and types. 1149 * Note that each TLV is padded to a length 1150 * that is a multiple of 4 for alignment. 1151 */ 1152 uint8_t data[0]; 1153}; 1154 1155/* 1156 * Registers in this file are internal, not PCI bus memory mapped. 1157 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1158 */ 1159#define IWM_PRPH_BASE (0x00000) 1160#define IWM_PRPH_END (0xFFFFF) 1161 1162/* APMG (power management) constants */ 1163#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1164#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1165#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1166#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1167#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1168#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1169#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1170#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1171#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1172#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1173#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1174 1175#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1176#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1177#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1178 1179#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1180#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1181#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1182#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1183#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1184#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1185#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1186 1187#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1188 1189#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1190 1191/* Device system time */ 1192#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1193 1194/* Device NMI register */ 1195#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1196#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1197#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1198#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1199#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1200 1201/* 1202 * Device reset for family 8000 1203 * write to bit 24 in order to reset the CPU 1204*/ 1205#define IWM_RELEASE_CPU_RESET 0x300c 1206#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1207 1208 1209/***************************************************************************** 1210 * 7000/3000 series SHR DTS addresses * 1211 *****************************************************************************/ 1212 1213#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1214#define IWM_DTSC_CFG_MODE (0x00a10604) 1215#define IWM_DTSC_VREF_AVG (0x00a10648) 1216#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1217#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1218#define IWM_DTSC_PTAT_AVG (0x00a10650) 1219 1220 1221/** 1222 * Tx Scheduler 1223 * 1224 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1225 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1226 * host DRAM. It steers each frame's Tx command (which contains the frame 1227 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1228 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1229 * but one DMA channel may take input from several queues. 1230 * 1231 * Tx DMA FIFOs have dedicated purposes. 1232 * 1233 * For 5000 series and up, they are used differently 1234 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1235 * 1236 * 0 -- EDCA BK (background) frames, lowest priority 1237 * 1 -- EDCA BE (best effort) frames, normal priority 1238 * 2 -- EDCA VI (video) frames, higher priority 1239 * 3 -- EDCA VO (voice) and management frames, highest priority 1240 * 4 -- unused 1241 * 5 -- unused 1242 * 6 -- unused 1243 * 7 -- Commands 1244 * 1245 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1246 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1247 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1248 * 1249 * The driver sets up each queue to work in one of two modes: 1250 * 1251 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1252 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1253 * contains TFDs for a unique combination of Recipient Address (RA) 1254 * and Traffic Identifier (TID), that is, traffic of a given 1255 * Quality-Of-Service (QOS) priority, destined for a single station. 1256 * 1257 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1258 * each frame within the BA window, including whether it's been transmitted, 1259 * and whether it's been acknowledged by the receiving station. The device 1260 * automatically processes block-acks received from the receiving STA, 1261 * and reschedules un-acked frames to be retransmitted (successful 1262 * Tx completion may end up being out-of-order). 1263 * 1264 * The driver must maintain the queue's Byte Count table in host DRAM 1265 * for this mode. 1266 * This mode does not support fragmentation. 1267 * 1268 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1269 * The device may automatically retry Tx, but will retry only one frame 1270 * at a time, until receiving ACK from receiving station, or reaching 1271 * retry limit and giving up. 1272 * 1273 * The command queue (#4/#9) must use this mode! 1274 * This mode does not require use of the Byte Count table in host DRAM. 1275 * 1276 * Driver controls scheduler operation via 3 means: 1277 * 1) Scheduler registers 1278 * 2) Shared scheduler data base in internal SRAM 1279 * 3) Shared data in host DRAM 1280 * 1281 * Initialization: 1282 * 1283 * When loading, driver should allocate memory for: 1284 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1285 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1286 * (1024 bytes for each queue). 1287 * 1288 * After receiving "Alive" response from uCode, driver must initialize 1289 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1290 * the driver can't issue commands!): 1291 */ 1292#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1293 1294/** 1295 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1296 * can keep track of at one time when creating block-ack chains of frames. 1297 * Note that "64" matches the number of ack bits in a block-ack packet. 1298 */ 1299#define IWM_SCD_WIN_SIZE 64 1300#define IWM_SCD_FRAME_LIMIT 64 1301 1302#define IWM_SCD_TXFIFO_POS_TID (0) 1303#define IWM_SCD_TXFIFO_POS_RA (4) 1304#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1305 1306/* agn SCD */ 1307#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1308#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1309#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1310#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1311#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1312 1313#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1314#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1315#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1316#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1317#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1318#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1319#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1320#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1321#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1322#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1323 1324/* Context Data */ 1325#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1326#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1327 1328/* Tx status */ 1329#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1330#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1331 1332/* Translation Data */ 1333#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1334#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1335 1336#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1337 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1338 1339#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1340 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1341 1342#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1343 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1344 1345#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1346 1347#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1348#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1349#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1350#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1351#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1352#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1353#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1354#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1355#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1356#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1357#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1358 1359static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1360{ 1361 if (chnl < 20) 1362 return IWM_SCD_BASE + 0x18 + chnl * 4; 1363 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1364} 1365 1366static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1367{ 1368 if (chnl < 20) 1369 return IWM_SCD_BASE + 0x68 + chnl * 4; 1370 return IWM_SCD_BASE + 0x2B4 + chnl * 4; 1371} 1372 1373static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1374{ 1375 if (chnl < 20) 1376 return IWM_SCD_BASE + 0x10c + chnl * 4; 1377 return IWM_SCD_BASE + 0x334 + chnl * 4; 1378} 1379 1380/*********************** END TX SCHEDULER *************************************/ 1381 1382/* Oscillator clock */ 1383#define IWM_OSC_CLK (0xa04068) 1384#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1385 1386/****************************/ 1387/* Flow Handler Definitions */ 1388/****************************/ 1389 1390/** 1391 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1392 * Addresses are offsets from device's PCI hardware base address. 1393 */ 1394#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1395#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1396 1397/** 1398 * Keep-Warm (KW) buffer base address. 1399 * 1400 * Driver must allocate a 4KByte buffer that is for keeping the 1401 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1402 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1403 * from going into a power-savings mode that would cause higher DRAM latency, 1404 * and possible data over/under-runs, before all Tx/Rx is complete. 1405 * 1406 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1407 * of the buffer, which must be 4K aligned. Once this is set up, the device 1408 * automatically invokes keep-warm accesses when normal accesses might not 1409 * be sufficient to maintain fast DRAM response. 1410 * 1411 * Bit fields: 1412 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1413 */ 1414#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1415 1416 1417/** 1418 * TFD Circular Buffers Base (CBBC) addresses 1419 * 1420 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1421 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1422 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1423 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1424 * aligned (address bits 0-7 must be 0). 1425 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1426 * for them are in different places. 1427 * 1428 * Bit fields in each pointer register: 1429 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1430 */ 1431#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1432#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1433#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1434#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1435#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1436#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1437 1438/* Find TFD CB base pointer for given queue */ 1439static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1440{ 1441 if (chnl < 16) 1442 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1443 if (chnl < 20) 1444 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1445 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1446} 1447 1448 1449/** 1450 * Rx SRAM Control and Status Registers (RSCSR) 1451 * 1452 * These registers provide handshake between driver and device for the Rx queue 1453 * (this queue handles *all* command responses, notifications, Rx data, etc. 1454 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1455 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1456 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1457 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1458 * mapping between RBDs and RBs. 1459 * 1460 * Driver must allocate host DRAM memory for the following, and set the 1461 * physical address of each into device registers: 1462 * 1463 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1464 * entries (although any power of 2, up to 4096, is selectable by driver). 1465 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1466 * (typically 4K, although 8K or 16K are also selectable by driver). 1467 * Driver sets up RB size and number of RBDs in the CB via Rx config 1468 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1469 * 1470 * Bit fields within one RBD: 1471 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1472 * 1473 * Driver sets physical address [35:8] of base of RBD circular buffer 1474 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1475 * 1476 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1477 * (RBs) have been filled, via a "write pointer", actually the index of 1478 * the RB's corresponding RBD within the circular buffer. Driver sets 1479 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1480 * 1481 * Bit fields in lower dword of Rx status buffer (upper dword not used 1482 * by driver: 1483 * 31-12: Not used by driver 1484 * 11- 0: Index of last filled Rx buffer descriptor 1485 * (device writes, driver reads this value) 1486 * 1487 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1488 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1489 * and update the device's "write" index register, 1490 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1491 * 1492 * This "write" index corresponds to the *next* RBD that the driver will make 1493 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1494 * the circular buffer. This value should initially be 0 (before preparing any 1495 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1496 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1497 * "read" index has advanced past 1! See below). 1498 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1499 * 1500 * As the device fills RBs (referenced from contiguous RBDs within the circular 1501 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1502 * to tell the driver the index of the latest filled RBD. The driver must 1503 * read this "read" index from DRAM after receiving an Rx interrupt from device 1504 * 1505 * The driver must also internally keep track of a third index, which is the 1506 * next RBD to process. When receiving an Rx interrupt, driver should process 1507 * all filled but unprocessed RBs up to, but not including, the RB 1508 * corresponding to the "read" index. For example, if "read" index becomes "1", 1509 * driver may process the RB pointed to by RBD 0. Depending on volume of 1510 * traffic, there may be many RBs to process. 1511 * 1512 * If read index == write index, device thinks there is no room to put new data. 1513 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1514 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1515 * and "read" indexes; that is, make sure that there are no more than 254 1516 * buffers waiting to be filled. 1517 */ 1518#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1519#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1520#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1521 1522/** 1523 * Physical base address of 8-byte Rx Status buffer. 1524 * Bit fields: 1525 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1526 */ 1527#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1528 1529/** 1530 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1531 * Bit fields: 1532 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1533 */ 1534#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1535 1536/** 1537 * Rx write pointer (index, really!). 1538 * Bit fields: 1539 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1540 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1541 */ 1542#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1543#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1544 1545#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1546#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1547 1548/** 1549 * Rx Config/Status Registers (RCSR) 1550 * Rx Config Reg for channel 0 (only channel used) 1551 * 1552 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1553 * normal operation (see bit fields). 1554 * 1555 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1556 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1557 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1558 * 1559 * Bit fields: 1560 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1561 * '10' operate normally 1562 * 29-24: reserved 1563 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1564 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1565 * 19-18: reserved 1566 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1567 * '10' 12K, '11' 16K. 1568 * 15-14: reserved 1569 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1570 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1571 * typical value 0x10 (about 1/2 msec) 1572 * 3- 0: reserved 1573 */ 1574#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1575#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1576#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1577 1578#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1579#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1580#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1581 1582#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1583#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1584#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1585#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1586#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1587#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1588 1589#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1590#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1591#define IWM_RX_RB_TIMEOUT (0x11) 1592 1593#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1594#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1595#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1596 1597#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1598#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1599#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1600#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1601 1602#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1603#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1604#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1605 1606/** 1607 * Rx Shared Status Registers (RSSR) 1608 * 1609 * After stopping Rx DMA channel (writing 0 to 1610 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1611 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1612 * 1613 * Bit fields: 1614 * 24: 1 = Channel 0 is idle 1615 * 1616 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1617 * contain default values that should not be altered by the driver. 1618 */ 1619#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1620#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1621 1622#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1623#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1624#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1625 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1626 1627#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1628 1629#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1630 1631/* TFDB Area - TFDs buffer table */ 1632#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1633#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1634#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1635#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1636#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1637 1638/** 1639 * Transmit DMA Channel Control/Status Registers (TCSR) 1640 * 1641 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1642 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1643 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1644 * 1645 * To use a Tx DMA channel, driver must initialize its 1646 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1647 * 1648 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1649 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1650 * 1651 * All other bits should be 0. 1652 * 1653 * Bit fields: 1654 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1655 * '10' operate normally 1656 * 29- 4: Reserved, set to "0" 1657 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1658 * 2- 0: Reserved, set to "0" 1659 */ 1660#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1661#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1662 1663/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1664#define IWM_FH_TCSR_CHNL_NUM (8) 1665 1666/* TCSR: tx_config register values */ 1667#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1668 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1669#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1670 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1671#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1672 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1673 1674#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1675#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1676 1677#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1678#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1679 1680#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1681#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1682#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1683 1684#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1685#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1686#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1687 1688#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1689#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1690#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1691 1692#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1693#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1694#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1695 1696#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1697#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1698 1699/** 1700 * Tx Shared Status Registers (TSSR) 1701 * 1702 * After stopping Tx DMA channel (writing 0 to 1703 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1704 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1705 * (channel's buffers empty | no pending requests). 1706 * 1707 * Bit fields: 1708 * 31-24: 1 = Channel buffers empty (channel 7:0) 1709 * 23-16: 1 = No pending requests (channel 7:0) 1710 */ 1711#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1712#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1713 1714#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1715 1716/** 1717 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1718 * 31: Indicates an address error when accessed to internal memory 1719 * uCode/driver must write "1" in order to clear this flag 1720 * 30: Indicates that Host did not send the expected number of dwords to FH 1721 * uCode/driver must write "1" in order to clear this flag 1722 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1723 * command was received from the scheduler while the TRB was already full 1724 * with previous command 1725 * uCode/driver must write "1" in order to clear this flag 1726 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1727 * bit is set, it indicates that the FH has received a full indication 1728 * from the RTC TxFIFO and the current value of the TxCredit counter was 1729 * not equal to zero. This mean that the credit mechanism was not 1730 * synchronized to the TxFIFO status 1731 * uCode/driver must write "1" in order to clear this flag 1732 */ 1733#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1734#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1735 1736#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1737 1738/* Tx service channels */ 1739#define IWM_FH_SRVC_CHNL (9) 1740#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1741#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1742#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1743 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1744 1745#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1746#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1747 (_chan) * 4) 1748 1749/* Instruct FH to increment the retry count of a packet when 1750 * it is brought from the memory to TX-FIFO 1751 */ 1752#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1753 1754#define IWM_RX_QUEUE_SIZE 256 1755#define IWM_RX_QUEUE_MASK 255 1756#define IWM_RX_QUEUE_SIZE_LOG 8 1757 1758/* 1759 * RX related structures and functions 1760 */ 1761#define IWM_RX_FREE_BUFFERS 64 1762#define IWM_RX_LOW_WATERMARK 8 1763 1764/** 1765 * struct iwm_rb_status - reseve buffer status 1766 * host memory mapped FH registers 1767 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1768 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1769 * @finished_rb_num [0:11] - Indicates the index of the current RB 1770 * in which the last frame was written to 1771 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1772 * which was transferred 1773 */ 1774struct iwm_rb_status { 1775 uint16_t closed_rb_num; 1776 uint16_t closed_fr_num; 1777 uint16_t finished_rb_num; 1778 uint16_t finished_fr_nam; 1779 uint32_t unused; 1780} __packed; 1781 1782 1783#define IWM_TFD_QUEUE_SIZE_MAX (256) 1784#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1785#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1786 IWM_TFD_QUEUE_SIZE_BC_DUP) 1787#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1788#define IWM_NUM_OF_TBS 20 1789 1790static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1791{ 1792 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1793} 1794/** 1795 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1796 * 1797 * This structure contains dma address and length of transmission address 1798 * 1799 * @lo: low [31:0] portion of the dma address of TX buffer 1800 * every even is unaligned on 16 bit boundary 1801 * @hi_n_len 0-3 [35:32] portion of dma 1802 * 4-15 length of the tx buffer 1803 */ 1804struct iwm_tfd_tb { 1805 uint32_t lo; 1806 uint16_t hi_n_len; 1807} __packed; 1808 1809/** 1810 * struct iwm_tfd 1811 * 1812 * Transmit Frame Descriptor (TFD) 1813 * 1814 * @ __reserved1[3] reserved 1815 * @ num_tbs 0-4 number of active tbs 1816 * 5 reserved 1817 * 6-7 padding (not used) 1818 * @ tbs[20] transmit frame buffer descriptors 1819 * @ __pad padding 1820 * 1821 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1822 * Both driver and device share these circular buffers, each of which must be 1823 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1824 * 1825 * Driver must indicate the physical address of the base of each 1826 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1827 * 1828 * Each TFD contains pointer/size information for up to 20 data buffers 1829 * in host DRAM. These buffers collectively contain the (one) frame described 1830 * by the TFD. Each buffer must be a single contiguous block of memory within 1831 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1832 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1833 * Tx frame, up to 8 KBytes in size. 1834 * 1835 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1836 */ 1837struct iwm_tfd { 1838 uint8_t __reserved1[3]; 1839 uint8_t num_tbs; 1840 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1841 uint32_t __pad; 1842} __packed; 1843 1844/* Keep Warm Size */ 1845#define IWM_KW_SIZE 0x1000 /* 4k */ 1846 1847/* Fixed (non-configurable) rx data from phy */ 1848 1849/** 1850 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1851 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1852 * @tfd_offset 0-12 - tx command byte count 1853 * 12-16 - station index 1854 */ 1855struct iwm_agn_scd_bc_tbl { 1856 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1857} __packed; 1858 1859#define IWM_TX_CRC_SIZE 4 1860#define IWM_TX_DELIMITER_SIZE 4 1861 1862/* Maximum number of Tx queues. */ 1863#define IWM_MAX_QUEUES 31 1864 1865/** 1866 * DQA - Dynamic Queue Allocation -introduction 1867 * 1868 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1869 * to allow dynamic allocation of queues on-demand, rather than allocate them 1870 * statically ahead of time. Ideally, we would like to allocate one queue 1871 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1872 * even if it also needs to send traffic to a sleeping STA1, without being 1873 * blocked by the sleeping station. 1874 * 1875 * Although the queues in DQA mode are dynamically allocated, there are still 1876 * some queues that are statically allocated: 1877 * TXQ #0 - command queue 1878 * TXQ #1 - aux frames 1879 * TXQ #2 - P2P device frames 1880 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames 1881 * TXQ #4 - BSS DATA frames queue 1882 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool 1883 * TXQ #9 - P2P GO/SoftAP probe responses 1884 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation) 1885 */ 1886 1887/* static DQA Tx queue numbers */ 1888#define IWM_DQA_CMD_QUEUE 0 1889#define IWM_DQA_AUX_QUEUE 1 1890#define IWM_DQA_P2P_DEVICE_QUEUE 2 1891#define IWM_DQA_INJECT_MONITOR_QUEUE 2 1892#define IWM_DQA_GCAST_QUEUE 3 1893#define IWM_DQA_BSS_CLIENT_QUEUE 4 1894#define IWM_DQA_MIN_MGMT_QUEUE 5 1895#define IWM_DQA_MAX_MGMT_QUEUE 8 1896#define IWM_DQA_AP_PROBE_RESP_QUEUE 9 1897#define IWM_DQA_MIN_DATA_QUEUE 10 1898#define IWM_DQA_MAX_DATA_QUEUE 31 1899 1900/* Reserve 8 DQA Tx queues, from 10 up to 17, for A-MPDU aggregation. */ 1901#define IWM_MAX_TID_COUNT 8 1902#define IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE 1903#define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1) 1904 1905/* legacy non-DQA queues; the legacy command queue uses a different number! */ 1906#define IWM_OFFCHANNEL_QUEUE 8 1907#define IWM_CMD_QUEUE 9 1908#define IWM_AUX_QUEUE 15 1909 1910#define IWM_TX_FIFO_BK 0 1911#define IWM_TX_FIFO_BE 1 1912#define IWM_TX_FIFO_VI 2 1913#define IWM_TX_FIFO_VO 3 1914#define IWM_TX_FIFO_MCAST 5 1915#define IWM_TX_FIFO_CMD 7 1916 1917#define IWM_STATION_COUNT 16 1918 1919/* 1920 * Commands 1921 */ 1922#define IWM_ALIVE 0x1 1923#define IWM_REPLY_ERROR 0x2 1924#define IWM_INIT_COMPLETE_NOTIF 0x4 1925 1926/* PHY context commands */ 1927#define IWM_PHY_CONTEXT_CMD 0x8 1928#define IWM_DBG_CFG 0x9 1929 1930/* UMAC scan commands */ 1931#define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1932#define IWM_SCAN_CFG_CMD 0xc 1933#define IWM_SCAN_REQ_UMAC 0xd 1934#define IWM_SCAN_ABORT_UMAC 0xe 1935#define IWM_SCAN_COMPLETE_UMAC 0xf 1936 1937/* station table */ 1938#define IWM_ADD_STA_KEY 0x17 1939#define IWM_ADD_STA 0x18 1940#define IWM_REMOVE_STA 0x19 1941 1942/* TX */ 1943#define IWM_TX_CMD 0x1c 1944#define IWM_TXPATH_FLUSH 0x1e 1945#define IWM_MGMT_MCAST_KEY 0x1f 1946 1947/* scheduler config */ 1948#define IWM_SCD_QUEUE_CFG 0x1d 1949 1950/* global key */ 1951#define IWM_WEP_KEY 0x20 1952 1953/* MAC and Binding commands */ 1954#define IWM_MAC_CONTEXT_CMD 0x28 1955#define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1956#define IWM_TIME_EVENT_NOTIFICATION 0x2a 1957#define IWM_BINDING_CONTEXT_CMD 0x2b 1958#define IWM_TIME_QUOTA_CMD 0x2c 1959#define IWM_NON_QOS_TX_COUNTER_CMD 0x2d 1960 1961#define IWM_LQ_CMD 0x4e 1962 1963/* Calibration */ 1964#define IWM_TEMPERATURE_NOTIFICATION 0x62 1965#define IWM_CALIBRATION_CFG_CMD 0x65 1966#define IWM_CALIBRATION_RES_NOTIFICATION 0x66 1967#define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1968#define IWM_RADIO_VERSION_NOTIFICATION 0x68 1969 1970/* paging block to FW cpu2 */ 1971#define IWM_FW_PAGING_BLOCK_CMD 0x4f 1972 1973/* Scan offload */ 1974#define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51 1975#define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52 1976#define IWM_HOT_SPOT_CMD 0x53 1977#define IWM_SCAN_OFFLOAD_COMPLETE 0x6d 1978#define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e 1979#define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f 1980#define IWM_MATCH_FOUND_NOTIFICATION 0xd9 1981#define IWM_SCAN_ITERATION_COMPLETE 0xe7 1982 1983/* Phy */ 1984#define IWM_PHY_CONFIGURATION_CMD 0x6a 1985#define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b 1986#define IWM_PHY_DB_CMD 0x6c 1987 1988/* Power - legacy power table command */ 1989#define IWM_POWER_TABLE_CMD 0x77 1990#define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1991#define IWM_LTR_CONFIG 0xee 1992 1993/* Thermal Throttling*/ 1994#define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e 1995 1996/* NVM */ 1997#define IWM_NVM_ACCESS_CMD 0x88 1998 1999#define IWM_SET_CALIB_DEFAULT_CMD 0x8e 2000 2001#define IWM_BEACON_NOTIFICATION 0x90 2002#define IWM_BEACON_TEMPLATE_CMD 0x91 2003#define IWM_TX_ANT_CONFIGURATION_CMD 0x98 2004#define IWM_BT_CONFIG 0x9b 2005#define IWM_STATISTICS_NOTIFICATION 0x9d 2006#define IWM_REDUCE_TX_POWER_CMD 0x9f 2007 2008/* RF-KILL commands and notifications */ 2009#define IWM_CARD_STATE_CMD 0xa0 2010#define IWM_CARD_STATE_NOTIFICATION 0xa1 2011 2012#define IWM_MISSED_BEACONS_NOTIFICATION 0xa2 2013 2014#define IWM_MFUART_LOAD_NOTIFICATION 0xb1 2015 2016/* Power - new power table command */ 2017#define IWM_MAC_PM_POWER_TABLE 0xa9 2018 2019#define IWM_REPLY_RX_PHY_CMD 0xc0 2020#define IWM_REPLY_RX_MPDU_CMD 0xc1 2021#define IWM_BA_NOTIF 0xc5 2022 2023/* Location Aware Regulatory */ 2024#define IWM_MCC_UPDATE_CMD 0xc8 2025#define IWM_MCC_CHUB_UPDATE_CMD 0xc9 2026 2027/* BT Coex */ 2028#define IWM_BT_COEX_PRIO_TABLE 0xcc 2029#define IWM_BT_COEX_PROT_ENV 0xcd 2030#define IWM_BT_PROFILE_NOTIFICATION 0xce 2031#define IWM_BT_COEX_CI 0x5d 2032 2033#define IWM_REPLY_SF_CFG_CMD 0xd1 2034#define IWM_REPLY_BEACON_FILTERING_CMD 0xd2 2035 2036/* DTS measurements */ 2037#define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 2038#define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd 2039 2040#define IWM_REPLY_DEBUG_CMD 0xf0 2041#define IWM_DEBUG_LOG_MSG 0xf7 2042 2043#define IWM_MCAST_FILTER_CMD 0xd0 2044 2045/* D3 commands/notifications */ 2046#define IWM_D3_CONFIG_CMD 0xd3 2047#define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4 2048#define IWM_OFFLOADS_QUERY_CMD 0xd5 2049#define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6 2050 2051/* for WoWLAN in particular */ 2052#define IWM_WOWLAN_PATTERNS 0xe0 2053#define IWM_WOWLAN_CONFIGURATION 0xe1 2054#define IWM_WOWLAN_TSC_RSC_PARAM 0xe2 2055#define IWM_WOWLAN_TKIP_PARAM 0xe3 2056#define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4 2057#define IWM_WOWLAN_GET_STATUSES 0xe5 2058#define IWM_WOWLAN_TX_POWER_PER_DB 0xe6 2059 2060/* and for NetDetect */ 2061#define IWM_NET_DETECT_CONFIG_CMD 0x54 2062#define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56 2063#define IWM_NET_DETECT_PROFILES_CMD 0x57 2064#define IWM_NET_DETECT_HOTSPOTS_CMD 0x58 2065#define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 2066 2067/* system group command IDs */ 2068#define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 2069 2070#define IWM_REPLY_MAX 0xff 2071 2072/* PHY_OPS subcommand IDs */ 2073#define IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 2074#define IWM_CTDP_CONFIG_CMD 0x03 2075#define IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04 2076#define IWM_CT_KILL_NOTIFICATION 0xFE 2077#define IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 2078 2079/* command groups */ 2080#define IWM_LEGACY_GROUP 0x0 2081#define IWM_LONG_GROUP 0x1 2082#define IWM_SYSTEM_GROUP 0x2 2083#define IWM_MAC_CONF_GROUP 0x3 2084#define IWM_PHY_OPS_GROUP 0x4 2085#define IWM_DATA_PATH_GROUP 0x5 2086#define IWM_PROT_OFFLOAD_GROUP 0xb 2087 2088/* SYSTEM_GROUP group subcommand IDs */ 2089 2090#define IWM_SHARED_MEM_CFG_CMD 0x00 2091#define IWM_SOC_CONFIGURATION_CMD 0x01 2092#define IWM_INIT_EXTENDED_CFG_CMD 0x03 2093#define IWM_FW_ERROR_RECOVERY_CMD 0x07 2094 2095/* DATA_PATH group subcommand IDs */ 2096#define IWM_DQA_ENABLE_CMD 0x00 2097 2098/* 2099 * struct iwm_dqa_enable_cmd 2100 * @cmd_queue: the TXQ number of the command queue 2101 */ 2102struct iwm_dqa_enable_cmd { 2103 uint32_t cmd_queue; 2104} __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 2105 2106/** 2107 * struct iwm_cmd_response - generic response struct for most commands 2108 * @status: status of the command asked, changes for each one 2109 */ 2110struct iwm_cmd_response { 2111 uint32_t status; 2112}; 2113 2114/* 2115 * struct iwm_tx_ant_cfg_cmd 2116 * @valid: valid antenna configuration 2117 */ 2118struct iwm_tx_ant_cfg_cmd { 2119 uint32_t valid; 2120} __packed; 2121 2122/** 2123 * struct iwm_reduce_tx_power_cmd - TX power reduction command 2124 * IWM_REDUCE_TX_POWER_CMD = 0x9f 2125 * @flags: (reserved for future implementation) 2126 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 2127 * @pwr_restriction: TX power restriction in dBms. 2128 */ 2129struct iwm_reduce_tx_power_cmd { 2130 uint8_t flags; 2131 uint8_t mac_context_id; 2132 uint16_t pwr_restriction; 2133} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 2134 2135/* 2136 * Calibration control struct. 2137 * Sent as part of the phy configuration command. 2138 * @flow_trigger: bitmap for which calibrations to perform according to 2139 * flow triggers. 2140 * @event_trigger: bitmap for which calibrations to perform according to 2141 * event triggers. 2142 */ 2143struct iwm_calib_ctrl { 2144 uint32_t flow_trigger; 2145 uint32_t event_trigger; 2146} __packed; 2147 2148/* This defines the bitmap of various calibrations to enable in both 2149 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 2150 */ 2151#define IWM_CALIB_CFG_XTAL_IDX (1 << 0) 2152#define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 2153#define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 2154#define IWM_CALIB_CFG_PAPD_IDX (1 << 3) 2155#define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4) 2156#define IWM_CALIB_CFG_DC_IDX (1 << 5) 2157#define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6) 2158#define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 2159#define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8) 2160#define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 2161#define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10) 2162#define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 2163#define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 2164#define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 2165#define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 2166#define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 2167#define IWM_CALIB_CFG_DAC_IDX (1 << 16) 2168#define IWM_CALIB_CFG_ABS_IDX (1 << 17) 2169#define IWM_CALIB_CFG_AGC_IDX (1 << 18) 2170 2171/* 2172 * Phy configuration command. 2173 */ 2174struct iwm_phy_cfg_cmd { 2175 uint32_t phy_cfg; 2176 struct iwm_calib_ctrl calib_control; 2177} __packed; 2178 2179#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2180#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2181#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2182#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2183#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2184#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2185#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2186#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2187#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2188#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2189 2190#define IWM_MAX_DTS_TRIPS 8 2191 2192/** 2193 * struct iwm_ct_kill_notif - CT-kill entry notification 2194 * 2195 * @temperature: the current temperature in celsius 2196 * @reserved: reserved 2197 */ 2198struct iwm_ct_kill_notif { 2199 uint16_t temperature; 2200 uint16_t reserved; 2201} __packed; /* GRP_PHY_CT_KILL_NTF */ 2202 2203/** 2204 * struct iwm_temp_report_ths_cmd - set temperature thresholds 2205 * (IWM_TEMP_REPORTING_THRESHOLDS_CMD) 2206 * 2207 * @num_temps: number of temperature thresholds passed 2208 * @thresholds: array with the thresholds to be configured 2209 */ 2210struct iwm_temp_report_ths_cmd { 2211 uint32_t num_temps; 2212 uint16_t thresholds[IWM_MAX_DTS_TRIPS]; 2213} __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 2214 2215/* 2216 * PHY db 2217 */ 2218 2219#define IWM_PHY_DB_CFG 1 2220#define IWM_PHY_DB_CALIB_NCH 2 2221#define IWM_PHY_DB_UNUSED 3 2222#define IWM_PHY_DB_CALIB_CHG_PAPD 4 2223#define IWM_PHY_DB_CALIB_CHG_TXP 5 2224#define IWM_PHY_DB_MAX 6 2225 2226/* 2227 * phy db - configure operational ucode 2228 */ 2229struct iwm_phy_db_cmd { 2230 uint16_t type; 2231 uint16_t length; 2232 uint8_t data[]; 2233} __packed; 2234 2235/* for parsing of tx power channel group data that comes from the firmware*/ 2236struct iwm_phy_db_chg_txp { 2237 uint32_t space; 2238 uint16_t max_channel_idx; 2239} __packed; 2240 2241/* 2242 * phy db - Receive phy db chunk after calibrations 2243 */ 2244struct iwm_calib_res_notif_phy_db { 2245 uint16_t type; 2246 uint16_t length; 2247 uint8_t data[]; 2248} __packed; 2249 2250/* 7k family NVM HW-Section offset (in words) definitions */ 2251#define IWM_HW_ADDR 0x15 2252/* 7k family NVM SW-Section offset (in words) definitions */ 2253#define IWM_NVM_SW_SECTION 0x1C0 2254#define IWM_NVM_VERSION 0 2255#define IWM_RADIO_CFG 1 2256#define IWM_SKU 2 2257#define IWM_N_HW_ADDRS 3 2258#define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION 2259/* 7k family NVM calibration section offset (in words) definitions */ 2260#define IWM_NVM_CALIB_SECTION 0x2B8 2261#define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION) 2262 2263/* 8k family NVM HW-Section offset (in words) definitions */ 2264#define IWM_HW_ADDR0_WFPM_8000 0x12 2265#define IWM_HW_ADDR1_WFPM_8000 0x16 2266#define IWM_HW_ADDR0_PCIE_8000 0x8A 2267#define IWM_HW_ADDR1_PCIE_8000 0x8E 2268#define IWM_MAC_ADDRESS_OVERRIDE_8000 1 2269 2270/* 8k family NVM SW-Section offset (in words) definitions */ 2271#define IWM_NVM_SW_SECTION_8000 0x1C0 2272#define IWM_NVM_VERSION_8000 0 2273#define IWM_RADIO_CFG_8000 0 2274#define IWM_SKU_8000 2 2275#define IWM_N_HW_ADDRS_8000 3 2276 2277/* 8k family NVM REGULATORY -Section offset (in words) definitions */ 2278#define IWM_NVM_CHANNELS_8000 0 2279#define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7 2280#define IWM_NVM_LAR_OFFSET_8000 0x507 2281#define IWM_NVM_LAR_ENABLED_8000 0x7 2282 2283/* 8k family NVM calibration section offset (in words) definitions */ 2284#define IWM_NVM_CALIB_SECTION_8000 0x2B8 2285#define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000) 2286 2287/* SKU Capabilities (actual values from NVM definition) */ 2288#define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0) 2289#define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1) 2290#define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2) 2291#define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3) 2292#define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5) 2293 2294/* radio config bits (actual values from NVM definition) */ 2295#define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 2296#define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 2297#define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 2298#define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 2299#define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 2300#define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 2301 2302#define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF) 2303#define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 2304#define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 2305#define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 2306#define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 2307#define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 2308 2309/* 2310 * channel flags in NVM 2311 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2312 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 2313 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 2314 * @IWM_NVM_CHANNEL_RADAR: radar detection required 2315 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 2316 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2317 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2318 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2319 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2320 */ 2321#define IWM_NVM_CHANNEL_VALID (1 << 0) 2322#define IWM_NVM_CHANNEL_IBSS (1 << 1) 2323#define IWM_NVM_CHANNEL_ACTIVE (1 << 3) 2324#define IWM_NVM_CHANNEL_RADAR (1 << 4) 2325#define IWM_NVM_CHANNEL_DFS (1 << 7) 2326#define IWM_NVM_CHANNEL_WIDE (1 << 8) 2327#define IWM_NVM_CHANNEL_40MHZ (1 << 9) 2328#define IWM_NVM_CHANNEL_80MHZ (1 << 10) 2329#define IWM_NVM_CHANNEL_160MHZ (1 << 11) 2330 2331/* Target of the IWM_NVM_ACCESS_CMD */ 2332#define IWM_NVM_ACCESS_TARGET_CACHE 0 2333#define IWM_NVM_ACCESS_TARGET_OTP 1 2334#define IWM_NVM_ACCESS_TARGET_EEPROM 2 2335 2336/* Section types for IWM_NVM_ACCESS_CMD */ 2337#define IWM_NVM_SECTION_TYPE_HW 0 2338#define IWM_NVM_SECTION_TYPE_SW 1 2339#define IWM_NVM_SECTION_TYPE_PAPD 2 2340#define IWM_NVM_SECTION_TYPE_REGULATORY 3 2341#define IWM_NVM_SECTION_TYPE_CALIBRATION 4 2342#define IWM_NVM_SECTION_TYPE_PRODUCTION 5 2343#define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6 2344/* 7 unknown */ 2345#define IWM_NVM_SECTION_TYPE_REGULATORY_SDP 8 2346/* 9 unknown */ 2347#define IWM_NVM_SECTION_TYPE_HW_8000 10 2348#define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11 2349#define IWM_NVM_SECTION_TYPE_PHY_SKU 12 2350#define IWM_NVM_NUM_OF_SECTIONS 13 2351 2352/** 2353 * enum iwm_nvm_type - nvm formats 2354 * @IWM_NVM: the regular format 2355 * @IWM_NVM_EXT: extended NVM format 2356 * @IWM_NVM_SDP: NVM format used by 3168 series 2357 */ 2358enum iwm_nvm_type { 2359 IWM_NVM, 2360 IWM_NVM_EXT, 2361 IWM_NVM_SDP, 2362}; 2363 2364/** 2365 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2366 * @op_code: 0 - read, 1 - write 2367 * @target: IWM_NVM_ACCESS_TARGET_* 2368 * @type: IWM_NVM_SECTION_TYPE_* 2369 * @offset: offset in bytes into the section 2370 * @length: in bytes, to read/write 2371 * @data: if write operation, the data to write. On read its empty 2372 */ 2373struct iwm_nvm_access_cmd { 2374 uint8_t op_code; 2375 uint8_t target; 2376 uint16_t type; 2377 uint16_t offset; 2378 uint16_t length; 2379 uint8_t data[]; 2380} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2381 2382/* 2383 * Block paging calculations 2384 */ 2385#define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */ 2386#define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */ 2387#define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3 2388/* 8 pages per group */ 2389#define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE) 2390/* don't change, support only 32KB size */ 2391#define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE) 2392/* 32K == 2^15 */ 2393#define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE) 2394 2395/* 2396 * Image paging calculations 2397 */ 2398#define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5 2399/* 2^5 == 32 blocks per image */ 2400#define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE) 2401/* maximum image size 1024KB */ 2402#define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE) 2403 2404/* Virtual address signature */ 2405#define IWM_PAGING_ADDR_SIG 0xAA000000 2406 2407#define IWM_PAGING_CMD_IS_SECURED (1 << 9) 2408#define IWM_PAGING_CMD_IS_ENABLED (1 << 8) 2409#define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0 2410#define IWM_PAGING_TLV_SECURE_MASK 1 2411 2412#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2413 2414/* 2415 * struct iwm_fw_paging_cmd - paging layout 2416 * 2417 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2418 * 2419 * Send to FW the paging layout in the driver. 2420 * 2421 * @flags: various flags for the command 2422 * @block_size: the block size in powers of 2 2423 * @block_num: number of blocks specified in the command. 2424 * @device_phy_addr: virtual addresses from device side 2425*/ 2426struct iwm_fw_paging_cmd { 2427 uint32_t flags; 2428 uint32_t block_size; 2429 uint32_t block_num; 2430 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2431} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2432 2433/** 2434 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2435 * @offset: offset in bytes into the section 2436 * @length: in bytes, either how much was written or read 2437 * @type: IWM_NVM_SECTION_TYPE_* 2438 * @status: 0 for success, fail otherwise 2439 * @data: if read operation, the data returned. Empty on write. 2440 */ 2441struct iwm_nvm_access_resp { 2442 uint16_t offset; 2443 uint16_t length; 2444 uint16_t type; 2445 uint16_t status; 2446 uint8_t data[]; 2447} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2448 2449/* IWM_ALIVE 0x1 */ 2450 2451/* alive response is_valid values */ 2452#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2453#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2454 2455/* alive response ver_type values */ 2456#define IWM_FW_TYPE_HW 0 2457#define IWM_FW_TYPE_PROT 1 2458#define IWM_FW_TYPE_AP 2 2459#define IWM_FW_TYPE_WOWLAN 3 2460#define IWM_FW_TYPE_TIMING 4 2461#define IWM_FW_TYPE_WIPAN 5 2462 2463/* alive response ver_subtype values */ 2464#define IWM_FW_SUBTYPE_FULL_FEATURE 0 2465#define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */ 2466#define IWM_FW_SUBTYPE_REDUCED 2 2467#define IWM_FW_SUBTYPE_ALIVE_ONLY 3 2468#define IWM_FW_SUBTYPE_WOWLAN 4 2469#define IWM_FW_SUBTYPE_AP_SUBTYPE 5 2470#define IWM_FW_SUBTYPE_WIPAN 6 2471#define IWM_FW_SUBTYPE_INITIALIZE 9 2472 2473#define IWM_ALIVE_STATUS_ERR 0xDEAD 2474#define IWM_ALIVE_STATUS_OK 0xCAFE 2475 2476#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2477 2478struct iwm_alive_resp_v1 { 2479 uint16_t status; 2480 uint16_t flags; 2481 uint8_t ucode_minor; 2482 uint8_t ucode_major; 2483 uint16_t id; 2484 uint8_t api_minor; 2485 uint8_t api_major; 2486 uint8_t ver_subtype; 2487 uint8_t ver_type; 2488 uint8_t mac; 2489 uint8_t opt; 2490 uint16_t reserved2; 2491 uint32_t timestamp; 2492 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2493 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2494 uint32_t cpu_register_ptr; 2495 uint32_t dbgm_config_ptr; 2496 uint32_t alive_counter_ptr; 2497 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2498} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2499 2500struct iwm_alive_resp_v2 { 2501 uint16_t status; 2502 uint16_t flags; 2503 uint8_t ucode_minor; 2504 uint8_t ucode_major; 2505 uint16_t id; 2506 uint8_t api_minor; 2507 uint8_t api_major; 2508 uint8_t ver_subtype; 2509 uint8_t ver_type; 2510 uint8_t mac; 2511 uint8_t opt; 2512 uint16_t reserved2; 2513 uint32_t timestamp; 2514 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2515 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2516 uint32_t cpu_register_ptr; 2517 uint32_t dbgm_config_ptr; 2518 uint32_t alive_counter_ptr; 2519 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2520 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2521 uint32_t st_fwrd_size; 2522 uint8_t umac_minor; /* UMAC version: minor */ 2523 uint8_t umac_major; /* UMAC version: major */ 2524 uint16_t umac_id; /* UMAC version: id */ 2525 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2526 uint32_t dbg_print_buff_addr; 2527} __packed; /* ALIVE_RES_API_S_VER_2 */ 2528 2529struct iwm_alive_resp_v3 { 2530 uint16_t status; 2531 uint16_t flags; 2532 uint32_t ucode_minor; 2533 uint32_t ucode_major; 2534 uint8_t ver_subtype; 2535 uint8_t ver_type; 2536 uint8_t mac; 2537 uint8_t opt; 2538 uint32_t timestamp; 2539 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2540 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2541 uint32_t cpu_register_ptr; 2542 uint32_t dbgm_config_ptr; 2543 uint32_t alive_counter_ptr; 2544 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2545 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2546 uint32_t st_fwrd_size; 2547 uint32_t umac_minor; /* UMAC version: minor */ 2548 uint32_t umac_major; /* UMAC version: major */ 2549 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2550 uint32_t dbg_print_buff_addr; 2551} __packed; /* ALIVE_RES_API_S_VER_3 */ 2552 2553#define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 2554#define IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 2555 2556#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 2557#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 2558#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1 2559#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 2560#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 2561 2562/** 2563 * struct iwm_soc_configuration_cmd - Set device stabilization latency 2564 * 2565 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 2566 * flag, because the FW treats the whole value as an integer. In 2567 * VER_2, we can set the bits independently. 2568 * @latency: time for SOC to ensure stable power & XTAL 2569 */ 2570struct iwm_soc_configuration_cmd { 2571 uint32_t flags; 2572 uint32_t latency; 2573} __packed; /* 2574 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 2575 * SOC_CONFIGURATION_CMD_S_VER_2 2576 */ 2577 2578 2579/* Error response/notification */ 2580#define IWM_FW_ERR_UNKNOWN_CMD 0x0 2581#define IWM_FW_ERR_INVALID_CMD_PARAM 0x1 2582#define IWM_FW_ERR_SERVICE 0x2 2583#define IWM_FW_ERR_ARC_MEMORY 0x3 2584#define IWM_FW_ERR_ARC_CODE 0x4 2585#define IWM_FW_ERR_WATCH_DOG 0x5 2586#define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10 2587#define IWM_FW_ERR_WEP_KEY_SIZE 0x11 2588#define IWM_FW_ERR_OBSOLETE_FUNC 0x12 2589#define IWM_FW_ERR_UNEXPECTED 0xFE 2590#define IWM_FW_ERR_FATAL 0xFF 2591 2592/** 2593 * struct iwm_error_resp - FW error indication 2594 * ( IWM_REPLY_ERROR = 0x2 ) 2595 * @error_type: one of IWM_FW_ERR_* 2596 * @cmd_id: the command ID for which the error occurred 2597 * @bad_cmd_seq_num: sequence number of the erroneous command 2598 * @error_service: which service created the error, applicable only if 2599 * error_type = 2, otherwise 0 2600 * @timestamp: TSF in usecs. 2601 */ 2602struct iwm_error_resp { 2603 uint32_t error_type; 2604 uint8_t cmd_id; 2605 uint8_t reserved1; 2606 uint16_t bad_cmd_seq_num; 2607 uint32_t error_service; 2608 uint64_t timestamp; 2609} __packed; 2610 2611#define IWM_FW_CMD_VER_UNKNOWN 99 2612 2613/** 2614 * struct iwm_fw_cmd_version - firmware command version entry 2615 * @cmd: command ID 2616 * @group: group ID 2617 * @cmd_ver: command version 2618 * @notif_ver: notification version 2619 */ 2620struct iwm_fw_cmd_version { 2621 uint8_t cmd; 2622 uint8_t group; 2623 uint8_t cmd_ver; 2624 uint8_t notif_ver; 2625} __packed; 2626 2627 2628/* Common PHY, MAC and Bindings definitions */ 2629 2630#define IWM_MAX_MACS_IN_BINDING (3) 2631#define IWM_MAX_BINDINGS (4) 2632#define IWM_AUX_BINDING_INDEX (3) 2633#define IWM_MAX_PHYS (4) 2634 2635/* Used to extract ID and color from the context dword */ 2636#define IWM_FW_CTXT_ID_POS (0) 2637#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2638#define IWM_FW_CTXT_COLOR_POS (8) 2639#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2640#define IWM_FW_CTXT_INVALID (0xffffffff) 2641 2642#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2643 (_color << IWM_FW_CTXT_COLOR_POS)) 2644 2645/* Possible actions on PHYs, MACs and Bindings */ 2646#define IWM_FW_CTXT_ACTION_STUB 0 2647#define IWM_FW_CTXT_ACTION_ADD 1 2648#define IWM_FW_CTXT_ACTION_MODIFY 2 2649#define IWM_FW_CTXT_ACTION_REMOVE 3 2650#define IWM_FW_CTXT_ACTION_NUM 4 2651/* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2652 2653/* Time Events */ 2654 2655/* Time Event types, according to MAC type */ 2656 2657/* BSS Station Events */ 2658#define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2659#define IWM_TE_BSS_STA_ASSOC 1 2660#define IWM_TE_BSS_EAP_DHCP_PROT 2 2661#define IWM_TE_BSS_QUIET_PERIOD 3 2662 2663/* P2P Device Events */ 2664#define IWM_TE_P2P_DEVICE_DISCOVERABLE 4 2665#define IWM_TE_P2P_DEVICE_LISTEN 5 2666#define IWM_TE_P2P_DEVICE_ACTION_SCAN 6 2667#define IWM_TE_P2P_DEVICE_FULL_SCAN 7 2668 2669/* P2P Client Events */ 2670#define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2671#define IWM_TE_P2P_CLIENT_ASSOC 9 2672#define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10 2673 2674/* P2P GO Events */ 2675#define IWM_TE_P2P_GO_ASSOC_PROT 11 2676#define IWM_TE_P2P_GO_REPETITIVE_NOA 12 2677#define IWM_TE_P2P_GO_CT_WINDOW 13 2678 2679/* WiDi Sync Events */ 2680#define IWM_TE_WIDI_TX_SYNC 14 2681 2682#define IWM_TE_MAX 15 2683/* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2684 2685 2686 2687/* Time event - defines for command API v1 */ 2688 2689/* 2690 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2691 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2692 * the first fragment is scheduled. 2693 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2694 * the first 2 fragments are scheduled. 2695 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2696 * number of fragments are valid. 2697 * 2698 * Other than the constant defined above, specifying a fragmentation value 'x' 2699 * means that the event can be fragmented but only the first 'x' will be 2700 * scheduled. 2701 */ 2702#define IWM_TE_V1_FRAG_NONE 0 2703#define IWM_TE_V1_FRAG_SINGLE 1 2704#define IWM_TE_V1_FRAG_DUAL 2 2705#define IWM_TE_V1_FRAG_ENDLESS 0xffffffff 2706 2707/* If a Time Event can be fragmented, this is the max number of fragments */ 2708#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2709/* Repeat the time event endlessly (until removed) */ 2710#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2711/* If a Time Event has bounded repetitions, this is the maximal value */ 2712#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2713 2714/* Time Event dependencies: none, on another TE, or in a specific time */ 2715#define IWM_TE_V1_INDEPENDENT 0 2716#define IWM_TE_V1_DEP_OTHER (1 << 0) 2717#define IWM_TE_V1_DEP_TSF (1 << 1) 2718#define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2) 2719/* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2720 2721/* 2722 * @IWM_TE_V1_NOTIF_NONE: no notifications 2723 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2724 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2725 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2726 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2727 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2728 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2729 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2730 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2731 * 2732 * Supported Time event notifications configuration. 2733 * A notification (both event and fragment) includes a status indicating weather 2734 * the FW was able to schedule the event or not. For fragment start/end 2735 * notification the status is always success. There is no start/end fragment 2736 * notification for monolithic events. 2737 */ 2738#define IWM_TE_V1_NOTIF_NONE 0 2739#define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0) 2740#define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1) 2741#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2) 2742#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3) 2743#define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4) 2744#define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5) 2745#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6) 2746#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7) 2747/* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2748 2749 2750/* Time event - defines for command API */ 2751 2752/** 2753 * DOC: Time Events - what is it? 2754 * 2755 * Time Events are a fw feature that allows the driver to control the presence 2756 * of the device on the channel. Since the fw supports multiple channels 2757 * concurrently, the fw may choose to jump to another channel at any time. 2758 * In order to make sure that the fw is on a specific channel at a certain time 2759 * and for a certain duration, the driver needs to issue a time event. 2760 * 2761 * The simplest example is for BSS association. The driver issues a time event, 2762 * waits for it to start, and only then tells mac80211 that we can start the 2763 * association. This way, we make sure that the association will be done 2764 * smoothly and won't be interrupted by channel switch decided within the fw. 2765 */ 2766 2767 /** 2768 * DOC: The flow against the fw 2769 * 2770 * When the driver needs to make sure we are in a certain channel, at a certain 2771 * time and for a certain duration, it sends a Time Event. The flow against the 2772 * fw goes like this: 2773 * 1) Driver sends a TIME_EVENT_CMD to the fw 2774 * 2) Driver gets the response for that command. This response contains the 2775 * Unique ID (UID) of the event. 2776 * 3) The fw sends notification when the event starts. 2777 * 2778 * Of course the API provides various options that allow to cover parameters 2779 * of the flow. 2780 * What is the duration of the event? 2781 * What is the start time of the event? 2782 * Is there an end-time for the event? 2783 * How much can the event be delayed? 2784 * Can the event be split? 2785 * If yes what is the maximal number of chunks? 2786 * etc... 2787 */ 2788 2789/* 2790 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2791 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2792 * the first fragment is scheduled. 2793 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2794 * the first 2 fragments are scheduled. 2795 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2796 * number of fragments are valid. 2797 * 2798 * Other than the constant defined above, specifying a fragmentation value 'x' 2799 * means that the event can be fragmented but only the first 'x' will be 2800 * scheduled. 2801 */ 2802#define IWM_TE_V2_FRAG_NONE 0 2803#define IWM_TE_V2_FRAG_SINGLE 1 2804#define IWM_TE_V2_FRAG_DUAL 2 2805#define IWM_TE_V2_FRAG_MAX 0xfe 2806#define IWM_TE_V2_FRAG_ENDLESS 0xff 2807 2808/* Repeat the time event endlessly (until removed) */ 2809#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2810/* If a Time Event has bounded repetitions, this is the maximal value */ 2811#define IWM_TE_V2_REPEAT_MAX 0xfe 2812 2813#define IWM_TE_V2_PLACEMENT_POS 12 2814#define IWM_TE_V2_ABSENCE_POS 15 2815 2816/* Time event policy values 2817 * A notification (both event and fragment) includes a status indicating weather 2818 * the FW was able to schedule the event or not. For fragment start/end 2819 * notification the status is always success. There is no start/end fragment 2820 * notification for monolithic events. 2821 * 2822 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2823 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2824 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2825 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2826 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2827 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2828 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2829 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2830 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2831 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2832 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2833 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of the same MAC 2834 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2835 */ 2836#define IWM_TE_V2_DEFAULT_POLICY 0x0 2837 2838/* notifications (event start/stop, fragment start/stop) */ 2839#define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 2840#define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 2841#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 2842#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 2843 2844#define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 2845#define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 2846#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 2847#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 2848#define IWM_T2_V2_START_IMMEDIATELY (1 << 11) 2849 2850#define IWM_TE_V2_NOTIF_MSK 0xff 2851 2852/* placement characteristics */ 2853#define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS) 2854#define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1)) 2855#define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2)) 2856 2857/* are we present or absent during the Time Event. */ 2858#define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS) 2859 2860/** 2861 * struct iwm_time_event_cmd_api - configuring Time Events 2862 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2863 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2864 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2865 * @id_and_color: ID and color of the relevant MAC 2866 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2867 * @id: this field has two meanings, depending on the action: 2868 * If the action is ADD, then it means the type of event to add. 2869 * For all other actions it is the unique event ID assigned when the 2870 * event was added by the FW. 2871 * @apply_time: When to start the Time Event (in GP2) 2872 * @max_delay: maximum delay to event's start (apply time), in TU 2873 * @depends_on: the unique ID of the event we depend on (if any) 2874 * @interval: interval between repetitions, in TU 2875 * @duration: duration of event in TU 2876 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2877 * @max_frags: maximal number of fragments the Time Event can be divided to 2878 * @policy: defines whether uCode shall notify the host or other uCode modules 2879 * on event and/or fragment start and/or end 2880 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2881 * IWM_TE_EVENT_SOCIOPATHIC 2882 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2883 */ 2884struct iwm_time_event_cmd { 2885 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2886 uint32_t id_and_color; 2887 uint32_t action; 2888 uint32_t id; 2889 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2890 uint32_t apply_time; 2891 uint32_t max_delay; 2892 uint32_t depends_on; 2893 uint32_t interval; 2894 uint32_t duration; 2895 uint8_t repeat; 2896 uint8_t max_frags; 2897 uint16_t policy; 2898} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2899 2900/** 2901 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2902 * @status: bit 0 indicates success, all others specify errors 2903 * @id: the Time Event type 2904 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2905 * @id_and_color: ID and color of the relevant MAC 2906 */ 2907struct iwm_time_event_resp { 2908 uint32_t status; 2909 uint32_t id; 2910 uint32_t unique_id; 2911 uint32_t id_and_color; 2912} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2913 2914/** 2915 * struct iwm_time_event_notif - notifications of time event start/stop 2916 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2917 * @timestamp: action timestamp in GP2 2918 * @session_id: session's unique id 2919 * @unique_id: unique id of the Time Event itself 2920 * @id_and_color: ID and color of the relevant MAC 2921 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2922 * @status: true if scheduled, false otherwise (not executed) 2923 */ 2924struct iwm_time_event_notif { 2925 uint32_t timestamp; 2926 uint32_t session_id; 2927 uint32_t unique_id; 2928 uint32_t id_and_color; 2929 uint32_t action; 2930 uint32_t status; 2931} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2932 2933 2934/* Bindings and Time Quota */ 2935 2936/** 2937 * struct iwm_binding_cmd_v1 - configuring bindings 2938 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2939 * @id_and_color: ID and color of the relevant Binding 2940 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2941 * @macs: array of MAC id and colors which belong to the binding 2942 * @phy: PHY id and color which belongs to the binding 2943 * @lmac_id: the lmac id the binding belongs to 2944 */ 2945struct iwm_binding_cmd_v1 { 2946 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2947 uint32_t id_and_color; 2948 uint32_t action; 2949 /* IWM_BINDING_DATA_API_S_VER_1 */ 2950 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2951 uint32_t phy; 2952} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2953 2954/** 2955 * struct iwm_binding_cmd - configuring bindings 2956 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2957 * @id_and_color: ID and color of the relevant Binding 2958 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2959 * @macs: array of MAC id and colors which belong to the binding 2960 * @phy: PHY id and color which belongs to the binding 2961 * @lmac_id: the lmac id the binding belongs to 2962 */ 2963struct iwm_binding_cmd { 2964 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2965 uint32_t id_and_color; 2966 uint32_t action; 2967 /* IWM_BINDING_DATA_API_S_VER_1 */ 2968 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2969 uint32_t phy; 2970 uint32_t lmac_id; 2971} __packed; /* IWM_BINDING_CMD_API_S_VER_2 */ 2972 2973#define IWM_LMAC_24G_INDEX 0 2974#define IWM_LMAC_5G_INDEX 1 2975 2976/* The maximal number of fragments in the FW's schedule session */ 2977#define IWM_MAX_QUOTA 128 2978 2979/** 2980 * struct iwm_time_quota_data - configuration of time quota per binding 2981 * @id_and_color: ID and color of the relevant Binding 2982 * @quota: absolute time quota in TU. The scheduler will try to divide the 2983 * remaining quota (after Time Events) according to this quota. 2984 * @max_duration: max uninterrupted context duration in TU 2985 */ 2986struct iwm_time_quota_data_v1 { 2987 uint32_t id_and_color; 2988 uint32_t quota; 2989 uint32_t max_duration; 2990} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2991 2992/** 2993 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2994 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2995 * @quotas: allocations per binding 2996 */ 2997struct iwm_time_quota_cmd_v1 { 2998 struct iwm_time_quota_data_v1 quotas[IWM_MAX_BINDINGS]; 2999} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 3000 3001#define IWM_QUOTA_LOW_LATENCY_NONE 0 3002#define IWM_QUOTA_LOW_LATENCY_TX (1 << 0) 3003#define IWM_QUOTA_LOW_LATENCY_RX (1 << 1) 3004 3005/** 3006 * struct iwm_time_quota_data - configuration of time quota per binding 3007 * @id_and_color: ID and color of the relevant Binding. 3008 * @quota: absolute time quota in TU. The scheduler will try to divide the 3009 * remaining quota (after Time Events) according to this quota. 3010 * @max_duration: max uninterrupted context duration in TU 3011 * @low_latency: low latency status IWM_QUOTA_LOW_LATENCY_* 3012 */ 3013struct iwm_time_quota_data { 3014 uint32_t id_and_color; 3015 uint32_t quota; 3016 uint32_t max_duration; 3017 uint32_t low_latency; 3018}; /* TIME_QUOTA_DATA_API_S_VER_2 */ 3019 3020/** 3021 * struct iwm_time_quota_cmd - configuration of time quota between bindings 3022 * ( TIME_QUOTA_CMD = 0x2c ) 3023 * Note: on non-CDB the fourth one is the auxiliary mac and is essentially zero. 3024 * On CDB the fourth one is a regular binding. 3025 * 3026 * @quotas: allocations per binding 3027 */ 3028struct iwm_time_quota_cmd { 3029 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 3030}; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_2 */ 3031 3032 3033/* PHY context */ 3034 3035/* Supported bands */ 3036#define IWM_PHY_BAND_5 (0) 3037#define IWM_PHY_BAND_24 (1) 3038 3039/* Supported channel width, vary if there is VHT support */ 3040#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 3041#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 3042#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 3043#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 3044 3045/* 3046 * Control channel position: 3047 * For legacy set bit means upper channel, otherwise lower. 3048 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 3049 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 3050 * center_freq 3051 * | 3052 * 40Mhz |_______|_______| 3053 * 80Mhz |_______|_______|_______|_______| 3054 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 3055 * code 011 010 001 000 | 100 101 110 111 3056 */ 3057#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 3058#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 3059#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 3060#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 3061#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 3062#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 3063#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 3064#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 3065 3066/* 3067 * @band: IWM_PHY_BAND_* 3068 * @channel: channel number 3069 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3070 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3071 */ 3072struct iwm_fw_channel_info_v1 { 3073 uint8_t band; 3074 uint8_t channel; 3075 uint8_t width; 3076 uint8_t ctrl_pos; 3077} __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 3078 3079/* 3080 * struct iwm_fw_channel_info - channel information 3081 * 3082 * @channel: channel number 3083 * @band: PHY_BAND_* 3084 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3085 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3086 * @reserved: for future use and alignment 3087 */ 3088struct iwm_fw_channel_info { 3089 uint32_t channel; 3090 uint8_t band; 3091 uint8_t width; 3092 uint8_t ctrl_pos; 3093 uint8_t reserved; 3094} __packed; /* CHANNEL_CONFIG_API_S_VER_2 */ 3095 3096#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 3097#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 3098 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 3099#define IWM_PHY_RX_CHAIN_VALID_POS (1) 3100#define IWM_PHY_RX_CHAIN_VALID_MSK \ 3101 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 3102#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 3103#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 3104 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 3105#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 3106#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 3107 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 3108#define IWM_PHY_RX_CHAIN_CNT_POS (10) 3109#define IWM_PHY_RX_CHAIN_CNT_MSK \ 3110 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 3111#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 3112#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 3113 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 3114#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 3115#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 3116 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 3117 3118/* TODO: fix the value, make it depend on firmware at runtime? */ 3119#define IWM_NUM_PHY_CTX 3 3120 3121/* TODO: complete missing documentation */ 3122/** 3123 * struct iwm_phy_context_cmd - config of the PHY context 3124 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 3125 * @id_and_color: ID and color of the relevant Binding 3126 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3127 * @apply_time: 0 means immediate apply and context switch. 3128 * other value means apply new params after X usecs 3129 * @tx_param_color: ??? 3130 * @channel_info: 3131 * @txchain_info: ??? 3132 * @rxchain_info: ??? 3133 * @acquisition_data: ??? 3134 * @dsp_cfg_flags: set to 0 3135 */ 3136/* 3137 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 3138 * the size of fw_channel_info from v1 to v2. 3139 * To keep things simple we define two versions of this struct, and both 3140 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 3141 * magic with pointers to struct members instead.) 3142 */ 3143/* This version must be used if IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 3144struct iwm_phy_context_cmd_uhb { 3145 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3146 uint32_t id_and_color; 3147 uint32_t action; 3148 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3149 uint32_t apply_time; 3150 uint32_t tx_param_color; 3151 struct iwm_fw_channel_info ci; 3152 uint32_t txchain_info; 3153 uint32_t rxchain_info; 3154 uint32_t acquisition_data; 3155 uint32_t dsp_cfg_flags; 3156} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3157/* This version must be used otherwise: */ 3158struct iwm_phy_context_cmd { 3159 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3160 uint32_t id_and_color; 3161 uint32_t action; 3162 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3163 uint32_t apply_time; 3164 uint32_t tx_param_color; 3165 struct iwm_fw_channel_info_v1 ci; 3166 uint32_t txchain_info; 3167 uint32_t rxchain_info; 3168 uint32_t acquisition_data; 3169 uint32_t dsp_cfg_flags; 3170} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3171 3172#define IWM_RX_INFO_PHY_CNT 8 3173#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 3174#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 3175#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 3176#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 3177#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 3178#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 3179#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 3180 3181#define IWM_RX_INFO_AGC_IDX 1 3182#define IWM_RX_INFO_RSSI_AB_IDX 2 3183#define IWM_OFDM_AGC_A_MSK 0x0000007f 3184#define IWM_OFDM_AGC_A_POS 0 3185#define IWM_OFDM_AGC_B_MSK 0x00003f80 3186#define IWM_OFDM_AGC_B_POS 7 3187#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 3188#define IWM_OFDM_AGC_CODE_POS 20 3189#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 3190#define IWM_OFDM_RSSI_A_POS 0 3191#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 3192#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 3193#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 3194#define IWM_OFDM_RSSI_B_POS 16 3195#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 3196#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 3197 3198/** 3199 * struct iwm_rx_phy_info - phy info 3200 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 3201 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 3202 * @cfg_phy_cnt: configurable DSP phy data byte count 3203 * @stat_id: configurable DSP phy data set ID 3204 * @reserved1: 3205 * @system_timestamp: GP2 at on air rise 3206 * @timestamp: TSF at on air rise 3207 * @beacon_time_stamp: beacon at on-air rise 3208 * @phy_flags: general phy flags: band, modulation, ... 3209 * @channel: channel number 3210 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 3211 * @rate_n_flags: IWM_RATE_MCS_* 3212 * @byte_count: frame's byte-count 3213 * @frame_time: frame's time on the air, based on byte count and frame rate 3214 * calculation 3215 * @mac_active_msk: what MACs were active when the frame was received 3216 * 3217 * Before each Rx, the device sends this data. It contains PHY information 3218 * about the reception of the packet. 3219 */ 3220struct iwm_rx_phy_info { 3221 uint8_t non_cfg_phy_cnt; 3222 uint8_t cfg_phy_cnt; 3223 uint8_t stat_id; 3224 uint8_t reserved1; 3225 uint32_t system_timestamp; 3226 uint64_t timestamp; 3227 uint32_t beacon_time_stamp; 3228 uint16_t phy_flags; 3229#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 3230 uint16_t channel; 3231 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 3232 uint32_t rate_n_flags; 3233 uint32_t byte_count; 3234 uint16_t mac_active_msk; 3235 uint16_t frame_time; 3236} __packed; 3237 3238struct iwm_rx_mpdu_res_start { 3239 uint16_t byte_count; 3240 uint16_t reserved; 3241} __packed; 3242 3243/** 3244 * Values to parse %iwm_rx_phy_info phy_flags 3245 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 3246 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 3247 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 3248 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 3249 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 3250 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 3251 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 3252 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 3253 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 3254 */ 3255#define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 3256#define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3257#define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3258#define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3259#define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3260#define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3261#define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7) 3262#define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3263#define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3264#define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3265 3266/** 3267 * Values written by fw for each Rx packet 3268 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3269 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3270 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3271 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 3272 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3273 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3274 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3275 * in the driver. 3276 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3277 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3278 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3279 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3280 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3281 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3282 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3283 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3284 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3285 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3286 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3287 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3288 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3289 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3290 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3291 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3292 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3293 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 3294 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 3295 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 3296 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3297 */ 3298#define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3299#define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3300#define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3301#define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3302#define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3303#define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3304#define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3305#define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3306#define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3307#define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3308#define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3309#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3310#define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3311#define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3312#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3313#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3314#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3315#define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3316#define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3317#define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3318#define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3319#define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3320#define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3321#define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3322#define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3323#define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3324#define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3325 3326#define IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3327#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3328#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3329 3330#define IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3331#define IWM_RX_MPDU_MFLG2_PAD 0x20 3332#define IWM_RX_MPDU_MFLG2_AMSDU 0x40 3333 3334#define IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f 3335#define IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80 3336 3337#define IWM_RX_MPDU_PHY_AMPDU (1 << 5) 3338#define IWM_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3339#define IWM_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3340#define IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3341#define IWM_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3342 3343struct iwm_rx_mpdu_desc_v1 { 3344 union { 3345 uint32_t rss_hash; 3346 uint32_t phy_data2; 3347 }; 3348 union { 3349 uint32_t filter_match; 3350 uint32_t phy_data3; 3351 }; 3352 uint32_t rate_n_flags; 3353 uint8_t energy_a; 3354 uint8_t energy_b; 3355 uint8_t channel; 3356 uint8_t mac_context; 3357 uint32_t gp2_on_air_rise; 3358 union { 3359 uint64_t tsf_on_air_rise; 3360 struct { 3361 uint32_t phy_data0; 3362 uint32_t phy_data1; 3363 }; 3364 }; 3365} __packed; 3366 3367#define IWM_RX_REORDER_DATA_INVALID_BAID 0x7f 3368 3369#define IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff 3370#define IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000 3371#define IWM_RX_MPDU_REORDER_SN_SHIFT 12 3372#define IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000 3373#define IWM_RX_MPDU_REORDER_BAID_SHIFT 24 3374#define IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000 3375 3376struct iwm_rx_mpdu_desc { 3377 uint16_t mpdu_len; 3378 uint8_t mac_flags1; 3379 uint8_t mac_flags2; 3380 uint8_t amsdu_info; 3381 uint16_t phy_info; 3382 uint8_t mac_phy_idx; 3383 uint16_t raw_csum; 3384 union { 3385 uint16_t l3l4_flags; 3386 uint16_t phy_data4; 3387 }; 3388 uint16_t status; 3389 uint8_t hash_filter; 3390 uint8_t sta_id_flags; 3391 uint32_t reorder_data; 3392 struct iwm_rx_mpdu_desc_v1 v1; 3393} __packed; 3394 3395/** 3396 * struct iwm_radio_version_notif - information on the radio version 3397 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 3398 * @radio_flavor: 3399 * @radio_step: 3400 * @radio_dash: 3401 */ 3402struct iwm_radio_version_notif { 3403 uint32_t radio_flavor; 3404 uint32_t radio_step; 3405 uint32_t radio_dash; 3406} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3407 3408#define IWM_CARD_ENABLED 0x00 3409#define IWM_HW_CARD_DISABLED 0x01 3410#define IWM_SW_CARD_DISABLED 0x02 3411#define IWM_CT_KILL_CARD_DISABLED 0x04 3412#define IWM_HALT_CARD_DISABLED 0x08 3413#define IWM_CARD_DISABLED_MSK 0x0f 3414#define IWM_CARD_IS_RX_ON 0x10 3415 3416/** 3417 * struct iwm_radio_version_notif - information on the radio version 3418 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 3419 * @flags: %iwm_card_state_flags 3420 */ 3421struct iwm_card_state_notif { 3422 uint32_t flags; 3423} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3424 3425/** 3426 * struct iwm_missed_beacons_notif - information on missed beacons 3427 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3428 * @mac_id: interface ID 3429 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3430 * beacons since last RX. 3431 * @consec_missed_beacons: number of consecutive missed beacons 3432 * @num_expected_beacons: 3433 * @num_recvd_beacons: 3434 */ 3435struct iwm_missed_beacons_notif { 3436 uint32_t mac_id; 3437 uint32_t consec_missed_beacons_since_last_rx; 3438 uint32_t consec_missed_beacons; 3439 uint32_t num_expected_beacons; 3440 uint32_t num_recvd_beacons; 3441} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 3442 3443/** 3444 * struct iwm_mfuart_load_notif - mfuart image version & status 3445 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3446 * @installed_ver: installed image version 3447 * @external_ver: external image version 3448 * @status: MFUART loading status 3449 * @duration: MFUART loading time 3450*/ 3451struct iwm_mfuart_load_notif { 3452 uint32_t installed_ver; 3453 uint32_t external_ver; 3454 uint32_t status; 3455 uint32_t duration; 3456} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3457 3458/** 3459 * struct iwm_set_calib_default_cmd - set default value for calibration. 3460 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 3461 * @calib_index: the calibration to set value for 3462 * @length: of data 3463 * @data: the value to set for the calibration result 3464 */ 3465struct iwm_set_calib_default_cmd { 3466 uint16_t calib_index; 3467 uint16_t length; 3468 uint8_t data[0]; 3469} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 3470 3471#define IWM_MAX_PORT_ID_NUM 2 3472#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 3473 3474/** 3475 * struct iwm_mcast_filter_cmd - configure multicast filter. 3476 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3477 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3478 * to identify network interface adopted in host-device IF. 3479 * It is used by FW as index in array of addresses. This array has 3480 * IWM_MAX_PORT_ID_NUM members. 3481 * @count: Number of MAC addresses in the array 3482 * @pass_all: Set 1 to pass all multicast packets. 3483 * @bssid: current association BSSID. 3484 * @addr_list: Place holder for array of MAC addresses. 3485 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3486 */ 3487struct iwm_mcast_filter_cmd { 3488 uint8_t filter_own; 3489 uint8_t port_id; 3490 uint8_t count; 3491 uint8_t pass_all; 3492 uint8_t bssid[6]; 3493 uint8_t reserved[2]; 3494 uint8_t addr_list[0]; 3495} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 3496 3497struct iwm_statistics_dbg { 3498 uint32_t burst_check; 3499 uint32_t burst_count; 3500 uint32_t wait_for_silence_timeout_cnt; 3501 uint32_t reserved[3]; 3502} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 3503 3504struct iwm_statistics_div { 3505 uint32_t tx_on_a; 3506 uint32_t tx_on_b; 3507 uint32_t exec_time; 3508 uint32_t probe_time; 3509 uint32_t rssi_ant; 3510 uint32_t reserved2; 3511} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3512 3513struct iwm_statistics_general_common { 3514 uint32_t temperature; /* radio temperature */ 3515 uint32_t temperature_m; /* radio voltage */ 3516 struct iwm_statistics_dbg dbg; 3517 uint32_t sleep_time; 3518 uint32_t slots_out; 3519 uint32_t slots_idle; 3520 uint32_t ttl_timestamp; 3521 struct iwm_statistics_div div; 3522 uint32_t rx_enable_counter; 3523 /* 3524 * num_of_sos_states: 3525 * count the number of times we have to re-tune 3526 * in order to get out of bad PHY status 3527 */ 3528 uint32_t num_of_sos_states; 3529} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3530 3531struct iwm_statistics_rx_non_phy { 3532 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3533 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3534 uint32_t non_bssid_frames; /* number of frames with BSSID that 3535 * doesn't belong to the STA BSSID */ 3536 uint32_t filtered_frames; /* count frames that were dumped in the 3537 * filtering process */ 3538 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3539 * our serving channel */ 3540 uint32_t channel_beacons; /* beacons with our bss id and in our 3541 * serving channel */ 3542 uint32_t num_missed_bcon; /* number of missed beacons */ 3543 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3544 * ADC was in saturation */ 3545 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3546 * for INA */ 3547 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3548 uint32_t interference_data_flag; /* flag for interference data 3549 * availability. 1 when data is 3550 * available. */ 3551 uint32_t channel_load; /* counts RX Enable time in uSec */ 3552 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3553 * and CCK) counter */ 3554 uint32_t beacon_rssi_a; 3555 uint32_t beacon_rssi_b; 3556 uint32_t beacon_rssi_c; 3557 uint32_t beacon_energy_a; 3558 uint32_t beacon_energy_b; 3559 uint32_t beacon_energy_c; 3560 uint32_t num_bt_kills; 3561 uint32_t mac_id; 3562 uint32_t directed_data_mpdu; 3563} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3564 3565struct iwm_statistics_rx_phy { 3566 uint32_t ina_cnt; 3567 uint32_t fina_cnt; 3568 uint32_t plcp_err; 3569 uint32_t crc32_err; 3570 uint32_t overrun_err; 3571 uint32_t early_overrun_err; 3572 uint32_t crc32_good; 3573 uint32_t false_alarm_cnt; 3574 uint32_t fina_sync_err_cnt; 3575 uint32_t sfd_timeout; 3576 uint32_t fina_timeout; 3577 uint32_t unresponded_rts; 3578 uint32_t rxe_frame_limit_overrun; 3579 uint32_t sent_ack_cnt; 3580 uint32_t sent_cts_cnt; 3581 uint32_t sent_ba_rsp_cnt; 3582 uint32_t dsp_self_kill; 3583 uint32_t mh_format_err; 3584 uint32_t re_acq_main_rssi_sum; 3585 uint32_t reserved; 3586} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3587 3588struct iwm_statistics_rx_ht_phy { 3589 uint32_t plcp_err; 3590 uint32_t overrun_err; 3591 uint32_t early_overrun_err; 3592 uint32_t crc32_good; 3593 uint32_t crc32_err; 3594 uint32_t mh_format_err; 3595 uint32_t agg_crc32_good; 3596 uint32_t agg_mpdu_cnt; 3597 uint32_t agg_cnt; 3598 uint32_t unsupport_mcs; 3599} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3600 3601#define IWM_MAX_CHAINS 3 3602 3603struct iwm_statistics_tx_non_phy_agg { 3604 uint32_t ba_timeout; 3605 uint32_t ba_reschedule_frames; 3606 uint32_t scd_query_agg_frame_cnt; 3607 uint32_t scd_query_no_agg; 3608 uint32_t scd_query_agg; 3609 uint32_t scd_query_mismatch; 3610 uint32_t frame_not_ready; 3611 uint32_t underrun; 3612 uint32_t bt_prio_kill; 3613 uint32_t rx_ba_rsp_cnt; 3614 int8_t txpower[IWM_MAX_CHAINS]; 3615 int8_t reserved; 3616 uint32_t reserved2; 3617} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3618 3619struct iwm_statistics_tx_channel_width { 3620 uint32_t ext_cca_narrow_ch20[1]; 3621 uint32_t ext_cca_narrow_ch40[2]; 3622 uint32_t ext_cca_narrow_ch80[3]; 3623 uint32_t ext_cca_narrow_ch160[4]; 3624 uint32_t last_tx_ch_width_indx; 3625 uint32_t rx_detected_per_ch_width[4]; 3626 uint32_t success_per_ch_width[4]; 3627 uint32_t fail_per_ch_width[4]; 3628}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3629 3630struct iwm_statistics_tx { 3631 uint32_t preamble_cnt; 3632 uint32_t rx_detected_cnt; 3633 uint32_t bt_prio_defer_cnt; 3634 uint32_t bt_prio_kill_cnt; 3635 uint32_t few_bytes_cnt; 3636 uint32_t cts_timeout; 3637 uint32_t ack_timeout; 3638 uint32_t expected_ack_cnt; 3639 uint32_t actual_ack_cnt; 3640 uint32_t dump_msdu_cnt; 3641 uint32_t burst_abort_next_frame_mismatch_cnt; 3642 uint32_t burst_abort_missing_next_frame_cnt; 3643 uint32_t cts_timeout_collision; 3644 uint32_t ack_or_ba_timeout_collision; 3645 struct iwm_statistics_tx_non_phy_agg agg; 3646 struct iwm_statistics_tx_channel_width channel_width; 3647} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3648 3649 3650struct iwm_statistics_bt_activity { 3651 uint32_t hi_priority_tx_req_cnt; 3652 uint32_t hi_priority_tx_denied_cnt; 3653 uint32_t lo_priority_tx_req_cnt; 3654 uint32_t lo_priority_tx_denied_cnt; 3655 uint32_t hi_priority_rx_req_cnt; 3656 uint32_t hi_priority_rx_denied_cnt; 3657 uint32_t lo_priority_rx_req_cnt; 3658 uint32_t lo_priority_rx_denied_cnt; 3659} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3660 3661struct iwm_statistics_general { 3662 struct iwm_statistics_general_common common; 3663 uint32_t beacon_filtered; 3664 uint32_t missed_beacons; 3665 int8_t beacon_filter_average_energy; 3666 int8_t beacon_filter_reason; 3667 int8_t beacon_filter_current_energy; 3668 int8_t beacon_filter_reserved; 3669 uint32_t beacon_filter_delta_time; 3670 struct iwm_statistics_bt_activity bt_activity; 3671} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3672 3673struct iwm_statistics_rx { 3674 struct iwm_statistics_rx_phy ofdm; 3675 struct iwm_statistics_rx_phy cck; 3676 struct iwm_statistics_rx_non_phy general; 3677 struct iwm_statistics_rx_ht_phy ofdm_ht; 3678} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3679 3680/* 3681 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3682 * 3683 * By default, uCode issues this notification after receiving a beacon 3684 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3685 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3686 * 3687 * Statistics counters continue to increment beacon after beacon, but are 3688 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3689 * 0x9c with CLEAR_STATS bit set (see above). 3690 * 3691 * uCode also issues this notification during scans. uCode clears statistics 3692 * appropriately so that each notification contains statistics for only the 3693 * one channel that has just been scanned. 3694 */ 3695 3696struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3697 uint32_t flag; 3698 struct iwm_statistics_rx rx; 3699 struct iwm_statistics_tx tx; 3700 struct iwm_statistics_general general; 3701} __packed; 3702 3703/*********************************** 3704 * Smart Fifo API 3705 ***********************************/ 3706/* Smart Fifo state */ 3707#define IWM_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 3708#define IWM_SF_FULL_ON 1 3709#define IWM_SF_UNINIT 2 3710#define IWM_SF_INIT_OFF 3 3711#define IWM_SF_HW_NUM_STATES 4 3712 3713/* Smart Fifo possible scenario */ 3714#define IWM_SF_SCENARIO_SINGLE_UNICAST 0 3715#define IWM_SF_SCENARIO_AGG_UNICAST 1 3716#define IWM_SF_SCENARIO_MULTICAST 2 3717#define IWM_SF_SCENARIO_BA_RESP 3 3718#define IWM_SF_SCENARIO_TX_RESP 4 3719#define IWM_SF_NUM_SCENARIO 5 3720 3721#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3722#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3723 3724/* smart FIFO default values */ 3725#define IWM_SF_W_MARK_SISO 4096 3726#define IWM_SF_W_MARK_MIMO2 8192 3727#define IWM_SF_W_MARK_MIMO3 6144 3728#define IWM_SF_W_MARK_LEGACY 4096 3729#define IWM_SF_W_MARK_SCAN 4096 3730 3731/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3732#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3733#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3734#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3735#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3736#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3737#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3738#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3739#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3740#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3741#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3742 3743/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3744#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3745#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3746#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3747#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3748#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3749#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3750#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3751#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3752#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3753#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3754 3755#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3756 3757#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3758 3759/** 3760 * Smart Fifo configuration command. 3761 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3762 * @watermark: Minimum allowed available free space in RXF for transient state. 3763 * @long_delay_timeouts: aging and idle timer values for each scenario 3764 * in long delay state. 3765 * @full_on_timeouts: timer values for each scenario in full on state. 3766 */ 3767struct iwm_sf_cfg_cmd { 3768 uint32_t state; 3769 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3770 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3771 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3772} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3773 3774/* 3775 * The first MAC indices (starting from 0) 3776 * are available to the driver, AUX follows 3777 */ 3778#define IWM_MAC_INDEX_AUX 4 3779#define IWM_MAC_INDEX_MIN_DRIVER 0 3780#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3781 3782#define IWM_AC_BK 0 3783#define IWM_AC_BE 1 3784#define IWM_AC_VI 2 3785#define IWM_AC_VO 3 3786#define IWM_AC_NUM 4 3787 3788/** 3789 * MAC context flags 3790 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3791 * this will require CCK RTS/CTS2self. 3792 * RTS/CTS will protect full burst time. 3793 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3794 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3795 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3796 */ 3797#define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 3798#define IWM_MAC_PROT_FLG_HT_PROT (1 << 23) 3799#define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24) 3800#define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 3801 3802#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3803#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3804 3805/** 3806 * Supported MAC types 3807 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3808 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3809 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3810 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3811 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3812 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3813 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3814 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3815 * @IWM_FW_MAC_TYPE_GO: P2P GO 3816 * @IWM_FW_MAC_TYPE_TEST: ? 3817 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3818 */ 3819#define IWM_FW_MAC_TYPE_FIRST 1 3820#define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST 3821#define IWM_FW_MAC_TYPE_LISTENER 2 3822#define IWM_FW_MAC_TYPE_PIBSS 3 3823#define IWM_FW_MAC_TYPE_IBSS 4 3824#define IWM_FW_MAC_TYPE_BSS_STA 5 3825#define IWM_FW_MAC_TYPE_P2P_DEVICE 6 3826#define IWM_FW_MAC_TYPE_P2P_STA 7 3827#define IWM_FW_MAC_TYPE_GO 8 3828#define IWM_FW_MAC_TYPE_TEST 9 3829#define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST 3830/* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3831 3832/** 3833 * TSF hw timer ID 3834 * @IWM_TSF_ID_A: use TSF A 3835 * @IWM_TSF_ID_B: use TSF B 3836 * @IWM_TSF_ID_C: use TSF C 3837 * @IWM_TSF_ID_D: use TSF D 3838 * @IWM_NUM_TSF_IDS: number of TSF timers available 3839 */ 3840#define IWM_TSF_ID_A 0 3841#define IWM_TSF_ID_B 1 3842#define IWM_TSF_ID_C 2 3843#define IWM_TSF_ID_D 3 3844#define IWM_NUM_TSF_IDS 4 3845/* IWM_TSF_ID_API_E_VER_1 */ 3846 3847/** 3848 * struct iwm_mac_data_ap - configuration data for AP MAC context 3849 * @beacon_time: beacon transmit time in system time 3850 * @beacon_tsf: beacon transmit time in TSF 3851 * @bi: beacon interval in TU 3852 * @bi_reciprocal: 2^32 / bi 3853 * @dtim_interval: dtim transmit time in TU 3854 * @dtim_reciprocal: 2^32 / dtim_interval 3855 * @mcast_qid: queue ID for multicast traffic 3856 * NOTE: obsolete from VER2 and on 3857 * @beacon_template: beacon template ID 3858 */ 3859struct iwm_mac_data_ap { 3860 uint32_t beacon_time; 3861 uint64_t beacon_tsf; 3862 uint32_t bi; 3863 uint32_t bi_reciprocal; 3864 uint32_t dtim_interval; 3865 uint32_t dtim_reciprocal; 3866 uint32_t mcast_qid; 3867 uint32_t beacon_template; 3868} __packed; /* AP_MAC_DATA_API_S_VER_2 */ 3869 3870/** 3871 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3872 * @beacon_time: beacon transmit time in system time 3873 * @beacon_tsf: beacon transmit time in TSF 3874 * @bi: beacon interval in TU 3875 * @bi_reciprocal: 2^32 / bi 3876 * @beacon_template: beacon template ID 3877 */ 3878struct iwm_mac_data_ibss { 3879 uint32_t beacon_time; 3880 uint64_t beacon_tsf; 3881 uint32_t bi; 3882 uint32_t bi_reciprocal; 3883 uint32_t beacon_template; 3884} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3885 3886/** 3887 * struct iwm_mac_data_sta - configuration data for station MAC context 3888 * @is_assoc: 1 for associated state, 0 otherwise 3889 * @dtim_time: DTIM arrival time in system time 3890 * @dtim_tsf: DTIM arrival time in TSF 3891 * @bi: beacon interval in TU, applicable only when associated 3892 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3893 * @dtim_interval: DTIM interval in TU, applicable only when associated 3894 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3895 * @listen_interval: in beacon intervals, applicable only when associated 3896 * @assoc_id: unique ID assigned by the AP during association 3897 */ 3898struct iwm_mac_data_sta { 3899 uint32_t is_assoc; 3900 uint32_t dtim_time; 3901 uint64_t dtim_tsf; 3902 uint32_t bi; 3903 uint32_t bi_reciprocal; 3904 uint32_t dtim_interval; 3905 uint32_t dtim_reciprocal; 3906 uint32_t listen_interval; 3907 uint32_t assoc_id; 3908 uint32_t assoc_beacon_arrive_time; 3909} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3910 3911/** 3912 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3913 * @ap: iwm_mac_data_ap struct with most config data 3914 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3915 * 0 indicates that there is no CT window. 3916 * @opp_ps_enabled: indicate that opportunistic PS allowed 3917 */ 3918struct iwm_mac_data_go { 3919 struct iwm_mac_data_ap ap; 3920 uint32_t ctwin; 3921 uint32_t opp_ps_enabled; 3922} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3923 3924/** 3925 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3926 * @sta: iwm_mac_data_sta struct with most config data 3927 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3928 * 0 indicates that there is no CT window. 3929 */ 3930struct iwm_mac_data_p2p_sta { 3931 struct iwm_mac_data_sta sta; 3932 uint32_t ctwin; 3933} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3934 3935/** 3936 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3937 * @stats_interval: interval in TU between statistics notifications to host. 3938 */ 3939struct iwm_mac_data_pibss { 3940 uint32_t stats_interval; 3941} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3942 3943/* 3944 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3945 * context. 3946 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3947 * other channels as well. This should be to true only in case that the 3948 * device is discoverable and there is an active GO. Note that setting this 3949 * field when not needed, will increase the number of interrupts and have 3950 * effect on the platform power, as this setting opens the Rx filters on 3951 * all macs. 3952 */ 3953struct iwm_mac_data_p2p_dev { 3954 uint32_t is_disc_extended; 3955} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3956 3957/** 3958 * MAC context filter flags 3959 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3960 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all management and 3961 * control frames to the host 3962 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3963 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3964 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3965 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3966 * (in station mode when associated) 3967 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3968 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3969 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3970 */ 3971#define IWM_MAC_FILTER_IN_PROMISC (1 << 0) 3972#define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 3973#define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2) 3974#define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3) 3975#define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 3976#define IWM_MAC_FILTER_IN_BEACON (1 << 6) 3977#define IWM_MAC_FILTER_OUT_BCAST (1 << 8) 3978#define IWM_MAC_FILTER_IN_CRC32 (1 << 11) 3979#define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 3980 3981/** 3982 * QoS flags 3983 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3984 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3985 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3986 * 3987 */ 3988#define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 3989#define IWM_MAC_QOS_FLG_TGN (1 << 1) 3990#define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 3991 3992/** 3993 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3994 * @cw_min: Contention window, start value in numbers of slots. 3995 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3996 * @cw_max: Contention window, max value in numbers of slots. 3997 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3998 * @aifsn: Number of slots in Arbitration Interframe Space (before 3999 * performing random backoff timing prior to Tx). Device default 1. 4000 * @fifos_mask: FIFOs used by this MAC for this AC 4001 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 4002 * 4003 * One instance of this config struct for each of 4 EDCA access categories 4004 * in struct iwm_qosparam_cmd. 4005 * 4006 * Device will automatically increase contention window by (2*CW) + 1 for each 4007 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 4008 * value, to cap the CW value. 4009 */ 4010struct iwm_ac_qos { 4011 uint16_t cw_min; 4012 uint16_t cw_max; 4013 uint8_t aifsn; 4014 uint8_t fifos_mask; 4015 uint16_t edca_txop; 4016} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 4017 4018/** 4019 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 4020 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 4021 * @id_and_color: ID and color of the MAC 4022 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 4023 * @mac_type: one of IWM_FW_MAC_TYPE_* 4024 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_* 4025 * @node_addr: MAC address 4026 * @bssid_addr: BSSID 4027 * @cck_rates: basic rates available for CCK 4028 * @ofdm_rates: basic rates available for OFDM 4029 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 4030 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 4031 * @short_slot: 0x10 for enabling short slots, 0 otherwise 4032 * @filter_flags: combination of IWM_MAC_FILTER_* 4033 * @qos_flags: from IWM_MAC_QOS_FLG_* 4034 * @ac: one iwm_mac_qos configuration for each AC 4035 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 4036 */ 4037struct iwm_mac_ctx_cmd { 4038 /* COMMON_INDEX_HDR_API_S_VER_1 */ 4039 uint32_t id_and_color; 4040 uint32_t action; 4041 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 4042 uint32_t mac_type; 4043 uint32_t tsf_id; 4044 uint8_t node_addr[6]; 4045 uint16_t reserved_for_node_addr; 4046 uint8_t bssid_addr[6]; 4047 uint16_t reserved_for_bssid_addr; 4048 uint32_t cck_rates; 4049 uint32_t ofdm_rates; 4050 uint32_t protection_flags; 4051 uint32_t cck_short_preamble; 4052 uint32_t short_slot; 4053 uint32_t filter_flags; 4054 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 4055 uint32_t qos_flags; 4056 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 4057 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 4058 union { 4059 struct iwm_mac_data_ap ap; 4060 struct iwm_mac_data_go go; 4061 struct iwm_mac_data_sta sta; 4062 struct iwm_mac_data_p2p_sta p2p_sta; 4063 struct iwm_mac_data_p2p_dev p2p_dev; 4064 struct iwm_mac_data_pibss pibss; 4065 struct iwm_mac_data_ibss ibss; 4066 }; 4067} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 4068 4069static inline uint32_t iwm_reciprocal(uint32_t v) 4070{ 4071 if (!v) 4072 return 0; 4073 return 0xFFFFFFFF / v; 4074} 4075 4076#define IWM_NONQOS_SEQ_GET 0x1 4077#define IWM_NONQOS_SEQ_SET 0x2 4078struct iwm_nonqos_seq_query_cmd { 4079 uint32_t get_set_flag; 4080 uint32_t mac_id_n_color; 4081 uint16_t value; 4082 uint16_t reserved; 4083} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 4084 4085/* Power Management Commands, Responses, Notifications */ 4086 4087/** 4088 * masks for LTR config command flags 4089 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 4090 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 4091 * memory access 4092 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 4093 * reg change 4094 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 4095 * D0 to D3 4096 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 4097 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 4098 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 4099 */ 4100#define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 4101#define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 4102#define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 4103#define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 4104#define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 4105#define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 4106#define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 4107 4108/** 4109 * struct iwm_ltr_config_cmd_v1 - configures the LTR 4110 * @flags: See %enum iwm_ltr_config_flags 4111 */ 4112struct iwm_ltr_config_cmd_v1 { 4113 uint32_t flags; 4114 uint32_t static_long; 4115 uint32_t static_short; 4116} __packed; /* LTR_CAPABLE_API_S_VER_1 */ 4117 4118#define IWM_LTR_VALID_STATES_NUM 4 4119 4120/** 4121 * struct iwm_ltr_config_cmd - configures the LTR 4122 * @flags: See %enum iwm_ltr_config_flags 4123 * @static_long: 4124 * @static_short: 4125 * @ltr_cfg_values: 4126 * @ltr_short_idle_timeout: 4127 */ 4128struct iwm_ltr_config_cmd { 4129 uint32_t flags; 4130 uint32_t static_long; 4131 uint32_t static_short; 4132 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 4133 uint32_t ltr_short_idle_timeout; 4134} __packed; /* LTR_CAPABLE_API_S_VER_2 */ 4135 4136/* Radio LP RX Energy Threshold measured in dBm */ 4137#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 4138#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 4139#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 4140 4141/** 4142 * Masks for iwm_mac_power_cmd command flags 4143 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 4144 * receiver and transmitter. '0' - does not allow. 4145 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 4146 * '1' Driver enables PM (use rest of parameters) 4147 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 4148 * '1' PM could sleep over DTIM till listen Interval. 4149 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 4150 * access categories are both delivery and trigger enabled. 4151 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 4152 * PBW Snoozing enabled 4153 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 4154 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 4155 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 4156 * detection enablement 4157*/ 4158#define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4159#define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 4160#define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 4161#define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 4162#define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8) 4163#define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 4164#define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 4165#define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 4166 4167#define IWM_POWER_VEC_SIZE 5 4168 4169/** 4170 * Masks for device power command flags 4171 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 4172 * '1' Allow to save power by turning off receiver and transmitter. 4173 * '0' Do not allow. This flag should be always set to '1' unless 4174 * one needs to disable actual power down for debug purposes. 4175 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: 4176 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 4177 * '0' Power management is enabled, one of the power schemes is applied. 4178 */ 4179#define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4180#define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 4181 4182/** 4183 * struct iwm_device_power_cmd - device wide power command. 4184 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 4185 * 4186 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 4187 */ 4188struct iwm_device_power_cmd { 4189 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 4190 uint16_t flags; 4191 uint16_t reserved; 4192} __packed; 4193 4194/** 4195 * struct iwm_mac_power_cmd - New power command containing uAPSD support 4196 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 4197 * @id_and_color: MAC context identifier 4198 * @flags: Power table command flags from POWER_FLAGS_* 4199 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 4200 * Minimum allowed:- 3 * DTIM. Keep alive period must be 4201 * set regardless of power scheme or current power state. 4202 * FW use this value also when PM is disabled. 4203 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 4204 * PSM transition - legacy PM 4205 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 4206 * PSM transition - legacy PM 4207 * @sleep_interval: not in use 4208 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 4209 * is set. For example, if it is required to skip over 4210 * one DTIM, this value need to be set to 2 (DTIM periods). 4211 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 4212 * PSM transition - uAPSD 4213 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 4214 * PSM transition - uAPSD 4215 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 4216 * Default: 80dbm 4217 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 4218 * @snooze_interval: Maximum time between attempts to retrieve buffered data 4219 * from the AP [msec] 4220 * @snooze_window: A window of time in which PBW snoozing insures that all 4221 * packets received. It is also the minimum time from last 4222 * received unicast RX packet, before client stops snoozing 4223 * for data. [msec] 4224 * @snooze_step: TBD 4225 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 4226 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4227 * each corresponding AC. 4228 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4229 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4230 * values. 4231 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4232 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4233 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4234 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4235 * @limited_ps_threshold: 4236*/ 4237struct iwm_mac_power_cmd { 4238 /* CONTEXT_DESC_API_T_VER_1 */ 4239 uint32_t id_and_color; 4240 4241 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4242 uint16_t flags; 4243 uint16_t keep_alive_seconds; 4244 uint32_t rx_data_timeout; 4245 uint32_t tx_data_timeout; 4246 uint32_t rx_data_timeout_uapsd; 4247 uint32_t tx_data_timeout_uapsd; 4248 uint8_t lprx_rssi_threshold; 4249 uint8_t skip_dtim_periods; 4250 uint16_t snooze_interval; 4251 uint16_t snooze_window; 4252 uint8_t snooze_step; 4253 uint8_t qndp_tid; 4254 uint8_t uapsd_ac_flags; 4255 uint8_t uapsd_max_sp; 4256 uint8_t heavy_tx_thld_packets; 4257 uint8_t heavy_rx_thld_packets; 4258 uint8_t heavy_tx_thld_percentage; 4259 uint8_t heavy_rx_thld_percentage; 4260 uint8_t limited_ps_threshold; 4261 uint8_t reserved; 4262} __packed; 4263 4264#define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4265#define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4266 4267/* 4268 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 4269 * associated AP is identified as improperly implementing uAPSD protocol. 4270 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4271 * @sta_id: index of station in uCode's station table - associated AP ID in 4272 * this context. 4273 */ 4274struct iwm_uapsd_misbehaving_ap_notif { 4275 uint32_t sta_id; 4276 uint8_t mac_id; 4277 uint8_t reserved[3]; 4278} __packed; 4279 4280/** 4281 * struct iwm_beacon_filter_cmd 4282 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4283 * @id_and_color: MAC context identifier 4284 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4285 * to driver if delta in Energy values calculated for this and last 4286 * passed beacon is greater than this threshold. Zero value means that 4287 * the Energy change is ignored for beacon filtering, and beacon will 4288 * not be forced to be sent to driver regardless of this delta. Typical 4289 * energy delta 5dB. 4290 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4291 * Send beacon to driver if delta in Energy values calculated for this 4292 * and last passed beacon is greater than this threshold. Zero value 4293 * means that the Energy change is ignored for beacon filtering while in 4294 * Roaming state, typical energy delta 1dB. 4295 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4296 * calculated for current beacon is less than the threshold, use 4297 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4298 * Threshold. Typical energy threshold is -72dBm. 4299 * @bf_temp_threshold: This threshold determines the type of temperature 4300 * filtering (Slow or Fast) that is selected (Units are in Celsius): 4301 * If the current temperature is above this threshold - Fast filter 4302 * will be used, If the current temperature is below this threshold - 4303 * Slow filter will be used. 4304 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4305 * calculated for this and the last passed beacon is greater than this 4306 * threshold. Zero value means that the temperature change is ignored for 4307 * beacon filtering; beacons will not be forced to be sent to driver 4308 * regardless of whether its temperature has been changed. 4309 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4310 * calculated for this and the last passed beacon is greater than this 4311 * threshold. Zero value means that the temperature change is ignored for 4312 * beacon filtering; beacons will not be forced to be sent to driver 4313 * regardless of whether its temperature has been changed. 4314 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4315 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4316 * for a specific period of time. Units: Beacons. 4317 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4318 * for a longer period of time then this escape-timeout. Units: Beacons. 4319 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4320 */ 4321struct iwm_beacon_filter_cmd { 4322 uint32_t bf_energy_delta; 4323 uint32_t bf_roaming_energy_delta; 4324 uint32_t bf_roaming_state; 4325 uint32_t bf_temp_threshold; 4326 uint32_t bf_temp_fast_filter; 4327 uint32_t bf_temp_slow_filter; 4328 uint32_t bf_enable_beacon_filter; 4329 uint32_t bf_debug_flag; 4330 uint32_t bf_escape_timer; 4331 uint32_t ba_escape_timer; 4332 uint32_t ba_enable_beacon_abort; 4333} __packed; 4334 4335/* Beacon filtering and beacon abort */ 4336#define IWM_BF_ENERGY_DELTA_DEFAULT 5 4337#define IWM_BF_ENERGY_DELTA_MAX 255 4338#define IWM_BF_ENERGY_DELTA_MIN 0 4339 4340#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4341#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 4342#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 4343 4344#define IWM_BF_ROAMING_STATE_DEFAULT 72 4345#define IWM_BF_ROAMING_STATE_MAX 255 4346#define IWM_BF_ROAMING_STATE_MIN 0 4347 4348#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 4349#define IWM_BF_TEMP_THRESHOLD_MAX 255 4350#define IWM_BF_TEMP_THRESHOLD_MIN 0 4351 4352#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 4353#define IWM_BF_TEMP_FAST_FILTER_MAX 255 4354#define IWM_BF_TEMP_FAST_FILTER_MIN 0 4355 4356#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 4357#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 4358#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 4359 4360#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4361 4362#define IWM_BF_DEBUG_FLAG_DEFAULT 0 4363 4364#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 4365#define IWM_BF_ESCAPE_TIMER_MAX 1024 4366#define IWM_BF_ESCAPE_TIMER_MIN 0 4367 4368#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 4369#define IWM_BA_ESCAPE_TIMER_D3 9 4370#define IWM_BA_ESCAPE_TIMER_MAX 1024 4371#define IWM_BA_ESCAPE_TIMER_MIN 0 4372 4373#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4374 4375#define IWM_BF_CMD_CONFIG_DEFAULTS \ 4376 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 4377 .bf_roaming_energy_delta = \ 4378 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4379 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 4380 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 4381 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 4382 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4383 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 4384 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 4385 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 4386 4387/* uCode API values for HT/VHT bit rates */ 4388#define IWM_RATE_HT_SISO_MCS_0_PLCP 0 4389#define IWM_RATE_HT_SISO_MCS_1_PLCP 1 4390#define IWM_RATE_HT_SISO_MCS_2_PLCP 2 4391#define IWM_RATE_HT_SISO_MCS_3_PLCP 3 4392#define IWM_RATE_HT_SISO_MCS_4_PLCP 4 4393#define IWM_RATE_HT_SISO_MCS_5_PLCP 5 4394#define IWM_RATE_HT_SISO_MCS_6_PLCP 6 4395#define IWM_RATE_HT_SISO_MCS_7_PLCP 7 4396#define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4397#define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4398#define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4399#define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4400#define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4401#define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4402#define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4403#define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4404#define IWM_RATE_VHT_SISO_MCS_0_PLCP 0 4405#define IWM_RATE_VHT_SISO_MCS_1_PLCP 1 4406#define IWM_RATE_VHT_SISO_MCS_2_PLCP 2 4407#define IWM_RATE_VHT_SISO_MCS_3_PLCP 3 4408#define IWM_RATE_VHT_SISO_MCS_4_PLCP 4 4409#define IWM_RATE_VHT_SISO_MCS_5_PLCP 5 4410#define IWM_RATE_VHT_SISO_MCS_6_PLCP 6 4411#define IWM_RATE_VHT_SISO_MCS_7_PLCP 7 4412#define IWM_RATE_VHT_SISO_MCS_8_PLCP 8 4413#define IWM_RATE_VHT_SISO_MCS_9_PLCP 9 4414#define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4415#define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4416#define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4417#define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4418#define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4419#define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4420#define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4421#define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4422#define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4423#define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4424#define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20 4425#define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4426#define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4427#define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4428#define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4429#define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4430 4431/* 4432 * These serve as indexes into struct iwm_rate iwm_rates[IWM_RIDX_MAX]. 4433 */ 4434enum { 4435 IWM_RATE_1M_INDEX = 0, 4436 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 4437 IWM_RATE_2M_INDEX, 4438 IWM_RATE_5M_INDEX, 4439 IWM_RATE_11M_INDEX, 4440 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 4441 IWM_RATE_6M_INDEX, 4442 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 4443 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 4444 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 4445 IWM_RATE_9M_INDEX, 4446 IWM_RATE_12M_INDEX, 4447 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 4448 IWM_RATE_MCS_8_INDEX, 4449 IWM_FIRST_HT_MIMO2_RATE = IWM_RATE_MCS_8_INDEX, 4450 IWM_RATE_18M_INDEX, 4451 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 4452 IWM_RATE_24M_INDEX, 4453 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 4454 IWM_RATE_MCS_9_INDEX, 4455 IWM_RATE_36M_INDEX, 4456 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 4457 IWM_RATE_MCS_10_INDEX, 4458 IWM_RATE_48M_INDEX, 4459 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 4460 IWM_RATE_MCS_11_INDEX, 4461 IWM_RATE_54M_INDEX, 4462 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 4463 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 4464 IWM_RATE_MCS_7_INDEX, 4465 IWM_LAST_HT_SISO_RATE = IWM_RATE_MCS_7_INDEX, 4466 IWM_RATE_MCS_12_INDEX, 4467 IWM_RATE_MCS_13_INDEX, 4468 IWM_RATE_MCS_14_INDEX, 4469 IWM_RATE_MCS_15_INDEX, 4470 IWM_LAST_HT_RATE = IWM_RATE_MCS_15_INDEX, 4471 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 4472 IWM_RATE_COUNT = IWM_LAST_HT_RATE + 1, 4473}; 4474 4475#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 4476 4477/* fw API values for legacy bit rates, both OFDM and CCK */ 4478#define IWM_RATE_6M_PLCP 13 4479#define IWM_RATE_9M_PLCP 15 4480#define IWM_RATE_12M_PLCP 5 4481#define IWM_RATE_18M_PLCP 7 4482#define IWM_RATE_24M_PLCP 9 4483#define IWM_RATE_36M_PLCP 11 4484#define IWM_RATE_48M_PLCP 1 4485#define IWM_RATE_54M_PLCP 3 4486#define IWM_RATE_1M_PLCP 10 4487#define IWM_RATE_2M_PLCP 20 4488#define IWM_RATE_5M_PLCP 55 4489#define IWM_RATE_11M_PLCP 110 4490#define IWM_RATE_INVM_PLCP 0xff 4491 4492/* 4493 * rate_n_flags bit fields 4494 * 4495 * The 32-bit value has different layouts in the low 8 bites depending on the 4496 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4497 * for CCK and OFDM). 4498 * 4499 * High-throughput (HT) rate format 4500 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4501 * Very High-throughput (VHT) rate format 4502 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4503 * Legacy OFDM rate format for bits 7:0 4504 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4505 * Legacy CCK rate format for bits 7:0: 4506 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4507 */ 4508 4509/* Bit 8: (1) HT format, (0) legacy or VHT format */ 4510#define IWM_RATE_MCS_HT_POS 8 4511#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 4512 4513/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4514#define IWM_RATE_MCS_CCK_POS 9 4515#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 4516 4517/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4518#define IWM_RATE_MCS_VHT_POS 26 4519#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 4520 4521/* Bit 31: (1) RTS (2) CTS */ 4522#define IWM_RATE_MCS_RTS_REQUIRED_POS 30 4523#define IWM_RATE_MCS_RTS_REQUIRED_MSK (1 << IWM_RATE_MCS_RTS_REQUIRED_POS) 4524 4525/* 4526 * High-throughput (HT) rate format for bits 7:0 4527 * 4528 * 2-0: MCS rate base 4529 * 0) 6 Mbps 4530 * 1) 12 Mbps 4531 * 2) 18 Mbps 4532 * 3) 24 Mbps 4533 * 4) 36 Mbps 4534 * 5) 48 Mbps 4535 * 6) 54 Mbps 4536 * 7) 60 Mbps 4537 * 4-3: 0) Single stream (SISO) 4538 * 1) Dual stream (MIMO) 4539 * 2) Triple stream (MIMO) 4540 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4541 * (bits 7-6 are zero) 4542 * 4543 * Together the low 5 bits work out to the MCS index because we don't 4544 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4545 * streams and 16-23 have three streams. We could also support MCS 32 4546 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4547 */ 4548#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4549#define IWM_RATE_HT_MCS_NSS_POS 3 4550#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4551 4552/* Bit 10: (1) Use Green Field preamble */ 4553#define IWM_RATE_HT_MCS_GF_POS 10 4554#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4555 4556#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4557 4558/* 4559 * Very High-throughput (VHT) rate format for bits 7:0 4560 * 4561 * 3-0: VHT MCS (0-9) 4562 * 5-4: number of streams - 1: 4563 * 0) Single stream (SISO) 4564 * 1) Dual stream (MIMO) 4565 * 2) Triple stream (MIMO) 4566 */ 4567 4568/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4569#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4570#define IWM_RATE_VHT_MCS_NSS_POS 4 4571#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4572 4573/* 4574 * Legacy OFDM rate format for bits 7:0 4575 * 4576 * 3-0: 0xD) 6 Mbps 4577 * 0xF) 9 Mbps 4578 * 0x5) 12 Mbps 4579 * 0x7) 18 Mbps 4580 * 0x9) 24 Mbps 4581 * 0xB) 36 Mbps 4582 * 0x1) 48 Mbps 4583 * 0x3) 54 Mbps 4584 * (bits 7-4 are 0) 4585 * 4586 * Legacy CCK rate format for bits 7:0: 4587 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4588 * 4589 * 6-0: 10) 1 Mbps 4590 * 20) 2 Mbps 4591 * 55) 5.5 Mbps 4592 * 110) 11 Mbps 4593 * (bit 7 is 0) 4594 */ 4595#define IWM_RATE_LEGACY_RATE_MSK 0xff 4596 4597 4598/* 4599 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4600 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4601 */ 4602#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4603#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4604#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4605#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4606#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4607#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4608 4609/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4610#define IWM_RATE_MCS_SGI_POS 13 4611#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4612 4613/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4614#define IWM_RATE_MCS_ANT_POS 14 4615#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4616#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4617#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4618#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4619 IWM_RATE_MCS_ANT_B_MSK) 4620#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4621 IWM_RATE_MCS_ANT_C_MSK) 4622#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4623#define IWM_RATE_MCS_ANT_NUM 3 4624 4625/* Bit 17-18: (0) SS, (1) SS*2 */ 4626#define IWM_RATE_MCS_STBC_POS 17 4627#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4628 4629/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4630#define IWM_RATE_MCS_BF_POS 19 4631#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4632 4633/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4634#define IWM_RATE_MCS_ZLF_POS 20 4635#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4636 4637/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4638#define IWM_RATE_MCS_DUP_POS 24 4639#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4640 4641/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4642#define IWM_RATE_MCS_LDPC_POS 27 4643#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4644 4645 4646/* Link Quality definitions */ 4647 4648/* # entries in rate scale table to support Tx retries */ 4649#define IWM_LQ_MAX_RETRY_NUM 16 4650 4651/* Link quality command flags bit fields */ 4652 4653/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4654#define IWM_LQ_FLAG_USE_RTS_POS 0 4655#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4656 4657/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4658#define IWM_LQ_FLAG_COLOR_POS 1 4659#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4660 4661/* Bit 4-5: Tx RTS BW Signalling 4662 * (0) No RTS BW signalling 4663 * (1) Static BW signalling 4664 * (2) Dynamic BW signalling 4665 */ 4666#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4667#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4668#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4669#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4670 4671/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4672 * Dynamic BW selection allows Tx with narrower BW than requested in rates 4673 */ 4674#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4675#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4676 4677/* Antenna flags. */ 4678#define IWM_ANT_A (1 << 0) 4679#define IWM_ANT_B (1 << 1) 4680#define IWM_ANT_C (1 << 2) 4681/* Shortcuts. */ 4682#define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B) 4683#define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C) 4684#define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C) 4685 4686/** 4687 * struct iwm_lq_cmd - link quality command 4688 * @sta_id: station to update 4689 * @control: not used 4690 * @flags: combination of IWM_LQ_FLAG_* 4691 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4692 * and SISO rates 4693 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4694 * Should be IWM_ANT_[ABC] 4695 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC] 4696 * @initial_rate_index: first index from rs_table per AC category 4697 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4698 * value of 100 is one usec. Range is 100 to 8000 4699 * @agg_disable_start_th: try-count threshold for starting aggregation. 4700 * If a frame has higher try-count, it should not be selected for 4701 * starting an aggregation sequence. 4702 * @agg_frame_cnt_limit: max frame count in an aggregation. 4703 * 0: no limit 4704 * 1: no aggregation (one frame per aggregation) 4705 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4706 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4707 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4708 * @bf_params: beam forming params, currently not used 4709 */ 4710struct iwm_lq_cmd { 4711 uint8_t sta_id; 4712 uint8_t reserved1; 4713 uint16_t control; 4714 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4715 uint8_t flags; 4716 uint8_t mimo_delim; 4717 uint8_t single_stream_ant_msk; 4718 uint8_t dual_stream_ant_msk; 4719 uint8_t initial_rate_index[IWM_AC_NUM]; 4720 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4721 uint16_t agg_time_limit; 4722 uint8_t agg_disable_start_th; 4723 uint8_t agg_frame_cnt_limit; 4724 uint32_t reserved2; 4725 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4726 uint32_t bf_params; 4727}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4728 4729/** 4730 * bitmasks for tx_flags in TX command 4731 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4732 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4733 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4734 * Otherwise, use rate_n_flags from the TX command 4735 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4736 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4737 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4738 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4739 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4740 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4741 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4742 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4743 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4744 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4745 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4746 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4747 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4748 * Should be set for beacons and probe responses 4749 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4750 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4751 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4752 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4753 * Should be set for 26/30 length MAC headers 4754 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4755 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4756 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4757 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4758 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4759 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4760 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4761 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4762 */ 4763#define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0) 4764#define IWM_TX_CMD_FLG_ACK (1 << 3) 4765#define IWM_TX_CMD_FLG_STA_RATE (1 << 4) 4766#define IWM_TX_CMD_FLG_BA (1 << 5) 4767#define IWM_TX_CMD_FLG_BAR (1 << 6) 4768#define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7) 4769#define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8) 4770#define IWM_TX_CMD_FLG_HT_NDPA (1 << 9) 4771#define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10) 4772#define IWM_TX_CMD_FLG_BT_DIS (1 << 12) 4773#define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13) 4774#define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14) 4775#define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15) 4776#define IWM_TX_CMD_FLG_TSF (1 << 16) 4777#define IWM_TX_CMD_FLG_CALIB (1 << 17) 4778#define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18) 4779#define IWM_TX_CMD_FLG_AGG_START (1 << 19) 4780#define IWM_TX_CMD_FLG_MH_PAD (1 << 20) 4781#define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21) 4782#define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22) 4783#define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23) 4784#define IWM_TX_CMD_FLG_DUR (1 << 25) 4785#define IWM_TX_CMD_FLG_FW_DROP (1 << 26) 4786#define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27) 4787#define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28) 4788#define IWM_TX_CMD_FLG_HCCA_CHUNK (1U << 31) 4789/* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4790 4791/* 4792 * TX command security control 4793 */ 4794#define IWM_TX_CMD_SEC_WEP 0x01 4795#define IWM_TX_CMD_SEC_CCM 0x02 4796#define IWM_TX_CMD_SEC_TKIP 0x03 4797#define IWM_TX_CMD_SEC_EXT 0x04 4798#define IWM_TX_CMD_SEC_MSK 0x07 4799#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4800#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4801#define IWM_TX_CMD_SEC_KEY128 0x08 4802 4803/* TODO: how does these values are OK with only 16 bit variable??? */ 4804/* 4805 * TX command next frame info 4806 * 4807 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4808 * bit 3 - immediate ACK required 4809 * bit 4 - rate is taken from STA table 4810 * bit 5 - frame belongs to BA stream 4811 * bit 6 - immediate BA response expected 4812 * bit 7 - unused 4813 * bits 8:15 - Station ID 4814 * bits 16:31 - rate 4815 */ 4816#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4817#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4818#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4819#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4820#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4821#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4822#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4823#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4824#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4825 4826/* 4827 * TX command Frame life time in us - to be written in pm_frame_timeout 4828 */ 4829#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4830#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4831#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4832#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4833 4834/* 4835 * TID for non QoS frames - to be written in tid_tspec 4836 */ 4837#define IWM_MAX_TID_COUNT 8 4838#define IWM_TID_NON_QOS 0 4839#define IWM_TID_MGMT 15 4840 4841/* 4842 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4843 */ 4844#define IWM_DEFAULT_TX_RETRY 15 4845#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4846#define IWM_RTS_DFAULT_RETRY_LIMIT 3 4847#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4848#define IWM_LOW_RETRY_LIMIT 7 4849 4850/** 4851 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values 4852 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 4853 * from mac header end. For normal case it is 4 words for SNAP. 4854 * note: tx_cmd, mac header and pad are not counted in the offset. 4855 * This is used to help the offload in case there is tunneling such as 4856 * IPv6 in IPv4, in such case the ip header offset should point to the 4857 * inner ip header and IPv4 checksum of the external header should be 4858 * calculated by driver. 4859 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 4860 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 4861 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 4862 * field. Doesn't include the pad. 4863 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 4864 * alignment 4865 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 4866 */ 4867#define IWM_TX_CMD_OFFLD_IP_HDR (1 << 0) 4868#define IWM_TX_CMD_OFFLD_L4_EN (1 << 6) 4869#define IWM_TX_CMD_OFFLD_L3_EN (1 << 7) 4870#define IWM_TX_CMD_OFFLD_MH_SIZE (1 << 8) 4871#define IWM_TX_CMD_OFFLD_PAD (1 << 13) 4872#define IWM_TX_CMD_OFFLD_AMSDU (1 << 14) 4873 4874/* TODO: complete documentation for try_cnt and btkill_cnt */ 4875/** 4876 * struct iwm_tx_cmd - TX command struct to FW 4877 * ( IWM_TX_CMD = 0x1c ) 4878 * @len: in bytes of the payload, see below for details 4879 * @offload_assist: TX offload configuration 4880 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4881 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4882 * cleared. Combination of IWM_RATE_MCS_* 4883 * @sta_id: index of destination station in FW station table 4884 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4885 * @initial_rate_index: index into the rate table for initial TX attempt. 4886 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4887 * @key: security key 4888 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4889 * @life_time: frame life time (usecs??) 4890 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4891 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4892 * @dram_msb_ptr: upper bits of the scratch physical address 4893 * @rts_retry_limit: max attempts for RTS 4894 * @data_retry_limit: max attempts to send the data packet 4895 * @tid_spec: TID/tspec 4896 * @pm_frame_timeout: PM TX frame timeout 4897 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4898 * specified by HCCA protocol 4899 * 4900 * The byte count (both len and next_frame_len) includes MAC header 4901 * (24/26/30/32 bytes) 4902 * + 2 bytes pad if 26/30 header size 4903 * + 8 byte IV for CCM or TKIP (not used for WEP) 4904 * + Data payload 4905 * + 8-byte MIC (not used for CCM/WEP) 4906 * It does not include post-MAC padding, i.e., 4907 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4908 * Range of len: 14-2342 bytes. 4909 * 4910 * After the struct fields the MAC header is placed, plus any padding, 4911 * and then the actual payload. 4912 */ 4913struct iwm_tx_cmd { 4914 uint16_t len; 4915 uint16_t offload_assist; 4916 uint32_t tx_flags; 4917 struct { 4918 uint8_t try_cnt; 4919 uint8_t btkill_cnt; 4920 uint16_t reserved; 4921 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4922 uint32_t rate_n_flags; 4923 uint8_t sta_id; 4924 uint8_t sec_ctl; 4925 uint8_t initial_rate_index; 4926 uint8_t reserved2; 4927 uint8_t key[16]; 4928 uint32_t reserved3; 4929 uint32_t life_time; 4930 uint32_t dram_lsb_ptr; 4931 uint8_t dram_msb_ptr; 4932 uint8_t rts_retry_limit; 4933 uint8_t data_retry_limit; 4934 uint8_t tid_tspec; 4935 uint16_t pm_frame_timeout; 4936 uint16_t reserved4; 4937 uint8_t payload[0]; 4938 struct ieee80211_frame hdr[0]; 4939} __packed; /* IWM_TX_CMD_API_S_VER_6 */ 4940 4941/* 4942 * TX response related data 4943 */ 4944 4945/* 4946 * status that is returned by the fw after attempts to Tx 4947 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4948 * STA table 4949 * Valid only if frame_count =1 4950 */ 4951#define IWM_TX_STATUS_MSK 0x000000ff 4952#define IWM_TX_STATUS_SUCCESS 0x01 4953#define IWM_TX_STATUS_DIRECT_DONE 0x02 4954/* postpone TX */ 4955#define IWM_TX_STATUS_POSTPONE_DELAY 0x40 4956#define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41 4957#define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42 4958#define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 4959#define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44 4960/* abort TX */ 4961#define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 4962#define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82 4963#define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83 4964#define IWM_TX_STATUS_FAIL_UNDERRUN 0x84 4965#define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85 4966#define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 4967#define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 4968#define IWM_TX_STATUS_FAIL_DEST_PS 0x88 4969#define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89 4970#define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a 4971#define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b 4972#define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 4973#define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d 4974#define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 4975#define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 4976#define IWM_TX_STATUS_FAIL_FW_DROP 0x90 4977#define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 4978#define IWM_TX_STATUS_INTERNAL_ABORT 0x92 4979#define IWM_TX_MODE_MSK 0x00000f00 4980#define IWM_TX_MODE_NO_BURST 0x00000000 4981#define IWM_TX_MODE_IN_BURST_SEQ 0x00000100 4982#define IWM_TX_MODE_FIRST_IN_BURST 0x00000200 4983#define IWM_TX_QUEUE_NUM_MSK 0x0001f000 4984#define IWM_TX_NARROW_BW_MSK 0x00060000 4985#define IWM_TX_NARROW_BW_1DIV2 0x00020000 4986#define IWM_TX_NARROW_BW_1DIV4 0x00040000 4987#define IWM_TX_NARROW_BW_1DIV8 0x00060000 4988 4989/* 4990 * TX aggregation status 4991 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4992 * occur if tx failed for this frame when it was a member of a previous 4993 * aggregation block). If rate scaling is used, retry count indicates the 4994 * rate table entry used for all frames in the new agg. 4995 */ 4996#define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff 4997#define IWM_AGG_TX_STATE_TRANSMITTED 0x0000 4998#define IWM_AGG_TX_STATE_UNDERRUN 0x0001 4999#define IWM_AGG_TX_STATE_BT_PRIO 0x0002 5000#define IWM_AGG_TX_STATE_FEW_BYTES 0x0004 5001#define IWM_AGG_TX_STATE_ABORT 0x0008 5002#define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010 5003#define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 5004#define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 5005#define IWM_AGG_TX_STATE_SCD_QUERY 0x0080 5006#define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 5007#define IWM_AGG_TX_STATE_RESPONSE 0x01ff 5008#define IWM_AGG_TX_STATE_DUMP_TX 0x0200 5009#define IWM_AGG_TX_STATE_DELAY_TX 0x0400 5010#define IWM_AGG_TX_STATE_TRY_CNT_POS 12 5011#define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS) 5012 5013#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 5014 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 5015 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 5016 5017/* 5018 * The mask below describes a status where we are absolutely sure that the MPDU 5019 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 5020 * written the bytes to the TXE, but we know nothing about what the DSP did. 5021 */ 5022#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 5023 IWM_AGG_TX_STATE_ABORT | \ 5024 IWM_AGG_TX_STATE_SCD_QUERY) 5025 5026/* 5027 * IWM_REPLY_TX = 0x1c (response) 5028 * 5029 * This response may be in one of two slightly different formats, indicated 5030 * by the frame_count field: 5031 * 5032 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 5033 * frame. Multiple attempts, at various bit rates, may have been made for 5034 * this frame. 5035 * 5036 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 5037 * frames that used block-acknowledge. All frames were transmitted at 5038 * same rate. Rate scaling may have been used if first frame in this new 5039 * agg block failed in previous agg block(s). 5040 * 5041 * Note that, for aggregation, ACK (block-ack) status is not delivered 5042 * here; block-ack has not been received by the time the device records 5043 * this status. 5044 * This status relates to reasons the tx might have been blocked or aborted 5045 * within the device, rather than whether it was received successfully by 5046 * the destination station. 5047 */ 5048 5049/** 5050 * struct iwm_agg_tx_status - per packet TX aggregation status 5051 * @status: IWM_AGG_TX_STATE_* 5052 * @idx: Tx queue index of this frame 5053 * @qid: Tx queue ID of this frame 5054 */ 5055struct iwm_agg_tx_status { 5056 uint16_t status; 5057 uint8_t idx; 5058 uint8_t qid; 5059} __packed; 5060 5061/* 5062 * definitions for initial rate index field 5063 * bits [3:0] initial rate index 5064 * bits [6:4] rate table color, used for the initial rate 5065 * bit-7 invalid rate indication 5066 */ 5067#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 5068#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 5069#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 5070 5071#define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 5072#define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 5073 5074/** 5075 * struct iwm_tx_resp - notifies that fw is TXing a packet 5076 * ( IWM_REPLY_TX = 0x1c ) 5077 * @frame_count: 1 no aggregation, >1 aggregation 5078 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5079 * @failure_rts: num of failures due to unsuccessful RTS 5080 * @failure_frame: num failures due to no ACK (unused for agg) 5081 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5082 * Tx of all the batch. IWM_RATE_MCS_* 5083 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5084 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5085 * in usec. 5086 * @pa_status: tx power info 5087 * @pa_integ_res_a: tx power info 5088 * @pa_integ_res_b: tx power info 5089 * @pa_integ_res_c: tx power info 5090 * @measurement_req_id: tx power info 5091 * @tfd_info: TFD information set by the FH 5092 * @seq_ctl: sequence control field from IEEE80211 frame header 5093 * @byte_cnt: byte count from the Tx cmd 5094 * @tlc_info: TLC rate info 5095 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5096 * @frame_ctrl: frame control 5097 * @status: for non-agg: frame status IWM_TX_STATUS_* 5098 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 5099 * follow this one, up to frame_count. 5100 * 5101 * After the array of statuses comes the SSN of the SCD. Look at 5102 * %iwm_get_scd_ssn for more details. 5103 */ 5104struct iwm_tx_resp { 5105 uint8_t frame_count; 5106 uint8_t bt_kill_count; 5107 uint8_t failure_rts; 5108 uint8_t failure_frame; 5109 uint32_t initial_rate; 5110 uint16_t wireless_media_time; 5111 5112 uint8_t pa_status; 5113 uint8_t pa_integ_res_a[3]; 5114 uint8_t pa_integ_res_b[3]; 5115 uint8_t pa_integ_res_c[3]; 5116 uint16_t measurement_req_id; 5117 uint16_t reserved; 5118 5119 uint32_t tfd_info; 5120 uint16_t seq_ctl; 5121 uint16_t byte_cnt; 5122 uint8_t tlc_info; 5123 uint8_t ra_tid; 5124 uint16_t frame_ctrl; 5125 5126 struct iwm_agg_tx_status status; 5127} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 5128 5129/** 5130 * struct iwm_ba_notif - notifies about reception of BA 5131 * ( IWM_BA_NOTIF = 0xc5 ) 5132 * @sta_addr: MAC address 5133 * @sta_id: Index of recipient (BA-sending) station in fw's station table 5134 * @tid: tid of the session 5135 * @seq_ctl: sequence control field from IEEE80211 frame header (the first 5136 * bit in @bitmap corresponds to the sequence number stored here) 5137 * @bitmap: the bitmap of the BA notification as seen in the air 5138 * @scd_flow: the tx queue this BA relates to 5139 * @scd_ssn: the index of the last contiguously sent packet 5140 * @txed: number of Txed frames in this batch 5141 * @txed_2_done: number of Acked frames in this batch 5142 * @reduced_txp: power reduced according to TPC. This is the actual value and 5143 * not a copy from the LQ command. Thus, if not the first rate was used 5144 * for Tx-ing then this value will be set to 0 by FW. 5145 * @reserved1: reserved 5146 */ 5147struct iwm_ba_notif { 5148 uint8_t sta_addr[ETHER_ADDR_LEN]; 5149 uint16_t reserved; 5150 5151 uint8_t sta_id; 5152 uint8_t tid; 5153 uint16_t seq_ctl; 5154 uint64_t bitmap; 5155 uint16_t scd_flow; 5156 uint16_t scd_ssn; 5157 uint8_t txed; 5158 uint8_t txed_2_done; 5159 uint8_t reduced_txp; 5160 uint8_t reserved1; 5161} __packed; 5162 5163/* 5164 * struct iwm_mac_beacon_cmd - beacon template command 5165 * @tx: the tx commands associated with the beacon frame 5166 * @template_id: currently equal to the mac context id of the corresponding 5167 * mac. 5168 * @tim_idx: the offset of the tim IE in the beacon 5169 * @tim_size: the length of the tim IE 5170 * @frame: the template of the beacon frame 5171 */ 5172struct iwm_mac_beacon_cmd { 5173 struct iwm_tx_cmd tx; 5174 uint32_t template_id; 5175 uint32_t tim_idx; 5176 uint32_t tim_size; 5177 struct ieee80211_frame frame[0]; 5178} __packed; 5179 5180struct iwm_beacon_notif { 5181 struct iwm_tx_resp beacon_notify_hdr; 5182 uint64_t tsf; 5183 uint32_t ibss_mgr_status; 5184} __packed; 5185 5186/** 5187 * dump (flush) control flags 5188 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 5189 * and the TFD queues are empty. 5190 */ 5191#define IWM_DUMP_TX_FIFO_FLUSH (1 << 1) 5192 5193/** 5194 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 5195 * @queues_ctl: bitmap of queues to flush 5196 * @flush_ctl: control flags 5197 * @reserved: reserved 5198 */ 5199struct iwm_tx_path_flush_cmd_v1 { 5200 uint32_t queues_ctl; 5201 uint16_t flush_ctl; 5202 uint16_t reserved; 5203} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 5204 5205/** 5206 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 5207 * @sta_id: station ID to flush 5208 * @tid_mask: TID mask to flush 5209 * @reserved: reserved 5210 */ 5211struct iwm_tx_path_flush_cmd { 5212 uint32_t sta_id; 5213 uint16_t tid_mask; 5214 uint16_t reserved; 5215} __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 5216 5217/** 5218 * iwm_get_scd_ssn - returns the SSN of the SCD 5219 * @tx_resp: the Tx response from the fw (agg or non-agg) 5220 * 5221 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 5222 * it can't know that everything will go well until the end of the AMPDU, it 5223 * can't know in advance the number of MPDUs that will be sent in the current 5224 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 5225 * Hence, it can't know in advance what the SSN of the SCD will be at the end 5226 * of the batch. This is why the SSN of the SCD is written at the end of the 5227 * whole struct at a variable offset. This function knows how to cope with the 5228 * variable offset and returns the SSN of the SCD. 5229 */ 5230static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp) 5231{ 5232 return le32_to_cpup((uint32_t *)&tx_resp->status + 5233 tx_resp->frame_count) & 0xfff; 5234} 5235 5236/** 5237 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 5238 * @token: 5239 * @sta_id: station id 5240 * @tid: 5241 * @scd_queue: scheduler queue to config 5242 * @enable: 1 queue enable, 0 queue disable 5243 * @aggregate: 1 aggregated queue, 0 otherwise 5244 * @tx_fifo: %enum iwm_tx_fifo 5245 * @window: BA window size 5246 * @ssn: SSN for the BA agreement 5247 */ 5248struct iwm_scd_txq_cfg_cmd { 5249 uint8_t token; 5250 uint8_t sta_id; 5251 uint8_t tid; 5252 uint8_t scd_queue; 5253 uint8_t enable; 5254 uint8_t aggregate; 5255 uint8_t tx_fifo; 5256 uint8_t window; 5257 uint16_t ssn; 5258 uint16_t reserved; 5259} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 5260 5261/** 5262 * struct iwm_scd_txq_cfg_rsp 5263 * @token: taken from the command 5264 * @sta_id: station id from the command 5265 * @tid: tid from the command 5266 * @scd_queue: scd_queue from the command 5267 */ 5268struct iwm_scd_txq_cfg_rsp { 5269 uint8_t token; 5270 uint8_t sta_id; 5271 uint8_t tid; 5272 uint8_t scd_queue; 5273} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 5274 5275 5276/* Scan Commands, Responses, Notifications */ 5277 5278/* Max number of IEs for direct SSID scans in a command */ 5279#define IWM_PROBE_OPTION_MAX 20 5280 5281/** 5282 * struct iwm_ssid_ie - directed scan network information element 5283 * 5284 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 5285 * selected by "type" bit field in struct iwm_scan_channel; 5286 * each channel may select different ssids from among the 20 entries. 5287 * SSID IEs get transmitted in reverse order of entry. 5288 */ 5289struct iwm_ssid_ie { 5290 uint8_t id; 5291 uint8_t len; 5292 uint8_t ssid[IEEE80211_NWID_LEN]; 5293} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5294 5295/* scan offload */ 5296#define IWM_SCAN_MAX_BLACKLIST_LEN 64 5297#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 5298#define IWM_SCAN_MAX_PROFILES 11 5299#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 5300 5301/* Default watchdog (in MS) for scheduled scan iteration */ 5302#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 5303 5304#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 5305#define IWM_CAN_ABORT_STATUS 1 5306 5307#define IWM_FULL_SCAN_MULTIPLIER 5 5308#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 5309#define IWM_MAX_SCHED_SCAN_PLANS 2 5310 5311/** 5312 * iwm_scan_schedule_lmac - schedule of scan offload 5313 * @delay: delay between iterations, in seconds. 5314 * @iterations: num of scan iterations 5315 * @full_scan_mul: number of partial scans before each full scan 5316 */ 5317struct iwm_scan_schedule_lmac { 5318 uint16_t delay; 5319 uint8_t iterations; 5320 uint8_t full_scan_mul; 5321} __packed; /* SCAN_SCHEDULE_API_S */ 5322 5323/** 5324 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5325 * @tx_flags: combination of TX_CMD_FLG_* 5326 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5327 * cleared. Combination of RATE_MCS_* 5328 * @sta_id: index of destination station in FW station table 5329 * @reserved: for alignment and future use 5330 */ 5331struct iwm_scan_req_tx_cmd { 5332 uint32_t tx_flags; 5333 uint32_t rate_n_flags; 5334 uint8_t sta_id; 5335 uint8_t reserved[3]; 5336} __packed; 5337 5338#define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 5339#define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 5340 5341/** 5342 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5343 * @flags: bits 1-20: directed scan to i'th ssid 5344 * other bits &enum iwm_scan_channel_flags_lmac 5345 * @channel_number: channel number 1-13 etc 5346 * @iter_count: scan iteration on this channel 5347 * @iter_interval: interval in seconds between iterations on one channel 5348 */ 5349struct iwm_scan_channel_cfg_lmac { 5350 uint32_t flags; 5351 uint16_t channel_num; 5352 uint16_t iter_count; 5353 uint32_t iter_interval; 5354} __packed; 5355 5356/* 5357 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5358 * @offset: offset in the data block 5359 * @len: length of the segment 5360 */ 5361struct iwm_scan_probe_segment { 5362 uint16_t offset; 5363 uint16_t len; 5364} __packed; 5365 5366/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5367 * @mac_header: first (and common) part of the probe 5368 * @band_data: band specific data 5369 * @common_data: last (and common) part of the probe 5370 * @buf: raw data block 5371 */ 5372struct iwm_scan_probe_req_v1 { 5373 struct iwm_scan_probe_segment mac_header; 5374 struct iwm_scan_probe_segment band_data[2]; 5375 struct iwm_scan_probe_segment common_data; 5376 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5377} __packed; 5378 5379/* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 5380 * @mac_header: first (and common) part of the probe 5381 * @band_data: band specific data 5382 * @common_data: last (and common) part of the probe 5383 * @buf: raw data block 5384 */ 5385struct iwm_scan_probe_req { 5386 struct iwm_scan_probe_segment mac_header; 5387 struct iwm_scan_probe_segment band_data[3]; 5388 struct iwm_scan_probe_segment common_data; 5389 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5390} __packed; 5391 5392 5393#define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0) 5394#define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 5395#define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 5396 5397/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5398 * @flags: enum iwm_scan_channel_flags 5399 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5400 * involved. 5401 * 1 - EBS is disabled. 5402 * 2 - every second scan will be full scan(and so on). 5403 */ 5404struct iwm_scan_channel_opt { 5405 uint16_t flags; 5406 uint16_t non_ebs_ratio; 5407} __packed; 5408 5409/** 5410 * LMAC scan flags 5411 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 5412 * without filtering. 5413 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 5414 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 5415 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 5416 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 5417 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 5418 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 5419 * and DS parameter set IEs into probe requests. 5420 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 5421 * 1, 6 and 11. 5422 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 5423 */ 5424#define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0) 5425#define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1) 5426#define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2) 5427#define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3) 5428#define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4) 5429#define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5) 5430#define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6) 5431#define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7) 5432#define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9) 5433 5434#define IWM_SCAN_PRIORITY_LOW 0 5435#define IWM_SCAN_PRIORITY_MEDIUM 1 5436#define IWM_SCAN_PRIORITY_HIGH 2 5437 5438/** 5439 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5440 * @reserved1: for alignment and future use 5441 * @channel_num: num of channels to scan 5442 * @active-dwell: dwell time for active channels 5443 * @passive-dwell: dwell time for passive channels 5444 * @fragmented-dwell: dwell time for fragmented passive scan 5445 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5446 * @reserved2: for alignment and future use 5447 * @rx_chain_selct: PHY_RX_CHAIN_* flags 5448 * @scan_flags: &enum iwm_lmac_scan_flags 5449 * @max_out_time: max time (in TU) to be out of associated channel 5450 * @suspend_time: pause scan this long (TUs) when returning to service channel 5451 * @flags: RXON flags 5452 * @filter_flags: RXON filter 5453 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5454 * @direct_scan: list of SSIDs for directed active scan 5455 * @scan_prio: enum iwm_scan_priority 5456 * @iter_num: number of scan iterations 5457 * @delay: delay in seconds before first iteration 5458 * @schedule: two scheduling plans. The first one is finite, the second one can 5459 * be infinite. 5460 * @channel_opt: channel optimization options, for full and partial scan 5461 * @data: channel configuration and probe request packet. 5462 */ 5463struct iwm_scan_req_lmac { 5464 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5465 uint32_t reserved1; 5466 uint8_t n_channels; 5467 uint8_t active_dwell; 5468 uint8_t passive_dwell; 5469 uint8_t fragmented_dwell; 5470 uint8_t extended_dwell; 5471 uint8_t reserved2; 5472 uint16_t rx_chain_select; 5473 uint32_t scan_flags; 5474 uint32_t max_out_time; 5475 uint32_t suspend_time; 5476 /* RX_ON_FLAGS_API_S_VER_1 */ 5477 uint32_t flags; 5478 uint32_t filter_flags; 5479 struct iwm_scan_req_tx_cmd tx_cmd[2]; 5480 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5481 uint32_t scan_prio; 5482 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5483 uint32_t iter_num; 5484 uint32_t delay; 5485 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5486 struct iwm_scan_channel_opt channel_opt[2]; 5487 uint8_t data[]; 5488} __packed; 5489 5490/** 5491 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5492 * @last_schedule_line: last schedule line executed (fast or regular) 5493 * @last_schedule_iteration: last scan iteration executed before scan abort 5494 * @status: enum iwm_scan_offload_complete_status 5495 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5496 * @time_after_last_iter; time in seconds elapsed after last iteration 5497 */ 5498struct iwm_periodic_scan_complete { 5499 uint8_t last_schedule_line; 5500 uint8_t last_schedule_iteration; 5501 uint8_t status; 5502 uint8_t ebs_status; 5503 uint32_t time_after_last_iter; 5504 uint32_t reserved; 5505} __packed; 5506 5507/** 5508 * struct iwm_scan_results_notif - scan results for one channel - 5509 * SCAN_RESULT_NTF_API_S_VER_3 5510 * @channel: which channel the results are from 5511 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5512 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5513 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5514 * @duration: duration spent in channel, in usecs 5515 */ 5516struct iwm_scan_results_notif { 5517 uint8_t channel; 5518 uint8_t band; 5519 uint8_t probe_status; 5520 uint8_t num_probe_not_sent; 5521 uint32_t duration; 5522} __packed; 5523 5524#define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0) 5525#define IWM_SCAN_CLIENT_NETDETECT (1 << 1) 5526#define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 5527 5528/** 5529 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5530 * @ssid: MAC address to filter out 5531 * @reported_rssi: AP rssi reported to the host 5532 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5533 */ 5534struct iwm_scan_offload_blacklist { 5535 uint8_t ssid[ETHER_ADDR_LEN]; 5536 uint8_t reported_rssi; 5537 uint8_t client_bitmap; 5538} __packed; 5539 5540#define IWM_NETWORK_TYPE_BSS 1 5541#define IWM_NETWORK_TYPE_IBSS 2 5542#define IWM_NETWORK_TYPE_ANY 3 5543 5544#define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4 5545#define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8 5546#define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc 5547 5548/** 5549 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5550 * @ssid_index: index to ssid list in fixed part 5551 * @unicast_cipher: encryption algorithm to match - bitmap 5552 * @aut_alg: authentication algorithm to match - bitmap 5553 * @network_type: enum iwm_scan_offload_network_type 5554 * @band_selection: enum iwm_scan_offload_band_selection 5555 * @client_bitmap: clients waiting for match - enum scan_framework_client 5556 */ 5557struct iwm_scan_offload_profile { 5558 uint8_t ssid_index; 5559 uint8_t unicast_cipher; 5560 uint8_t auth_alg; 5561 uint8_t network_type; 5562 uint8_t band_selection; 5563 uint8_t client_bitmap; 5564 uint8_t reserved[2]; 5565} __packed; 5566 5567/** 5568 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5569 * @blacklist: AP list to filter off from scan results 5570 * @profiles: profiles to search for match 5571 * @blacklist_len: length of blacklist 5572 * @num_profiles: num of profiles in the list 5573 * @match_notify: clients waiting for match found notification 5574 * @pass_match: clients waiting for the results 5575 * @active_clients: active clients bitmap - enum scan_framework_client 5576 * @any_beacon_notify: clients waiting for match notification without match 5577 */ 5578struct iwm_scan_offload_profile_cfg { 5579 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5580 uint8_t blacklist_len; 5581 uint8_t num_profiles; 5582 uint8_t match_notify; 5583 uint8_t pass_match; 5584 uint8_t active_clients; 5585 uint8_t any_beacon_notify; 5586 uint8_t reserved[2]; 5587} __packed; 5588 5589#define IWM_SCAN_OFFLOAD_COMPLETED 1 5590#define IWM_SCAN_OFFLOAD_ABORTED 2 5591 5592/** 5593 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5594 * SCAN_COMPLETE_NTF_API_S_VER_3 5595 * @scanned_channels: number of channels scanned (and number of valid results) 5596 * @status: one of SCAN_COMP_STATUS_* 5597 * @bt_status: BT on/off status 5598 * @last_channel: last channel that was scanned 5599 * @tsf_low: TSF timer (lower half) in usecs 5600 * @tsf_high: TSF timer (higher half) in usecs 5601 * @results: an array of scan results, only "scanned_channels" of them are valid 5602 */ 5603struct iwm_lmac_scan_complete_notif { 5604 uint8_t scanned_channels; 5605 uint8_t status; 5606 uint8_t bt_status; 5607 uint8_t last_channel; 5608 uint32_t tsf_low; 5609 uint32_t tsf_high; 5610 struct iwm_scan_results_notif results[]; 5611} __packed; 5612 5613 5614/* UMAC Scan API */ 5615 5616/* The maximum of either of these cannot exceed 8, because we use an 5617 * 8-bit mask (see IWM_SCAN_MASK). 5618 */ 5619#define IWM_MAX_UMAC_SCANS 8 5620#define IWM_MAX_LMAC_SCANS 1 5621 5622#define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 5623#define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 5624#define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 5625#define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 5626#define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 5627#define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 5628#define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 5629#define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 5630#define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 5631#define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 5632#define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 5633#define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 5634#define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 5635#define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 5636#define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 5637#define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 5638#define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 5639#define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 5640 5641/* Bits 26-31 are for num of channels in channel_array */ 5642#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5643 5644/* OFDM basic rates */ 5645#define IWM_SCAN_CONFIG_RATE_6M (1 << 0) 5646#define IWM_SCAN_CONFIG_RATE_9M (1 << 1) 5647#define IWM_SCAN_CONFIG_RATE_12M (1 << 2) 5648#define IWM_SCAN_CONFIG_RATE_18M (1 << 3) 5649#define IWM_SCAN_CONFIG_RATE_24M (1 << 4) 5650#define IWM_SCAN_CONFIG_RATE_36M (1 << 5) 5651#define IWM_SCAN_CONFIG_RATE_48M (1 << 6) 5652#define IWM_SCAN_CONFIG_RATE_54M (1 << 7) 5653/* CCK basic rates */ 5654#define IWM_SCAN_CONFIG_RATE_1M (1 << 8) 5655#define IWM_SCAN_CONFIG_RATE_2M (1 << 9) 5656#define IWM_SCAN_CONFIG_RATE_5M (1 << 10) 5657#define IWM_SCAN_CONFIG_RATE_11M (1 << 11) 5658 5659/* Bits 16-27 are for supported rates */ 5660#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5661 5662#define IWM_CHANNEL_FLAG_EBS (1 << 0) 5663#define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 5664#define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2) 5665#define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 5666 5667/** 5668 * struct iwm_scan_config 5669 * @flags: enum scan_config_flags 5670 * @tx_chains: valid_tx antenna - ANT_* definitions 5671 * @rx_chains: valid_rx antenna - ANT_* definitions 5672 * @legacy_rates: default legacy rates - enum scan_config_rates 5673 * @out_of_channel_time: default max out of serving channel time 5674 * @suspend_time: default max suspend time 5675 * @dwell_active: default dwell time for active scan 5676 * @dwell_passive: default dwell time for passive scan 5677 * @dwell_fragmented: default dwell time for fragmented scan 5678 * @dwell_extended: default dwell time for channels 1, 6 and 11 5679 * @mac_addr: default mac address to be used in probes 5680 * @bcast_sta_id: the index of the station in the fw 5681 * @channel_flags: default channel flags - enum iwm_channel_flags 5682 * scan_config_channel_flag 5683 * @channel_array: default supported channels 5684 */ 5685struct iwm_scan_config { 5686 uint32_t flags; 5687 uint32_t tx_chains; 5688 uint32_t rx_chains; 5689 uint32_t legacy_rates; 5690 uint32_t out_of_channel_time; 5691 uint32_t suspend_time; 5692 uint8_t dwell_active; 5693 uint8_t dwell_passive; 5694 uint8_t dwell_fragmented; 5695 uint8_t dwell_extended; 5696 uint8_t mac_addr[ETHER_ADDR_LEN]; 5697 uint8_t bcast_sta_id; 5698 uint8_t channel_flags; 5699 uint8_t channel_array[]; 5700} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5701 5702/** 5703 * iwm_umac_scan_flags 5704 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5705 * can be preempted by other scan requests with higher priority. 5706 * The low priority scan will be resumed when the higher priority scan is 5707 * completed. 5708 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5709 * when scan starts. 5710 */ 5711#define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 5712#define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 5713 5714#define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0 5715#define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8 5716 5717#define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 5718#define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 5719#define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 5720#define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 5721#define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 5722#define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 5723#define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 5724#define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 5725#define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 5726#define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 5727#define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 5728/* Extended dwell is obsolete when adaptive dwell is used, making this 5729 * bit reusable. Hence, probe request defer is used only when adaptive 5730 * dwell is supported. */ 5731#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 5732#define IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 5733#define IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 5734#define IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 5735#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 5736 5737/** 5738 * UMAC scan general flags #2 5739 * @IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 5740 * notification per channel or not. 5741 * @IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 5742 * reorder optimization or not. 5743 */ 5744#define IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 5745#define IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 5746 5747/** 5748 * struct iwm_scan_channel_cfg_umac 5749 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5750 * @channel_num: channel number 1-13 etc. 5751 * @iter_count: repetition count for the channel. 5752 * @iter_interval: interval between two scan iterations on one channel. 5753 */ 5754struct iwm_scan_channel_cfg_umac { 5755 uint32_t flags; 5756 uint8_t channel_num; 5757 uint8_t iter_count; 5758 uint16_t iter_interval; 5759} __packed; /* SCAN_CHANNEL_CFG_S_VER1 */ 5760 5761/** 5762 * struct iwm_scan_umac_schedule 5763 * @interval: interval in seconds between scan iterations 5764 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5765 * @reserved: for alignment and future use 5766 */ 5767struct iwm_scan_umac_schedule { 5768 uint16_t interval; 5769 uint8_t iter_count; 5770 uint8_t reserved; 5771} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5772 5773/** 5774 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5775 * parameters following channels configuration array. 5776 * @schedule: two scheduling plans. 5777 * @delay: delay in TUs before starting the first scan iteration 5778 * @reserved: for future use and alignment 5779 * @preq: probe request with IEs blocks 5780 * @direct_scan: list of SSIDs for directed active scan 5781 */ 5782struct iwm_scan_req_umac_tail_v1 { 5783 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5784 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5785 uint16_t delay; 5786 uint16_t reserved; 5787 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5788 struct iwm_scan_probe_req_v1 preq; 5789 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5790} __packed; 5791 5792/** 5793 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5794 * parameters following channels configuration array. 5795 * @schedule: two scheduling plans. 5796 * @delay: delay in TUs before starting the first scan iteration 5797 * @reserved: for future use and alignment 5798 * @preq: probe request with IEs blocks 5799 * @direct_scan: list of SSIDs for directed active scan 5800 */ 5801struct iwm_scan_req_umac_tail_v2 { 5802 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5803 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5804 uint16_t delay; 5805 uint16_t reserved; 5806 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 5807 struct iwm_scan_probe_req preq; 5808 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5809} __packed; 5810 5811/** 5812 * struct iwm_scan_umac_chan_param 5813 * @flags: channel flags &enum iwl_scan_channel_flags 5814 * @count: num of channels in scan request 5815 * @reserved: for future use and alignment 5816 */ 5817struct iwm_scan_umac_chan_param { 5818 uint8_t flags; 5819 uint8_t count; 5820 uint16_t reserved; 5821} __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5822 5823#define IWM_SCAN_LB_LMAC_IDX 0 5824#define IWM_SCAN_HB_LMAC_IDX 1 5825 5826/** 5827 * struct iwm_scan_req_umac 5828 * @flags: &enum iwl_umac_scan_flags 5829 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 5830 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 5831 * @general_flags: &enum iwl_umac_scan_general_flags 5832 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 5833 * @extended_dwell: dwell time for channels 1, 6 and 11 5834 * @active_dwell: dwell time for active scan per LMAC 5835 * @passive_dwell: dwell time for passive scan per LMAC 5836 * @fragmented_dwell: dwell time for fragmented passive scan 5837 * @adwell_default_n_aps: for adaptive dwell the default number of APs 5838 * per channel 5839 * @adwell_default_n_aps_social: for adaptive dwell the default 5840 * number of APs per social (1,6,11) channel 5841 * @general_flags2: &enum iwl_umac_scan_general_flags2 5842 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 5843 * to total scan time 5844 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 5845 * are 2 LMACs (high band and low band) 5846 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 5847 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 5848 * @num_of_fragments: Number of fragments needed for full coverage per band. 5849 * Relevant only for fragmented scan. 5850 * @channel: &struct iwm_scan_umac_chan_param 5851 * @reserved: for future use and alignment 5852 * @reserved3: for future use and alignment 5853 * @data: &struct iwm_scan_channel_cfg_umac and 5854 * &struct iwm_scan_req_umac_tail 5855 */ 5856struct iwm_scan_req_umac { 5857 uint32_t flags; 5858 uint32_t uid; 5859 uint32_t ooc_priority; 5860 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5861 uint16_t general_flags; 5862 uint8_t reserved; 5863 uint8_t scan_start_mac_id; 5864 union { 5865 struct { 5866 uint8_t extended_dwell; 5867 uint8_t active_dwell; 5868 uint8_t passive_dwell; 5869 uint8_t fragmented_dwell; 5870 uint32_t max_out_time; 5871 uint32_t suspend_time; 5872 uint32_t scan_priority; 5873 struct iwm_scan_umac_chan_param channel; 5874 uint8_t data[]; 5875 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5876 struct { 5877 uint8_t extended_dwell; 5878 uint8_t active_dwell; 5879 uint8_t passive_dwell; 5880 uint8_t fragmented_dwell; 5881 uint32_t max_out_time[2]; 5882 uint32_t suspend_time[2]; 5883 uint32_t scan_priority; 5884 struct iwm_scan_umac_chan_param channel; 5885 uint8_t data[]; 5886 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 5887 struct { 5888 uint8_t active_dwell; 5889 uint8_t passive_dwell; 5890 uint8_t fragmented_dwell; 5891 uint8_t adwell_default_n_aps; 5892 uint8_t adwell_default_n_aps_social; 5893 uint8_t reserved3; 5894 uint16_t adwell_max_budget; 5895 uint32_t max_out_time[2]; 5896 uint32_t suspend_time[2]; 5897 uint32_t scan_priority; 5898 struct iwm_scan_umac_chan_param channel; 5899 uint8_t data[]; 5900 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 5901 struct { 5902 uint8_t active_dwell[2]; 5903 uint8_t reserved2; 5904 uint8_t adwell_default_n_aps; 5905 uint8_t adwell_default_n_aps_social; 5906 uint8_t general_flags2; 5907 uint16_t adwell_max_budget; 5908 uint32_t max_out_time[2]; 5909 uint32_t suspend_time[2]; 5910 uint32_t scan_priority; 5911 uint8_t passive_dwell[2]; 5912 uint8_t num_of_fragments[2]; 5913 struct iwm_scan_umac_chan_param channel; 5914 uint8_t data[]; 5915 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 5916 struct { 5917 uint8_t active_dwell[2]; 5918 uint8_t adwell_default_hb_n_aps; 5919 uint8_t adwell_default_lb_n_aps; 5920 uint8_t adwell_default_n_aps_social; 5921 uint8_t general_flags2; 5922 uint16_t adwell_max_budget; 5923 uint32_t max_out_time[2]; 5924 uint32_t suspend_time[2]; 5925 uint32_t scan_priority; 5926 uint8_t passive_dwell[2]; 5927 uint8_t num_of_fragments[2]; 5928 struct iwm_scan_umac_chan_param channel; 5929 uint8_t data[]; 5930 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 5931 }; 5932} __packed; 5933 5934#define IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac) 5935#define IWM_SCAN_REQ_UMAC_SIZE_V7 48 5936#define IWM_SCAN_REQ_UMAC_SIZE_V6 44 5937#define IWM_SCAN_REQ_UMAC_SIZE_V1 36 5938 5939/** 5940 * struct iwm_umac_scan_abort 5941 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5942 * @flags: reserved 5943 */ 5944struct iwm_umac_scan_abort { 5945 uint32_t uid; 5946 uint32_t flags; 5947} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5948 5949/** 5950 * struct iwm_umac_scan_complete 5951 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5952 * @last_schedule: last scheduling line 5953 * @last_iter: last scan iteration number 5954 * @scan status: &enum iwm_scan_offload_complete_status 5955 * @ebs_status: &enum iwm_scan_ebs_status 5956 * @time_from_last_iter: time elapsed from last iteration 5957 * @reserved: for future use 5958 */ 5959struct iwm_umac_scan_complete { 5960 uint32_t uid; 5961 uint8_t last_schedule; 5962 uint8_t last_iter; 5963 uint8_t status; 5964 uint8_t ebs_status; 5965 uint32_t time_from_last_iter; 5966 uint32_t reserved; 5967} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5968 5969#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5970/** 5971 * struct iwm_scan_offload_profile_match - match information 5972 * @bssid: matched bssid 5973 * @channel: channel where the match occurred 5974 * @energy: 5975 * @matching_feature: 5976 * @matching_channels: bitmap of channels that matched, referencing 5977 * the channels passed in tue scan offload request 5978 */ 5979struct iwm_scan_offload_profile_match { 5980 uint8_t bssid[ETHER_ADDR_LEN]; 5981 uint16_t reserved; 5982 uint8_t channel; 5983 uint8_t energy; 5984 uint8_t matching_feature; 5985 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5986} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5987 5988/** 5989 * struct iwm_scan_offload_profiles_query - match results query response 5990 * @matched_profiles: bitmap of matched profiles, referencing the 5991 * matches passed in the scan offload request 5992 * @last_scan_age: age of the last offloaded scan 5993 * @n_scans_done: number of offloaded scans done 5994 * @gp2_d0u: GP2 when D0U occurred 5995 * @gp2_invoked: GP2 when scan offload was invoked 5996 * @resume_while_scanning: not used 5997 * @self_recovery: obsolete 5998 * @reserved: reserved 5999 * @matches: array of match information, one for each match 6000 */ 6001struct iwm_scan_offload_profiles_query { 6002 uint32_t matched_profiles; 6003 uint32_t last_scan_age; 6004 uint32_t n_scans_done; 6005 uint32_t gp2_d0u; 6006 uint32_t gp2_invoked; 6007 uint8_t resume_while_scanning; 6008 uint8_t self_recovery; 6009 uint16_t reserved; 6010 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 6011} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 6012 6013/** 6014 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 6015 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6016 * @scanned_channels: number of channels scanned and number of valid elements in 6017 * results array 6018 * @status: one of SCAN_COMP_STATUS_* 6019 * @bt_status: BT on/off status 6020 * @last_channel: last channel that was scanned 6021 * @tsf_low: TSF timer (lower half) in usecs 6022 * @tsf_high: TSF timer (higher half) in usecs 6023 * @results: array of scan results, only "scanned_channels" of them are valid 6024 */ 6025struct iwm_umac_scan_iter_complete_notif { 6026 uint32_t uid; 6027 uint8_t scanned_channels; 6028 uint8_t status; 6029 uint8_t bt_status; 6030 uint8_t last_channel; 6031 uint32_t tsf_low; 6032 uint32_t tsf_high; 6033 struct iwm_scan_results_notif results[]; 6034} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 6035 6036#define IWM_GSCAN_START_CMD 0x0 6037#define IWM_GSCAN_STOP_CMD 0x1 6038#define IWM_GSCAN_SET_HOTLIST_CMD 0x2 6039#define IWM_GSCAN_RESET_HOTLIST_CMD 0x3 6040#define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 6041#define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 6042#define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 6043#define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 6044#define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 6045 6046/* STA API */ 6047 6048/** 6049 * flags for the ADD_STA host command 6050 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 6051 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 6052 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 6053 * @IWM_STA_FLG_PS: set if STA is in Power Save 6054 * @IWM_STA_FLG_INVALID: set if STA is invalid 6055 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 6056 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 6057 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 6058 * @IWM_STA_FLG_PAN: STA is for PAN interface 6059 * @IWM_STA_FLG_CLASS_AUTH: 6060 * @IWM_STA_FLG_CLASS_ASSOC: 6061 * @IWM_STA_FLG_CLASS_MIMO_PROT: 6062 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 6063 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 6064 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 6065 * initialised by driver and can be updated by fw upon reception of 6066 * action frames that can change the channel width. When cleared the fw 6067 * will send all the frames in 20MHz even when FAT channel is requested. 6068 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 6069 * driver and can be updated by fw upon reception of action frames. 6070 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 6071 */ 6072#define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 6073#define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 6074 6075#define IWM_STA_FLG_DISABLE_TX (1 << 4) 6076 6077#define IWM_STA_FLG_PS (1 << 8) 6078#define IWM_STA_FLG_DRAIN_FLOW (1 << 12) 6079#define IWM_STA_FLG_PAN (1 << 13) 6080#define IWM_STA_FLG_CLASS_AUTH (1 << 14) 6081#define IWM_STA_FLG_CLASS_ASSOC (1 << 15) 6082#define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17) 6083 6084#define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19 6085#define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6086#define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6087#define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6088#define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6089#define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6090#define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6091#define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6092#define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6093#define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6094 6095#define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23 6096#define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6097#define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6098#define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6099#define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6100#define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6101 6102#define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26) 6103#define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26) 6104#define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26) 6105#define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26) 6106#define IWM_STA_FLG_FAT_EN_MSK (3 << 26) 6107 6108#define IWM_STA_FLG_MIMO_EN_SISO (0 << 28) 6109#define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 6110#define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 6111#define IWM_STA_FLG_MIMO_EN_MSK (3 << 28) 6112 6113/** 6114 * key flags for the ADD_STA host command 6115 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 6116 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 6117 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 6118 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 6119 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 6120 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 6121 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 6122 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithm value 6123 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 6124 * station info array (1 - n 1X mode) 6125 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 6126 * @IWM_STA_KEY_NOT_VALID: key is invalid 6127 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 6128 * @IWM_STA_KEY_MULTICAST: set for multicast key 6129 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 6130 */ 6131#define IWM_STA_KEY_FLG_NO_ENC (0 << 0) 6132#define IWM_STA_KEY_FLG_WEP (1 << 0) 6133#define IWM_STA_KEY_FLG_CCM (2 << 0) 6134#define IWM_STA_KEY_FLG_TKIP (3 << 0) 6135#define IWM_STA_KEY_FLG_EXT (4 << 0) 6136#define IWM_STA_KEY_FLG_CMAC (6 << 0) 6137#define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 6138#define IWM_STA_KEY_FLG_EN_MSK (7 << 0) 6139#define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 6140#define IWM_STA_KEY_FLG_KEYID_POS 8 6141#define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS) 6142#define IWM_STA_KEY_NOT_VALID (1 << 11) 6143#define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12) 6144#define IWM_STA_KEY_MULTICAST (1 << 14) 6145#define IWM_STA_KEY_MFP (1 << 15) 6146 6147/** 6148 * indicate to the fw what flag are being changed 6149 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 6150 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 6151 * @IWM_STA_MODIFY_TX_RATE: unused 6152 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 6153 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 6154 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 6155 * @IWM_STA_MODIFY_PROT_TH: 6156 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 6157 */ 6158#define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 6159#define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1) 6160#define IWM_STA_MODIFY_TX_RATE (1 << 2) 6161#define IWM_STA_MODIFY_ADD_BA_TID (1 << 3) 6162#define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4) 6163#define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 6164#define IWM_STA_MODIFY_PROT_TH (1 << 6) 6165#define IWM_STA_MODIFY_QUEUES (1 << 7) 6166 6167#define IWM_STA_MODE_MODIFY 1 6168 6169/** 6170 * type of sleep of the station 6171 * @IWM_STA_SLEEP_STATE_AWAKE: 6172 * @IWM_STA_SLEEP_STATE_PS_POLL: 6173 * @IWM_STA_SLEEP_STATE_UAPSD: 6174 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6175 * (last) released frame 6176 */ 6177#define IWM_STA_SLEEP_STATE_AWAKE 0 6178#define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0) 6179#define IWM_STA_SLEEP_STATE_UAPSD (1 << 1) 6180#define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2) 6181 6182/* STA ID and color bits definitions */ 6183#define IWM_STA_ID_SEED (0x0f) 6184#define IWM_STA_ID_POS (0) 6185#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 6186 6187#define IWM_STA_COLOR_SEED (0x7) 6188#define IWM_STA_COLOR_POS (4) 6189#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 6190 6191#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6192 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 6193#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6194 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 6195 6196#define IWM_STA_KEY_MAX_NUM (16) 6197#define IWM_STA_KEY_IDX_INVALID (0xff) 6198#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 6199#define IWM_MAX_GLOBAL_KEYS (4) 6200#define IWM_STA_KEY_LEN_WEP40 (5) 6201#define IWM_STA_KEY_LEN_WEP104 (13) 6202 6203/** 6204 * struct iwm_keyinfo - key information 6205 * @key_flags: type %iwm_sta_key_flag 6206 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6207 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6208 * @key_offset: key offset in the fw's key table 6209 * @key: 16-byte unicast decryption key 6210 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6211 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6212 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6213 */ 6214struct iwm_keyinfo { 6215 uint16_t key_flags; 6216 uint8_t tkip_rx_tsc_byte2; 6217 uint8_t reserved1; 6218 uint16_t tkip_rx_ttak[5]; 6219 uint8_t key_offset; 6220 uint8_t reserved2; 6221 uint8_t key[16]; 6222 uint64_t tx_secur_seq_cnt; 6223 uint64_t hw_tkip_mic_rx_key; 6224 uint64_t hw_tkip_mic_tx_key; 6225} __packed; 6226 6227#define IWM_ADD_STA_STATUS_MASK 0xFF 6228#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 6229#define IWM_ADD_STA_BAID_MASK 0x7F00 6230#define IWM_ADD_STA_BAID_SHIFT 8 6231 6232/** 6233 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 6234 * ( REPLY_ADD_STA = 0x18 ) 6235 * @add_modify: 1: modify existing, 0: add new station 6236 * @awake_acs: 6237 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6238 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 6239 * @mac_id_n_color: the Mac context this station belongs to 6240 * @addr[ETHER_ADDR_LEN]: station's MAC address 6241 * @sta_id: index of station in uCode's station table 6242 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 6243 * alone. 1 - modify, 0 - don't change. 6244 * @station_flags: look at %iwm_sta_flags 6245 * @station_flags_msk: what of %station_flags have changed 6246 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6247 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 6248 * add_immediate_ba_ssn. 6249 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6250 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 6251 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6252 * add_immediate_ba_tid. 6253 * @sleep_tx_count: number of packets to transmit to station even though it is 6254 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6255 * keeps track of STA sleep state. 6256 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 6257 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6258 * mac-addr. 6259 * @beamform_flags: beam forming controls 6260 * @tfd_queue_msk: tfd queues used by this station 6261 * 6262 * The device contains an internal table of per-station information, with info 6263 * on security keys, aggregation parameters, and Tx rates for initial Tx 6264 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 6265 * 6266 * ADD_STA sets up the table entry for one station, either creating a new 6267 * entry, or modifying a pre-existing one. 6268 */ 6269struct iwm_add_sta_cmd_v7 { 6270 uint8_t add_modify; 6271 uint8_t awake_acs; 6272 uint16_t tid_disable_tx; 6273 uint32_t mac_id_n_color; 6274 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6275 uint16_t reserved2; 6276 uint8_t sta_id; 6277 uint8_t modify_mask; 6278 uint16_t reserved3; 6279 uint32_t station_flags; 6280 uint32_t station_flags_msk; 6281 uint8_t add_immediate_ba_tid; 6282 uint8_t remove_immediate_ba_tid; 6283 uint16_t add_immediate_ba_ssn; 6284 uint16_t sleep_tx_count; 6285 uint16_t sleep_state_flags; 6286 uint16_t assoc_id; 6287 uint16_t beamform_flags; 6288 uint32_t tfd_queue_msk; 6289} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6290 6291/** 6292 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table. 6293 * ( REPLY_ADD_STA = 0x18 ) 6294 * @add_modify: see &enum iwl_sta_mode 6295 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 6296 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6297 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 6298 * @mac_id_n_color: the Mac context this station belongs to, 6299 * see &enum iwl_ctxt_id_and_color 6300 * @addr: station's MAC address 6301 * @reserved2: reserved 6302 * @sta_id: index of station in uCode's station table 6303 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 6304 * alone. 1 - modify, 0 - don't change. 6305 * @reserved3: reserved 6306 * @station_flags: look at &enum iwl_sta_flags 6307 * @station_flags_msk: what of %station_flags have changed, 6308 * also &enum iwl_sta_flags 6309 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6310 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 6311 * add_immediate_ba_ssn. 6312 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6313 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 6314 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6315 * add_immediate_ba_tid. 6316 * @sleep_tx_count: number of packets to transmit to station even though it is 6317 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6318 * keeps track of STA sleep state. 6319 * @station_type: type of this station. See &enum iwl_sta_type. 6320 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 6321 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6322 * mac-addr. 6323 * @beamform_flags: beam forming controls 6324 * @tfd_queue_msk: tfd queues used by this station. 6325 * Obsolete for new TX API (9 and above). 6326 * @rx_ba_window: aggregation window size 6327 * @sp_length: the size of the SP in actual number of frames 6328 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 6329 * enabled ACs. 6330 * 6331 * The device contains an internal table of per-station information, with info 6332 * on security keys, aggregation parameters, and Tx rates for initial Tx 6333 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 6334 * 6335 * ADD_STA sets up the table entry for one station, either creating a new 6336 * entry, or modifying a pre-existing one. 6337 */ 6338struct iwm_add_sta_cmd { 6339 uint8_t add_modify; 6340 uint8_t awake_acs; 6341 uint16_t tid_disable_tx; 6342 uint32_t mac_id_n_color; 6343 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6344 uint16_t reserved2; 6345 uint8_t sta_id; 6346 uint8_t modify_mask; 6347 uint16_t reserved3; 6348 uint32_t station_flags; 6349 uint32_t station_flags_msk; 6350 uint8_t add_immediate_ba_tid; 6351 uint8_t remove_immediate_ba_tid; 6352 uint16_t add_immediate_ba_ssn; 6353 uint16_t sleep_tx_count; 6354 uint8_t sleep_state_flags; 6355 uint8_t station_type; 6356 uint16_t assoc_id; 6357 uint16_t beamform_flags; 6358 uint32_t tfd_queue_msk; 6359 uint16_t rx_ba_window; 6360 uint8_t sp_length; 6361 uint8_t uapsd_acs; 6362} __packed; /* ADD_STA_CMD_API_S_VER_10 */ 6363 6364/** 6365 * FW station types 6366 * ( REPLY_ADD_STA = 0x18 ) 6367 * @IWM_STA_LINK: Link station - normal RX and TX traffic. 6368 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 6369 * and probe responses. 6370 * @IWM_STA_MULTICAST: multicast traffic, 6371 * @IWM_STA_TDLS_LINK: TDLS link station 6372 * @IWM_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on). 6373 */ 6374#define IWM_STA_LINK 0 6375#define IWM_STA_GENERAL_PURPOSE 1 6376#define IWM_STA_MULTICAST 2 6377#define IWM_STA_TDLS_LINK 3 6378#define IWM_STA_AUX_ACTIVITY 4 6379 6380/** 6381 * struct iwm_add_sta_key_common - add/modify sta key common part 6382 * ( REPLY_ADD_STA_KEY = 0x17 ) 6383 * @sta_id: index of station in uCode's station table 6384 * @key_offset: key offset in key storage 6385 * @key_flags: IWM_STA_KEY_FLG_* 6386 * @key: key material data 6387 * @rx_secur_seq_cnt: RX security sequence counter for the key 6388 */ 6389struct iwm_add_sta_key_common { 6390 uint8_t sta_id; 6391 uint8_t key_offset; 6392 uint16_t key_flags; 6393 uint8_t key[32]; 6394 uint8_t rx_secur_seq_cnt[16]; 6395} __packed; 6396 6397/** 6398 * struct iwm_add_sta_key_cmd_v1 - add/modify sta key 6399 * @common: see &struct iwm_add_sta_key_common 6400 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6401 * @reserved: reserved 6402 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6403 */ 6404struct iwm_add_sta_key_cmd_v1 { 6405 struct iwm_add_sta_key_common common; 6406 uint8_t tkip_rx_tsc_byte2; 6407 uint8_t reserved; 6408 uint16_t tkip_rx_ttak[5]; 6409} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6410 6411/** 6412 * struct iwm_add_sta_key_cmd - add/modify sta key 6413 * @common: see &struct iwm_add_sta_key_common 6414 * @rx_mic_key: TKIP RX unicast or multicast key 6415 * @tx_mic_key: TKIP TX key 6416 * @transmit_seq_cnt: TSC, transmit packet number 6417 */ 6418struct iwm_add_sta_key_cmd { 6419 struct iwm_add_sta_key_common common; 6420 uint64_t rx_mic_key; 6421 uint64_t tx_mic_key; 6422 uint64_t transmit_seq_cnt; 6423} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 6424 6425/** 6426 * status in the response to ADD_STA command 6427 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6428 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6429 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6430 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6431 * that doesn't exist. 6432 */ 6433#define IWM_ADD_STA_SUCCESS 0x1 6434#define IWM_ADD_STA_STATIONS_OVERLOAD 0x2 6435#define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 6436#define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 6437 6438/** 6439 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table 6440 * ( IWM_REMOVE_STA = 0x19 ) 6441 * @sta_id: the station id of the station to be removed 6442 */ 6443struct iwm_rm_sta_cmd { 6444 uint8_t sta_id; 6445 uint8_t reserved[3]; 6446} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6447 6448/** 6449 * struct iwm_mgmt_mcast_key_cmd 6450 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6451 * @ctrl_flags: %iwm_sta_key_flag 6452 * @IGTK: 6453 * @K1: IGTK master key 6454 * @K2: IGTK sub key 6455 * @sta_id: station ID that support IGTK 6456 * @key_id: 6457 * @receive_seq_cnt: initial RSC/PN needed for replay check 6458 */ 6459struct iwm_mgmt_mcast_key_cmd { 6460 uint32_t ctrl_flags; 6461 uint8_t IGTK[16]; 6462 uint8_t K1[16]; 6463 uint8_t K2[16]; 6464 uint32_t key_id; 6465 uint32_t sta_id; 6466 uint64_t receive_seq_cnt; 6467} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6468 6469struct iwm_wep_key { 6470 uint8_t key_index; 6471 uint8_t key_offset; 6472 uint16_t reserved1; 6473 uint8_t key_size; 6474 uint8_t reserved2[3]; 6475 uint8_t key[16]; 6476} __packed; 6477 6478struct iwm_wep_key_cmd { 6479 uint32_t mac_id_n_color; 6480 uint8_t num_keys; 6481 uint8_t decryption_type; 6482 uint8_t flags; 6483 uint8_t reserved; 6484 struct iwm_wep_key wep_key[0]; 6485} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6486 6487/* 6488 * BT coex 6489 */ 6490 6491#define IWM_BT_COEX_DISABLE 0x0 6492#define IWM_BT_COEX_NW 0x1 6493#define IWM_BT_COEX_BT 0x2 6494#define IWM_BT_COEX_WIFI 0x3 6495/* BT_COEX_MODES_E */ 6496 6497#define IWM_BT_COEX_MPLUT_ENABLED (1 << 0) 6498#define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 6499#define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 6500#define IWM_BT_COEX_CORUN_ENABLED (1 << 3) 6501#define IWM_BT_COEX_HIGH_BAND_RET (1 << 4) 6502/* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6503 6504/** 6505 * struct iwm_bt_coex_cmd - bt coex configuration command 6506 * @mode: enum %iwm_bt_coex_mode 6507 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6508 * 6509 * The structure is used for the BT_COEX command. 6510 */ 6511struct iwm_bt_coex_cmd { 6512 uint32_t mode; 6513 uint32_t enabled_modules; 6514} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6515 6516 6517/* 6518 * Location Aware Regulatory (LAR) API - MCC updates 6519 */ 6520 6521/** 6522 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6523 * regulatory profile according to the given MCC (Mobile Country Code). 6524 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6525 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6526 * MCC in the cmd response will be the relevant MCC in the NVM. 6527 * @mcc: given mobile country code 6528 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6529 * @reserved: reserved for alignment 6530 */ 6531struct iwm_mcc_update_cmd_v1 { 6532 uint16_t mcc; 6533 uint8_t source_id; 6534 uint8_t reserved; 6535} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6536 6537/** 6538 * struct iwm_mcc_update_cmd - Request the device to update geographic 6539 * regulatory profile according to the given MCC (Mobile Country Code). 6540 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6541 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6542 * MCC in the cmd response will be the relevant MCC in the NVM. 6543 * @mcc: given mobile country code 6544 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6545 * @reserved: reserved for alignment 6546 * @key: integrity key for MCC API OEM testing 6547 * @reserved2: reserved 6548 */ 6549struct iwm_mcc_update_cmd { 6550 uint16_t mcc; 6551 uint8_t source_id; 6552 uint8_t reserved; 6553 uint32_t key; 6554 uint32_t reserved2[5]; 6555} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6556 6557/** 6558 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6559 * Contains the new channel control profile map, if changed, and the new MCC 6560 * (mobile country code). 6561 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6562 * @status: see &enum iwm_mcc_update_status 6563 * @mcc: the new applied MCC 6564 * @cap: capabilities for all channels which matches the MCC 6565 * @source_id: the MCC source, see iwm_mcc_source 6566 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6567 * channels, depending on platform) 6568 * @channels: channel control data map, DWORD for each channel. Only the first 6569 * 16bits are used. 6570 */ 6571struct iwm_mcc_update_resp_v1 { 6572 uint32_t status; 6573 uint16_t mcc; 6574 uint8_t cap; 6575 uint8_t source_id; 6576 uint32_t n_channels; 6577 uint32_t channels[0]; 6578} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6579 6580/** 6581 * iwm_mcc_update_resp_v2 - response to MCC_UPDATE_CMD. 6582 * Contains the new channel control profile map, if changed, and the new MCC 6583 * (mobile country code). 6584 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6585 * @status: see &enum iwm_mcc_update_status 6586 * @mcc: the new applied MCC 6587 * @cap: capabilities for all channels which matches the MCC 6588 * @source_id: the MCC source, see iwm_mcc_source 6589 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6590 * @reserved: reserved. 6591 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6592 * channels, depending on platform) 6593 * @channels: channel control data map, DWORD for each channel. Only the first 6594 * 16bits are used. 6595 */ 6596struct iwm_mcc_update_resp_v2 { 6597 uint32_t status; 6598 uint16_t mcc; 6599 uint8_t cap; 6600 uint8_t source_id; 6601 uint16_t time; 6602 uint16_t reserved; 6603 uint32_t n_channels; 6604 uint32_t channels[0]; 6605} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6606 6607#define IWM_GEO_NO_INFO 0 6608#define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 6609 6610/** 6611 * iwm_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 6612 * Contains the new channel control profile map, if changed, and the new MCC 6613 * (mobile country code). 6614 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6615 * @status: see &enum iwm_mcc_update_status 6616 * @mcc: the new applied MCC 6617 * @cap: capabilities for all channels which matches the MCC 6618 * @source_id: the MCC source, see IWM_MCC_SOURCE_* 6619 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6620 * @geo_info: geographic specific profile information 6621 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6622 * channels, depending on platform) 6623 * @channels: channel control data map, DWORD for each channel. Only the first 6624 * 16bits are used. 6625 */ 6626struct iwm_mcc_update_resp_v3 { 6627 uint32_t status; 6628 uint16_t mcc; 6629 uint8_t cap; 6630 uint8_t source_id; 6631 uint16_t time; 6632 uint16_t geo_info; 6633 uint32_t n_channels; 6634 uint32_t channels[0]; 6635} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 6636 6637/** 6638 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6639 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6640 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6641 * the cellular and connectivity cores that gets updates of the mcc, and 6642 * notifies the ucode directly of any mcc change. 6643 * The ucode requests the driver to request the device to update geographic 6644 * regulatory profile according to the given MCC (Mobile Country Code). 6645 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6646 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6647 * MCC in the cmd response will be the relevant MCC in the NVM. 6648 * @mcc: given mobile country code 6649 * @source_id: identity of the change originator, see iwm_mcc_source 6650 * @reserved1: reserved for alignment 6651 */ 6652struct iwm_mcc_chub_notif { 6653 uint16_t mcc; 6654 uint8_t source_id; 6655 uint8_t reserved1; 6656} __packed; /* LAR_MCC_NOTIFY_S */ 6657 6658#define IWM_MCC_RESP_NEW_CHAN_PROFILE 0 6659#define IWM_MCC_RESP_SAME_CHAN_PROFILE 1 6660#define IWM_MCC_RESP_INVALID 2 6661#define IWM_MCC_RESP_NVM_DISABLED 3 6662#define IWM_MCC_RESP_ILLEGAL 4 6663#define IWM_MCC_RESP_LOW_PRIORITY 5 6664#define IWM_MCC_RESP_TEST_MODE_ACTIVE 6 6665#define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7 6666#define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8 6667 6668#define IWM_MCC_SOURCE_OLD_FW 0 6669#define IWM_MCC_SOURCE_ME 1 6670#define IWM_MCC_SOURCE_BIOS 2 6671#define IWM_MCC_SOURCE_3G_LTE_HOST 3 6672#define IWM_MCC_SOURCE_3G_LTE_DEVICE 4 6673#define IWM_MCC_SOURCE_WIFI 5 6674#define IWM_MCC_SOURCE_RESERVED 6 6675#define IWM_MCC_SOURCE_DEFAULT 7 6676#define IWM_MCC_SOURCE_UNINITIALIZED 8 6677#define IWM_MCC_SOURCE_MCC_API 9 6678#define IWM_MCC_SOURCE_GET_CURRENT 0x10 6679#define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 6680 6681/* 6682 * Some cherry-picked definitions 6683 */ 6684 6685#define IWM_FRAME_LIMIT 64 6686 6687/* 6688 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6689 * As the firmware is slowly running out of command IDs and grouping of 6690 * commands is desirable anyway, the firmware is extending the command 6691 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6692 * former flags field, since that's always 0 on commands and thus can 6693 * be easily used to distinguish between the two). 6694 * 6695 * These functions retrieve specific information from the id field in 6696 * the iwm_host_cmd struct which contains the command id, the group id, 6697 * and the version of the command. 6698*/ 6699static inline uint8_t 6700iwm_cmd_opcode(uint32_t cmdid) 6701{ 6702 return cmdid & 0xff; 6703} 6704 6705static inline uint8_t 6706iwm_cmd_groupid(uint32_t cmdid) 6707{ 6708 return ((cmdid & 0Xff00) >> 8); 6709} 6710 6711static inline uint8_t 6712iwm_cmd_version(uint32_t cmdid) 6713{ 6714 return ((cmdid & 0xff0000) >> 16); 6715} 6716 6717static inline uint32_t 6718iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6719{ 6720 return opcode + (groupid << 8) + (version << 16); 6721} 6722 6723/* make uint16_t wide id out of uint8_t group and opcode */ 6724#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6725 6726struct iwm_cmd_header { 6727 uint8_t code; 6728 uint8_t flags; 6729 uint8_t idx; 6730 uint8_t qid; 6731} __packed; 6732 6733struct iwm_cmd_header_wide { 6734 uint8_t opcode; 6735 uint8_t group_id; 6736 uint8_t idx; 6737 uint8_t qid; 6738 uint16_t length; 6739 uint8_t reserved; 6740 uint8_t version; 6741} __packed; 6742 6743#define IWM_POWER_SCHEME_CAM 1 6744#define IWM_POWER_SCHEME_BPS 2 6745#define IWM_POWER_SCHEME_LP 3 6746 6747#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6748#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6749#define IWM_CMD_FAILED_MSK 0x40 6750 6751/** 6752 * struct iwm_device_cmd 6753 * 6754 * For allocation of the command and tx queues, this establishes the overall 6755 * size of the largest command we send to uCode, except for commands that 6756 * aren't fully copied and use other TFD space. 6757 */ 6758struct iwm_device_cmd { 6759 union { 6760 struct { 6761 struct iwm_cmd_header hdr; 6762 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6763 }; 6764 struct { 6765 struct iwm_cmd_header_wide hdr_wide; 6766 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6767 sizeof(struct iwm_cmd_header_wide) + 6768 sizeof(struct iwm_cmd_header)]; 6769 }; 6770 }; 6771} __packed; 6772 6773struct iwm_rx_packet { 6774 /* 6775 * The first 4 bytes of the RX frame header contain both the RX frame 6776 * size and some flags. 6777 * Bit fields: 6778 * 31: flag flush RB request 6779 * 30: flag ignore TC (terminal counter) request 6780 * 29: flag fast IRQ request 6781 * 28-26: Reserved 6782 * 25: Offload enabled 6783 * 24: RPF enabled 6784 * 23: RSS enabled 6785 * 22: Checksum enabled 6786 * 21-16: RX queue 6787 * 15-14: Reserved 6788 * 13-00: RX frame size 6789 */ 6790 uint32_t len_n_flags; 6791 struct iwm_cmd_header hdr; 6792 uint8_t data[]; 6793} __packed; 6794 6795#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6796#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6797#define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6798#define IWM_FH_RSCSR_RPA_EN (1 << 25) 6799#define IWM_FH_RSCSR_RADA_EN (1 << 26) 6800#define IWM_FH_RSCSR_RXQ_POS 16 6801#define IWM_FH_RSCSR_RXQ_MASK 0x3F0000 6802 6803static uint32_t 6804iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6805{ 6806 6807 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6808} 6809 6810static uint32_t 6811iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6812{ 6813 6814 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6815} 6816 6817 6818#define IWM_MIN_DBM -100 6819#define IWM_MAX_DBM -33 /* realistic guess */ 6820 6821#define IWM_READ(sc, reg) \ 6822 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6823 6824#define IWM_WRITE(sc, reg, val) \ 6825 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6826 6827#define IWM_WRITE_1(sc, reg, val) \ 6828 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6829 6830#define IWM_SETBITS(sc, reg, mask) \ 6831 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6832 6833#define IWM_CLRBITS(sc, reg, mask) \ 6834 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6835 6836#define IWM_BARRIER_WRITE(sc) \ 6837 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6838 BUS_SPACE_BARRIER_WRITE) 6839 6840#define IWM_BARRIER_READ_WRITE(sc) \ 6841 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6842 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6843