1/* $OpenBSD: if_iwxreg.h,v 1.52 2023/10/06 15:15:41 stsp Exp $ */ 2 3/*- 4 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 5 * which were used as the reference documentation for this implementation. 6 * 7 ****************************************************************************** 8 * 9 * This file is provided under a dual BSD/GPLv2 license. When using or 10 * redistributing this file, you may do so under either license. 11 * 12 * GPL LICENSE SUMMARY 13 * 14 * Copyright(c) 2017 Intel Deutschland GmbH 15 * Copyright(c) 2018 - 2019 Intel Corporation 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of version 2 of the GNU General Public License as 19 * published by the Free Software Foundation. 20 * 21 * This program is distributed in the hope that it will be useful, but 22 * WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * General Public License for more details. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2017 Intel Deutschland GmbH 29 * Copyright(c) 2018 - 2019 Intel Corporation 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 ***************************************************************************** 59 */ 60 61 62/* maximum number of DRAM map entries supported by FW */ 63#define IWX_MAX_DRAM_ENTRY 64 64#define IWX_CSR_CTXT_INFO_BA 0x40 65 66/** 67 * enum iwx_context_info_flags - Context information control flags 68 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 69 * the init done for driver command that configures several system modes 70 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug 71 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump 72 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size 73 * exponent, the actual size is 2**value, valid sizes are 8-2048. 74 * The value is four bits long. Maximum valid exponent is 12 75 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 76 * default is short format - not supported by the driver) 77 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position 78 * (values are IWX_CTXT_INFO_RB_SIZE_*K) 79 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 80 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 81 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 82 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 83 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 84 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 85 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 86 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 87 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 88 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 89 */ 90enum iwx_context_info_flags { 91 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0), 92 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1), 93 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2), 94 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4, 95 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8), 96 IWX_CTXT_INFO_RB_SIZE_POS = 9, 97 IWX_CTXT_INFO_RB_SIZE_1K = 0x1, 98 IWX_CTXT_INFO_RB_SIZE_2K = 0x2, 99 IWX_CTXT_INFO_RB_SIZE_4K = 0x4, 100 IWX_CTXT_INFO_RB_SIZE_8K = 0x8, 101 IWX_CTXT_INFO_RB_SIZE_12K = 0x9, 102 IWX_CTXT_INFO_RB_SIZE_16K = 0xa, 103 IWX_CTXT_INFO_RB_SIZE_20K = 0xb, 104 IWX_CTXT_INFO_RB_SIZE_24K = 0xc, 105 IWX_CTXT_INFO_RB_SIZE_28K = 0xd, 106 IWX_CTXT_INFO_RB_SIZE_32K = 0xe, 107}; 108 109/* 110 * struct iwx_context_info_version - version structure 111 * @mac_id: SKU and revision id 112 * @version: context information version id 113 * @size: the size of the context information in DWs 114 */ 115struct iwx_context_info_version { 116 uint16_t mac_id; 117 uint16_t version; 118 uint16_t size; 119 uint16_t reserved; 120} __packed; 121 122/* 123 * struct iwx_context_info_control - version structure 124 * @control_flags: context information flags see &enum iwx_context_info_flags 125 */ 126struct iwx_context_info_control { 127 uint32_t control_flags; 128 uint32_t reserved; 129} __packed; 130 131/* 132 * struct iwx_context_info_dram - images DRAM map 133 * each entry in the map represents a DRAM chunk of up to 32 KB 134 * @umac_img: UMAC image DRAM map 135 * @lmac_img: LMAC image DRAM map 136 * @virtual_img: paged image DRAM map 137 */ 138struct iwx_context_info_dram { 139 uint64_t umac_img[IWX_MAX_DRAM_ENTRY]; 140 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY]; 141 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY]; 142} __packed; 143 144/* 145 * struct iwx_context_info_rbd_cfg - RBDs configuration 146 * @free_rbd_addr: default queue free RB CB base address 147 * @used_rbd_addr: default queue used RB CB base address 148 * @status_wr_ptr: default queue used RB status write pointer 149 */ 150struct iwx_context_info_rbd_cfg { 151 uint64_t free_rbd_addr; 152 uint64_t used_rbd_addr; 153 uint64_t status_wr_ptr; 154} __packed; 155 156/* 157 * struct iwx_context_info_hcmd_cfg - command queue configuration 158 * @cmd_queue_addr: address of command queue 159 * @cmd_queue_size: number of entries 160 */ 161struct iwx_context_info_hcmd_cfg { 162 uint64_t cmd_queue_addr; 163 uint8_t cmd_queue_size; 164 uint8_t reserved[7]; 165} __packed; 166 167/* 168 * struct iwx_context_info_dump_cfg - Core Dump configuration 169 * @core_dump_addr: core dump (debug DRAM address) start address 170 * @core_dump_size: size, in DWs 171 */ 172struct iwx_context_info_dump_cfg { 173 uint64_t core_dump_addr; 174 uint32_t core_dump_size; 175 uint32_t reserved; 176} __packed; 177 178/* 179 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration 180 * @platform_nvm_addr: Platform NVM data start address 181 * @platform_nvm_size: size in DWs 182 */ 183struct iwx_context_info_pnvm_cfg { 184 uint64_t platform_nvm_addr; 185 uint32_t platform_nvm_size; 186 uint32_t reserved; 187} __packed; 188 189/* 190 * struct iwx_context_info_early_dbg_cfg - early debug configuration for 191 * dumping DRAM addresses 192 * @early_debug_addr: early debug start address 193 * @early_debug_size: size in DWs 194 */ 195struct iwx_context_info_early_dbg_cfg { 196 uint64_t early_debug_addr; 197 uint32_t early_debug_size; 198 uint32_t reserved; 199} __packed; 200 201/* 202 * struct iwx_context_info - device INIT configuration 203 * @version: version information of context info and HW 204 * @control: control flags of FH configurations 205 * @rbd_cfg: default RX queue configuration 206 * @hcmd_cfg: command queue configuration 207 * @dump_cfg: core dump data 208 * @edbg_cfg: early debug configuration 209 * @pnvm_cfg: platform nvm configuration 210 * @dram: firmware image addresses in DRAM 211 */ 212struct iwx_context_info { 213 struct iwx_context_info_version version; 214 struct iwx_context_info_control control; 215 uint64_t reserved0; 216 struct iwx_context_info_rbd_cfg rbd_cfg; 217 struct iwx_context_info_hcmd_cfg hcmd_cfg; 218 uint32_t reserved1[4]; 219 struct iwx_context_info_dump_cfg dump_cfg; 220 struct iwx_context_info_early_dbg_cfg edbg_cfg; 221 struct iwx_context_info_pnvm_cfg pnvm_cfg; 222 uint32_t reserved2[16]; 223 struct iwx_context_info_dram dram; 224 uint32_t reserved3[16]; 225} __packed; 226 227 228/* 229 * Context info definitions for AX210 devices. 230 */ 231 232#define IWX_CSR_CTXT_INFO_BOOT_CTRL 0x0 233#define IWX_CSR_CTXT_INFO_ADDR 0x118 234#define IWX_CSR_IML_DATA_ADDR 0x120 235#define IWX_CSR_IML_SIZE_ADDR 0x128 236#define IWX_CSR_IML_RESP_ADDR 0x12c 237 238/* Set bit for enabling automatic function boot */ 239#define IWX_CSR_AUTO_FUNC_BOOT_ENA (1 << 1) 240/* Set bit for initiating function boot */ 241#define IWX_CSR_AUTO_FUNC_INIT (1 << 7) 242 243/** 244 * iwx_prph_scratch_mtr_format - tfd size configuration 245 * @IWX_PRPH_MTR_FORMAT_16B: 16 bit tfd 246 * @IWX_PRPH_MTR_FORMAT_32B: 32 bit tfd 247 * @IWX_PRPH_MTR_FORMAT_64B: 64 bit tfd 248 * @IWX_PRPH_MTR_FORMAT_256B: 256 bit tfd 249 */ 250#define IWX_PRPH_MTR_FORMAT_16B 0x0 251#define IWX_PRPH_MTR_FORMAT_32B 0x40000 252#define IWX_PRPH_MTR_FORMAT_64B 0x80000 253#define IWX_PRPH_MTR_FORMAT_256B 0xC0000 254 255/** 256 * iwx_prph_scratch_flags - PRPH scratch control flags 257 * @IWX_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 258 * @IWX_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 259 * @IWX_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 260 * in hwm config. 261 * @IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 262 * @IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 263 * multicomm. 264 * @IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 265 * @IWX_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 266 * @IWX_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 267 * completion descriptor, 1 for responses (legacy) 268 * @IWX_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 269 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 270 * 3: 256 bit. 271 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 272 * by older firmware versions, so set IWX_PRPH_SCRATCH_RB_SIZE_4K 273 * appropriately; use the below values for this. 274 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 275 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 276 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 277 */ 278#define IWX_PRPH_SCRATCH_IMR_DEBUG_EN (1 << 1) 279#define IWX_PRPH_SCRATCH_EARLY_DEBUG_EN (1 << 4) 280#define IWX_PRPH_SCRATCH_EDBG_DEST_DRAM (1 << 8) 281#define IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL (1 << 9) 282#define IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER (1 << 10) 283#define IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF (1 << 11) 284#define IWX_PRPH_SCRATCH_RB_SIZE_4K (1 << 16) 285#define IWX_PRPH_SCRATCH_MTR_MODE (1 << 17) 286#define IWX_PRPH_SCRATCH_MTR_FORMAT ((1 << 18) | (1 << 19)) 287#define IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK (0xf << 20) 288#define IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K (8 << 20) 289#define IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K (9 << 20) 290#define IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K (10 << 20) 291 292/* 293 * struct iwx_prph_scratch_version - version structure 294 * @mac_id: SKU and revision id 295 * @version: prph scratch information version id 296 * @size: the size of the context information in DWs 297 * @reserved: reserved 298 */ 299struct iwx_prph_scratch_version { 300 uint16_t mac_id; 301 uint16_t version; 302 uint16_t size; 303 uint16_t reserved; 304} __packed; /* PERIPH_SCRATCH_VERSION_S */ 305 306/* 307 * struct iwx_prph_scratch_control - control structure 308 * @control_flags: context information flags see &iwx_prph_scratch_flags 309 * @reserved: reserved 310 */ 311struct iwx_prph_scratch_control { 312 uint32_t control_flags; 313 uint32_t reserved; 314} __packed; /* PERIPH_SCRATCH_CONTROL_S */ 315 316/* 317 * struct iwx_prph_scratch_pnvm_cfg - ror config 318 * @pnvm_base_addr: PNVM start address 319 * @pnvm_size: PNVM size in DWs 320 * @reserved: reserved 321 */ 322struct iwx_prph_scratch_pnvm_cfg { 323 uint64_t pnvm_base_addr; 324 uint32_t pnvm_size; 325 uint32_t reserved; 326} __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 327 328struct iwx_pnvm_section { 329 uint32_t offset; 330 const uint8_t data[]; 331} __packed; 332 333/* 334 * struct iwx_prph_scratch_hwm_cfg - hwm config 335 * @hwm_base_addr: hwm start address 336 * @hwm_size: hwm size in DWs 337 * @debug_token_config: debug preset 338 */ 339struct iwx_prph_scratch_hwm_cfg { 340 uint64_t hwm_base_addr; 341 uint32_t hwm_size; 342 uint32_t debug_token_config; 343} __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 344 345/* 346 * struct iwx_prph_scratch_rbd_cfg - RBDs configuration 347 * @free_rbd_addr: default queue free RB CB base address 348 * @reserved: reserved 349 */ 350struct iwx_prph_scratch_rbd_cfg { 351 uint64_t free_rbd_addr; 352 uint32_t reserved; 353} __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 354 355/* 356 * struct iwx_prph_scratch_uefi_cfg - prph scratch reduce power table 357 * @base_addr: reduce power table address 358 * @size: table size in dwords 359 */ 360struct iwx_prph_scratch_uefi_cfg { 361 uint64_t base_addr; 362 uint32_t size; 363 uint32_t reserved; 364} __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 365 366/* 367 * struct iwx_prph_scratch_ctrl_cfg - prph scratch ctrl and config 368 * @version: version information of context info and HW 369 * @control: control flags of FH configurations 370 * @pnvm_cfg: ror configuration 371 * @hwm_cfg: hwm configuration 372 * @rbd_cfg: default RX queue configuration 373 */ 374struct iwx_prph_scratch_ctrl_cfg { 375 struct iwx_prph_scratch_version version; 376 struct iwx_prph_scratch_control control; 377 struct iwx_prph_scratch_pnvm_cfg pnvm_cfg; 378 struct iwx_prph_scratch_hwm_cfg hwm_cfg; 379 struct iwx_prph_scratch_rbd_cfg rbd_cfg; 380 struct iwx_prph_scratch_uefi_cfg reduce_power_cfg; 381} __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 382 383/* 384 * struct iwx_prph_scratch - peripheral scratch mapping 385 * @ctrl_cfg: control and configuration of prph scratch 386 * @dram: firmware images addresses in DRAM 387 * @reserved: reserved 388 */ 389struct iwx_prph_scratch { 390 struct iwx_prph_scratch_ctrl_cfg ctrl_cfg; 391 uint32_t reserved[12]; 392 struct iwx_context_info_dram dram; 393} __packed; /* PERIPH_SCRATCH_S */ 394 395/* 396 * struct iwx_prph_info - peripheral information 397 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 398 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 399 * @sleep_notif: indicates the peripheral sleep status 400 * @reserved: reserved 401 */ 402struct iwx_prph_info { 403 uint32_t boot_stage_mirror; 404 uint32_t ipc_status_mirror; 405 uint32_t sleep_notif; 406 uint32_t reserved; 407} __packed; /* PERIPH_INFO_S */ 408 409/* 410 * struct iwx_context_info_gen3 - device INIT configuration 411 * @version: version of the context information 412 * @size: size of context information in DWs 413 * @config: context in which the peripheral would execute - a subset of 414 * capability csr register published by the peripheral 415 * @prph_info_base_addr: the peripheral information structure start address 416 * @cr_head_idx_arr_base_addr: the completion ring head index array 417 * start address 418 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 419 * start address 420 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 421 * start address 422 * @tr_head_idx_arr_base_addr: the transfer ring head index array 423 * start address 424 * @cr_idx_arr_size: number of entries in the completion ring index array 425 * @tr_idx_arr_size: number of entries in the transfer ring index array 426 * @mtr_base_addr: the message transfer ring start address 427 * @mcr_base_addr: the message completion ring start address 428 * @mtr_size: number of entries which the message transfer ring can hold 429 * @mcr_size: number of entries which the message completion ring can hold 430 * @mtr_doorbell_vec: the doorbell vector associated with the message 431 * transfer ring 432 * @mcr_doorbell_vec: the doorbell vector associated with the message 433 * completion ring 434 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 435 * completing a transfer descriptor in the message transfer ring 436 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 437 * completing a completion descriptor in the message completion ring 438 * @mtr_opt_header_size: the size of the optional header in the transfer 439 * descriptor associated with the message transfer ring in DWs 440 * @mtr_opt_footer_size: the size of the optional footer in the transfer 441 * descriptor associated with the message transfer ring in DWs 442 * @mcr_opt_header_size: the size of the optional header in the completion 443 * descriptor associated with the message completion ring in DWs 444 * @mcr_opt_footer_size: the size of the optional footer in the completion 445 * descriptor associated with the message completion ring in DWs 446 * @msg_rings_ctrl_flags: message rings control flags 447 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 448 * after updating the Peripheral Information structure 449 * @prph_scratch_base_addr: the peripheral scratch structure start address 450 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 451 * @reserved: reserved 452 */ 453struct iwx_context_info_gen3 { 454 uint16_t version; 455 uint16_t size; 456 uint32_t config; 457 uint64_t prph_info_base_addr; 458 uint64_t cr_head_idx_arr_base_addr; 459 uint64_t tr_tail_idx_arr_base_addr; 460 uint64_t cr_tail_idx_arr_base_addr; 461 uint64_t tr_head_idx_arr_base_addr; 462 uint16_t cr_idx_arr_size; 463 uint16_t tr_idx_arr_size; 464 uint64_t mtr_base_addr; 465 uint64_t mcr_base_addr; 466 uint16_t mtr_size; 467 uint16_t mcr_size; 468 uint16_t mtr_doorbell_vec; 469 uint16_t mcr_doorbell_vec; 470 uint16_t mtr_msi_vec; 471 uint16_t mcr_msi_vec; 472 uint8_t mtr_opt_header_size; 473 uint8_t mtr_opt_footer_size; 474 uint8_t mcr_opt_header_size; 475 uint8_t mcr_opt_footer_size; 476 uint16_t msg_rings_ctrl_flags; 477 uint16_t prph_info_msi_vec; 478 uint64_t prph_scratch_base_addr; 479 uint32_t prph_scratch_size; 480 uint32_t reserved; 481} __packed; /* IPC_CONTEXT_INFO_S */ 482 483#define IWX_MGMT_TID 15 484 485#define IWX_MQ_RX_TABLE_SIZE 512 486 487/* cb size is the exponent */ 488#define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1)) 489 490/* 491 * CSR (control and status registers) 492 * 493 * CSR registers are mapped directly into PCI bus space, and are accessible 494 * whenever platform supplies power to device, even when device is in 495 * low power states due to driver-invoked device resets 496 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 497 * 498 * Use iwl_write32() and iwl_read32() family to access these registers; 499 * these provide simple PCI bus access, without waking up the MAC. 500 * Do not use iwl_write_direct32() family for these registers; 501 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 502 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 503 * the CSR registers. 504 * 505 * NOTE: Device does need to be awake in order to read this memory 506 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers 507 */ 508#define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 509#define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 510#define IWX_CSR_INT (0x008) /* host interrupt status/ack */ 511#define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */ 512#define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 513#define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */ 514#define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 515#define IWX_CSR_GP_CNTRL (0x024) 516 517/* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 518#define IWX_CSR_INT_PERIODIC_REG (0x005) 519 520/* 521 * Hardware revision info 522 * Bit fields: 523 * 31-16: Reserved 524 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions 525 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 526 * 1-0: "Dash" (-) value, as in A-1, etc. 527 */ 528#define IWX_CSR_HW_REV (0x028) 529 530/* 531 * RF ID revision info 532 * Bit fields: 533 * 31:24: Reserved (set to 0x0) 534 * 23:12: Type 535 * 11:8: Step (A - 0x0, B - 0x1, etc) 536 * 7:4: Dash 537 * 3:0: Flavor 538 */ 539#define IWX_CSR_HW_RF_ID (0x09c) 540 541 542#define IWX_CSR_GIO_REG (0x03C) 543 544/* 545 * UCODE-DRIVER GP (general purpose) mailbox registers. 546 * SET/CLR registers set/clear bit(s) if "1" is written. 547 */ 548#define IWX_CSR_UCODE_DRV_GP1 (0x054) 549#define IWX_CSR_UCODE_DRV_GP1_SET (0x058) 550#define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c) 551#define IWX_CSR_UCODE_DRV_GP2 (0x060) 552 553#define IWX_CSR_MBOX_SET_REG (0x088) 554#define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20 555 556#define IWX_CSR_DRAM_INT_TBL_REG (0x0A0) 557#define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 558 559/* LTR control */ 560#define IWX_CSR_LTR_LONG_VAL_AD (0x0d4) 561#define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 562#define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_MASK 0x1c000000 563#define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_SHIFT 24 564#define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_MASK 0x03ff0000 565#define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_SHIFT 16 566#define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 567#define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_MASK 0x00001c00 568#define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_SHIFT 8 569#define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff 570#define IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 571 572/* GIO Chicken Bits (PCI Express bus link power management) */ 573#define IWX_CSR_GIO_CHICKEN_BITS (0x100) 574 575#define IWX_CSR_DBG_HPET_MEM_REG (0x240) 576#define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 577 578/* Bits for IWX_CSR_HW_IF_CONFIG_REG */ 579#define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 580#define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 581#define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 582#define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 583#define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 584#define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 585#define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 586#define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 587 588#define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 589#define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 590#define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 591#define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 592#define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 593#define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 594 595#define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 596#define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 597#define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 598#define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 599#define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 600#define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 601#define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 602 603#define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 604#define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 605 606/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 607 * acknowledged (reset) by host writing "1" to flagged bits. */ 608#define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 609#define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 610#define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 611#define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 612#define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 613#define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 614#define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 615#define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 616#define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 617#define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 618#define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 619 620#define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \ 621 IWX_CSR_INT_BIT_HW_ERR | \ 622 IWX_CSR_INT_BIT_FH_TX | \ 623 IWX_CSR_INT_BIT_SW_ERR | \ 624 IWX_CSR_INT_BIT_RF_KILL | \ 625 IWX_CSR_INT_BIT_SW_RX | \ 626 IWX_CSR_INT_BIT_WAKEUP | \ 627 IWX_CSR_INT_BIT_ALIVE | \ 628 IWX_CSR_INT_BIT_RX_PERIODIC) 629 630/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 631#define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 632#define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 633#define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 634#define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 635#define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 636#define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 637 638#define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \ 639 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \ 640 IWX_CSR_FH_INT_BIT_RX_CHNL0) 641 642#define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \ 643 IWX_CSR_FH_INT_BIT_TX_CHNL0) 644 645/** 646 * struct iwx_rx_transfer_desc - transfer descriptor AX210 647 * @addr: ptr to free buffer start address 648 * @rbid: unique tag of the buffer 649 * @reserved: reserved 650 */ 651struct iwx_rx_transfer_desc { 652 uint16_t rbid; 653 uint16_t reserved[3]; 654 uint64_t addr; 655}; 656 657#define IWX_RX_CD_FLAGS_FRAGMENTED (1 << 0) 658 659/** 660 * struct iwx_rx_completion_desc - completion descriptor AX210 661 * @reserved1: reserved 662 * @rbid: unique tag of the received buffer 663 * @flags: flags (0: fragmented, all others: reserved) 664 * @reserved2: reserved 665 */ 666struct iwx_rx_completion_desc { 667 uint32_t reserved1; 668 uint16_t rbid; 669 uint8_t flags; 670 uint8_t reserved2[25]; 671}; 672 673/* RESET */ 674#define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 675#define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 676#define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 677#define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 678#define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 679#define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 680 681/* 682 * GP (general purpose) CONTROL REGISTER 683 * Bit fields: 684 * 27: HW_RF_KILL_SW 685 * Indicates state of (platform's) hardware RF-Kill switch 686 * 26-24: POWER_SAVE_TYPE 687 * Indicates current power-saving mode: 688 * 000 -- No power saving 689 * 001 -- MAC power-down 690 * 010 -- PHY (radio) power-down 691 * 011 -- Error 692 * 9-6: SYS_CONFIG 693 * Indicates current system configuration, reflecting pins on chip 694 * as forced high/low by device circuit board. 695 * 4: GOING_TO_SLEEP 696 * Indicates MAC is entering a power-saving sleep power-down. 697 * Not a good time to access device-internal resources. 698 * 3: MAC_ACCESS_REQ 699 * Host sets this to request and maintain MAC wakeup, to allow host 700 * access to device-internal resources. Host must wait for 701 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 702 * device registers. 703 * 2: INIT_DONE 704 * Host sets this to put device into fully operational D0 power mode. 705 * Host resets this after SW_RESET to put device into low power mode. 706 * 0: MAC_CLOCK_READY 707 * Indicates MAC (ucode processor, etc.) is powered up and can run. 708 * Internal resources are accessible. 709 * NOTE: This does not indicate that the processor is actually running. 710 * NOTE: This does not indicate that device has completed 711 * init or post-power-down restore of internal SRAM memory. 712 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 713 * SRAM is restored and uCode is in normal operation mode. 714 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 715 * do not need to save/restore it. 716 * NOTE: After device reset, this bit remains "0" until host sets 717 * INIT_DONE 718 */ 719#define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 720#define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 721#define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 722#define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 723 724#define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 725 726#define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 727#define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 728#define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 729 730 731/* HW REV */ 732#define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 733#define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 734#define IWX_CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) 735 736#define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0) 737#define IWX_CSR_HW_REV_TYPE_QU_B0 (0x0000334) 738#define IWX_CSR_HW_REV_TYPE_QU_C0 (0x0000338) 739#define IWX_CSR_HW_REV_TYPE_QUZ (0x0000354) 740#define IWX_CSR_HW_REV_TYPE_SO (0x0000370) 741#define IWX_CSR_HW_REV_TYPE_TY (0x0000420) 742 743/* HW RFID */ 744#define IWX_CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 745#define IWX_CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 746#define IWX_CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 747#define IWX_CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 748#define IWX_CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) 749#define IWX_CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) 750 751/* CSR GIO */ 752#define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 753 754/* 755 * UCODE-DRIVER GP (general purpose) mailbox register 1 756 * Host driver and uCode write and/or read this register to communicate with 757 * each other. 758 * Bit fields: 759 * 4: UCODE_DISABLE 760 * Host sets this to request permanent halt of uCode, same as 761 * sending CARD_STATE command with "halt" bit set. 762 * 3: CT_KILL_EXIT 763 * Host sets this to request exit from CT_KILL state, i.e. host thinks 764 * device temperature is low enough to continue normal operation. 765 * 2: CMD_BLOCKED 766 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 767 * to release uCode to clear all Tx and command queues, enter 768 * unassociated mode, and power down. 769 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 770 * 1: SW_BIT_RFKILL 771 * Host sets this when issuing CARD_STATE command to request 772 * device sleep. 773 * 0: MAC_SLEEP 774 * uCode sets this when preparing a power-saving power-down. 775 * uCode resets this when power-up is complete and SRAM is sane. 776 * NOTE: device saves internal SRAM data to host when powering down, 777 * and must restore this data after powering back up. 778 * MAC_SLEEP is the best indication that restore is complete. 779 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 780 * do not need to save/restore it. 781 */ 782#define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 783#define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 784#define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 785#define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 786#define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 787 788/* GIO Chicken Bits (PCI Express bus link power management) */ 789#define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 790#define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 791 792/* HPET MEM debug */ 793#define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 794 795/* DRAM INT TABLE */ 796#define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 797#define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 798#define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 799 800/* 22000 configuration registers */ 801 802/* 803 * TFH Configuration register. 804 * 805 * BIT fields: 806 * 807 * Bits 3:0: 808 * Define the maximum number of pending read requests. 809 * Maximum configuration value allowed is 0xC 810 * Bits 9:8: 811 * Define the maximum transfer size. (64 / 128 / 256) 812 * Bit 10: 813 * When bit is set and transfer size is set to 128B, the TFH will enable 814 * reading chunks of more than 64B only if the read address is aligned to 128B. 815 * In case of DRAM read address which is not aligned to 128B, the TFH will 816 * enable transfer size which doesn't cross 64B DRAM address boundary. 817*/ 818#define IWX_TFH_TRANSFER_MODE (0x1F40) 819#define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc 820#define IWX_TFH_CHUNK_SIZE_128 (1 << 8) 821#define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10) 822 823/* 824 * Defines the offset address in dwords referring from the beginning of the 825 * Tx CMD which will be updated in DRAM. 826 * Note that the TFH offset address for Tx CMD update is always referring to 827 * the start of the TFD first TB. 828 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 829 */ 830#define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48) 831 832/* 833 * Controls TX DMA operation 834 * 835 * BIT fields: 836 * 837 * Bits 31:30: Enable the SRAM DMA channel. 838 * Turning on bit 31 will kick the SRAM2DRAM DMA. 839 * Note that the sram2dram may be enabled only after configuring the DRAM and 840 * SRAM addresses registers and the byte count register. 841 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 842 * set to 1 - interrupt is sent to the driver 843 * Bit 0: Indicates the snoop configuration 844*/ 845#define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 846#define IWX_TFH_SRV_DMA_SNOOP (1 << 0) 847#define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24) 848#define IWX_TFH_SRV_DMA_START (1U << 31) 849 850/* Defines the DMA SRAM write start address to transfer a data block */ 851#define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 852 853/* Defines the 64bits DRAM start address to read the DMA data block from */ 854#define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 855 856/* 857 * Defines the number of bytes to transfer from DRAM to SRAM. 858 * Note that this register may be configured with non-dword aligned size. 859 */ 860#define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70) 861 862/* 9000 rx series registers */ 863 864#define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 865#define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 866/* Write index table */ 867#define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080 868#define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4) 869/* Write index table - shadow registers */ 870#define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 871#define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 872/* Read index table */ 873#define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0 874#define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4) 875/* Used list table */ 876#define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 877#define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 878/* Write index table */ 879#define IWX_RFH_Q0_URBDCB_WIDX 0xA08180 880#define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4) 881#define IWX_RFH_Q0_URBDCB_VAID 0xA081C0 882#define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4) 883/* stts */ 884#define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 885#define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 886 887#define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280 888#define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 889#define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300 890#define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8) 891 892/** 893 * RFH Status Register 894 * 895 * Bit fields: 896 * 897 * Bit 29: RBD_FETCH_IDLE 898 * This status flag is set by the RFH when there is no active RBD fetch from 899 * DRAM. 900 * Once the RFH RBD controller starts fetching (or when there is a pending 901 * RBD read response from DRAM), this flag is immediately turned off. 902 * 903 * Bit 30: SRAM_DMA_IDLE 904 * This status flag is set by the RFH when there is no active transaction from 905 * SRAM to DRAM. 906 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 907 * 908 * Bit 31: RXF_DMA_IDLE 909 * This status flag is set by the RFH when there is no active transaction from 910 * RXF to DRAM. 911 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 912 */ 913#define IWX_RFH_GEN_STATUS 0xA09808 914#define IWX_RFH_GEN_STATUS_GEN3 0xA07824 915#define IWX_RBD_FETCH_IDLE (1 << 29) 916#define IWX_SRAM_DMA_IDLE (1 << 30) 917#define IWX_RXF_DMA_IDLE (1U << 31) 918 919/* DMA configuration */ 920#define IWX_RFH_RXF_DMA_CFG 0xA09820 921#define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880 922/* RB size */ 923#define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 924#define IWX_RFH_RXF_DMA_RB_SIZE_POS 16 925#define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 926#define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 927#define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 928#define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 929#define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 930#define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS) 931#define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS) 932#define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS) 933#define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS) 934#define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS) 935/* RB Circular Buffer size:defines the table sizes in RBD units */ 936#define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 937#define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20 938#define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 939#define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 940#define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 941#define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 942#define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 943#define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 944#define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 945#define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 946#define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 947#define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 948#define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 949#define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS) 950#define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 951#define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 952#define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 953#define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31) 954 955#define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C 956 957#define IWX_RFH_GEN_CFG 0xA09800 958#define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 959#define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 960#define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 961#define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 962/* the driver assumes everywhere that the default RXQ is 0 */ 963#define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 964 965/* end of 9000 rx series registers */ 966 967/* 968 * This register is written by driver and is read by uCode during boot flow. 969 * Note this address is cleared after MAC reset. 970 */ 971#define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40) 972#define IWX_UREG_CPU_INIT_RUN (0xa05c44) 973 974/* 975 * HBUS (Host-side Bus) 976 * 977 * HBUS registers are mapped directly into PCI bus space, but are used 978 * to indirectly access device's internal memory or registers that 979 * may be powered-down. 980 * 981 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 982 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 983 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 984 * internal resources. 985 * 986 * Do not use iwl_write32()/iwl_read32() family to access these registers; 987 * these provide only simple PCI bus access, without waking up the MAC. 988 */ 989#define IWX_HBUS_BASE (0x400) 990 991/* 992 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 993 * structures, error log, event log, verifying uCode load). 994 * First write to address register, then read from or write to data register 995 * to complete the job. Once the address register is set up, accesses to 996 * data registers auto-increment the address by one dword. 997 * Bit usage for address registers (read or write): 998 * 0-31: memory address within device 999 */ 1000#define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c) 1001#define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010) 1002#define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018) 1003#define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c) 1004 1005/* 1006 * Registers for accessing device's internal peripheral registers 1007 * (e.g. SCD, BSM, etc.). First write to address register, 1008 * then read from or write to data register to complete the job. 1009 * Bit usage for address registers (read or write): 1010 * 0-15: register address (offset) within device 1011 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 1012 */ 1013#define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044) 1014#define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048) 1015#define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c) 1016#define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050) 1017 1018/* enable the ID buf for read */ 1019#define IWX_WFPM_PS_CTL_CLR 0xa0300c 1020#define IWX_WFMP_MAC_ADDR_0 0xa03080 1021#define IWX_WFMP_MAC_ADDR_1 0xa03084 1022#define IWX_LMPM_PMG_EN 0xa01cec 1023#define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 1024#define IWX_RFIC_REG_RD 0xad0470 1025#define IWX_WFPM_CTRL_REG 0xa03030 1026#define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 1027#define IWX_ENABLE_WFPM 0x80000000 1028 1029#define IWX_AUX_MISC_MASTER1_EN 0xa20818 1030#define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 1031#define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 1032#define IWX_RSA_ENABLE 0xa24b08 1033#define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0 1034#define IWX_PREG_PRPH_WPROT_9000 0xa04ce0 1035#define IWX_PREG_PRPH_WPROT_22000 0xa04d00 1036#define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78 1037#define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000 1038#define IWX_SB_CFG_BASE_OVERRIDE 0xa20000 1039#define IWX_SB_MODIFY_CFG_FLAG 0xa03088 1040#define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0 1041#define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4 1042 1043#define IWX_UREG_CHICK 0xa05c00 1044#define IWX_UREG_CHICK_MSI_ENABLE (1 << 24) 1045#define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25) 1046 1047#define IWX_HPM_DEBUG 0xa03440 1048#define IWX_PERSISTENCE_BIT (1 << 12) 1049#define IWX_PREG_WFPM_ACCESS (1 << 12) 1050 1051#define IWX_HPM_HIPM_GEN_CFG 0xa03458 1052#define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0) 1053#define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1) 1054#define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10) 1055 1056#define IWX_UREG_DOORBELL_TO_ISR6 0xa05c04 1057#define IWX_UREG_DOORBELL_TO_ISR6_NMI_BIT (1 << 0) 1058#define IWX_UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE ((1 << 0) | (1 << 1)) 1059#define IWX_UREG_DOORBELL_TO_ISR6_SUSPEND (1 << 18) 1060#define IWX_UREG_DOORBELL_TO_ISR6_RESUME (1 << 19) 1061#define IWX_UREG_DOORBELL_TO_ISR6_PNVM (1 << 20) 1062 1063/* LTR control (Qu only) */ 1064#define IWX_HPM_MAC_LTR_CSR 0xa0348c 1065#define IWX_HPM_MAC_LRT_ENABLE_ALL 0xf 1066/* also uses CSR_LTR_* for values */ 1067#define IWX_HPM_UMAC_LTR 0xa03480 1068 1069/* 1070 * Per-Tx-queue write pointer (index, really!) 1071 * Indicates index to next TFD that driver will fill (1 past latest filled). 1072 * Bit usage: 1073 * 0-7: queue write index 1074 * 11-8: queue selector 1075 */ 1076#define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060) 1077 1078/********************************************************** 1079 * CSR values 1080 **********************************************************/ 1081 /* 1082 * host interrupt timeout value 1083 * used with setting interrupt coalescing timer 1084 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 1085 * 1086 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 1087 */ 1088#define IWX_HOST_INT_TIMEOUT_MAX (0xFF) 1089#define IWX_HOST_INT_TIMEOUT_DEF (0x40) 1090#define IWX_HOST_INT_TIMEOUT_MIN (0x0) 1091#define IWX_HOST_INT_OPER_MODE (1U << 31) 1092 1093/***************************************************************************** 1094 * MSIX related registers * 1095 *****************************************************************************/ 1096 1097#define IWX_CSR_MSIX_BASE (0x2000) 1098#define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800) 1099#define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804) 1100#define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808) 1101#define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C) 1102#define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810) 1103#define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880) 1104#define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890) 1105#define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000) 1106#define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 1107#define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause)) 1108 1109/* 1110 * Causes for the FH register interrupts 1111 */ 1112enum msix_fh_int_causes { 1113 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 1114 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 1115 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 1116 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 1117 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 1118 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 1119}; 1120 1121/* 1122 * Causes for the HW register interrupts 1123 */ 1124enum mix_hw_int_causes { 1125 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 1126 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 1127 IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE = (1 << 2), 1128 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 1129 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 1130 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 1131 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 1132 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 1133 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 1134 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 1135 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 1136 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 1137}; 1138 1139/* 1140 * Registers to map causes to vectors 1141 */ 1142enum msix_ivar_for_cause { 1143 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 1144 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 1145 IWX_MSIX_IVAR_CAUSE_S2D = 0x3, 1146 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 1147 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 1148 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 1149 IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE = 0x12, 1150 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 1151 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 1152 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 1153 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 1154 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 1155 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 1156 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 1157 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 1158}; 1159 1160#define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 1161#define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 1162 1163#define IWX_CSR_ADDR_BASE(sc) ((sc)->mac_addr_from_csr) 1164#define IWX_CSR_MAC_ADDR0_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x00) 1165#define IWX_CSR_MAC_ADDR1_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x04) 1166#define IWX_CSR_MAC_ADDR0_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x08) 1167#define IWX_CSR_MAC_ADDR1_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x0c) 1168 1169/** 1170 * uCode API flags 1171 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1172 * was a separate TLV but moved here to save space. 1173 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1174 * treats good CRC threshold as a boolean 1175 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1176 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1177 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1178 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1179 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1180 * offload profile config command. 1181 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1182 * (rather than two) IPv6 addresses 1183 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1184 * from the probe request template. 1185 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1186 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1187 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 1188 * single bound interface). 1189 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 1190 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 1191 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 1192 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 1193 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 1194 * 1195 */ 1196#define IWX_UCODE_TLV_FLAGS_PAN (1 << 0) 1197#define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 1198#define IWX_UCODE_TLV_FLAGS_MFP (1 << 2) 1199#define IWX_UCODE_TLV_FLAGS_P2P (1 << 3) 1200#define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 1201#define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 1202#define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 1203#define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 1204#define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 1205#define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 1206#define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 1207#define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 1208#define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 1209#define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 1210#define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 1211#define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 1212#define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 1213#define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 1214#define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 1215 1216#define IWX_UCODE_TLV_FLAG_BITS \ 1217 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 1218 1219/** 1220 * uCode TLV api 1221 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 1222 * longer than the passive one, which is essential for fragmented scan. 1223 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 1224 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 1225 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 1226 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format 1227 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 1228 * (command version 3) that supports per-chain limits 1229 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 1230 * iteration complete notification, and the timestamp reported for RX 1231 * received during scan, are reported in TSF of the mac specified in the 1232 * scan request. 1233 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 1234 * ADD_MODIFY_STA_KEY_API_S_VER_2. 1235 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment. 1236 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 1237 * instead of 3. 1238 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 1239 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of 1240 * SCAN_CONFIG_DB_CMD_API_S. 1241 * 1242 * @IWX_NUM_UCODE_TLV_API: number of bits used 1243 */ 1244#define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8 1245#define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9 1246#define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14 1247#define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18 1248#define IWX_UCODE_TLV_API_NEW_VERSION 20 1249#define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 1250#define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27 1251#define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28 1252#define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29 1253#define IWX_UCODE_TLV_API_STA_TYPE 30 1254#define IWX_UCODE_TLV_API_NAN2_VER2 31 1255#define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32 1256#define IWX_UCODE_TLV_API_NEW_RX_STATS 35 1257#define IWX_UCODE_TLV_API_WOWLAN_KEY_MATERIAL 36 1258#define IWX_UCODE_TLV_API_QUOTA_LOW_LATENCY 38 1259#define IWX_UCODE_TLV_API_DEPRECATE_TTAK 41 1260#define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 1261#define IWX_UCODE_TLV_API_NAN_NOTIF_V2 43 1262#define IWX_UCODE_TLV_API_FRAG_EBS 44 1263#define IWX_UCODE_TLV_API_REDUCE_TX_POWER 45 1264#define IWX_UCODE_TLV_API_SHORT_BEACON_NOTIF 46 1265#define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47 1266#define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48 1267#define IWX_UCODE_TLV_API_FTM_NEW_RANGE_REQ 49 1268#define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 1269#define IWX_UCODE_TLV_API_SCAN_OFFLOAD_CHANS 50 1270#define IWX_UCODE_TLV_API_MBSSID_HE 52 1271#define IWX_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE 53 1272#define IWX_UCODE_TLV_API_FTM_RTT_ACCURACY 54 1273#define IWX_UCODE_TLV_API_SAR_TABLE_VER 55 1274#define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 1275#define IWX_UCODE_TLV_API_ADWELL_HB_DEF_N_AP 57 1276#define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 1277#define IWX_UCODE_TLV_API_BAND_IN_RX_DATA 59 1278#define IWX_NUM_UCODE_TLV_API 128 1279 1280#define IWX_UCODE_TLV_API_BITS \ 1281 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 1282 1283/** 1284 * uCode capabilities 1285 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 1286 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 1287 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 1288 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 1289 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 1290 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 1291 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 1292 * tx power value into TPC Report action frame and Link Measurement Report 1293 * action frame 1294 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 1295 * channel in DS parameter set element in probe requests. 1296 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 1297 * probe requests. 1298 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 1299 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 1300 * which also implies support for the scheduler configuration command 1301 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 1302 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 1303 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 1304 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 1305 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 1306 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 1307 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 1308 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 1309 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 1310 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 1311 * sources for the MCC. This TLV bit is a future replacement to 1312 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 1313 * is supported. 1314 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 1315 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 1316 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 1317 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 1318 * 0=no support) 1319 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band 1320 * (6 GHz). 1321 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 1322 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 1323 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 1324 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 1325 * antenna the beacon should be transmitted 1326 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 1327 * from AP and will send it upon d0i3 exit. 1328 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 1329 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 1330 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 1331 * thresholds reporting 1332 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 1333 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 1334 * regular image. 1335 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 1336 * memory addresses from the firmware. 1337 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 1338 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 1339 * 0=no support) 1340 * 1341 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used 1342 */ 1343#define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0 1344#define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1 1345#define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2 1346#define IWX_UCODE_TLV_CAPA_BEAMFORMER 3 1347#define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5 1348#define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6 1349#define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 1350#define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 1351#define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 1352#define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 1353#define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12 1354#define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 1355#define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 1356#define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 1357#define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 1358#define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 1359#define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21 1360#define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 1361#define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 1362#define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28 1363#define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 1364#define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30 1365#define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 1366#define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34 1367#define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35 1368#define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37 1369#define IWX_UCODE_TLV_CAPA_STA_PM_NOTIF 38 1370#define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 1371#define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40 1372#define IWX_UCODE_TLV_CAPA_D0I3_END_FIRST 41 1373#define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43 1374#define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 1375#define IWX_UCODE_TLV_CAPA_COEX_SCHEMA_2 45 1376#define IWX_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD 46 1377#define IWX_UCODE_TLV_CAPA_FTM_CALIBRATED 47 1378#define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 1379#define IWX_UCODE_TLV_CAPA_CS_MODIFY 49 1380#define IWX_UCODE_TLV_CAPA_SET_LTR_GEN2 50 1381#define IWX_UCODE_TLV_CAPA_SET_PPAG 52 1382#define IWX_UCODE_TLV_CAPA_TAS_CFG 53 1383#define IWX_UCODE_TLV_CAPA_SESSION_PROT_CMD 54 1384#define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56 1385#define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57 1386#define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58 1387#define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56 1388#define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57 1389#define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58 1390#define IWX_UCODE_TLV_CAPA_BAID_ML_SUPPORT 63 1391#define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 1392#define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 1393#define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 1394#define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 1395#define IWX_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD 70 1396#define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 1397#define IWX_UCODE_TLV_CAPA_BEACON_STORING 72 1398#define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V3 73 1399#define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 1400#define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 1401#define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76 1402#define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 1403#define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79 1404#define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 1405#define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81 1406#define IWX_UCODE_TLV_CAPA_TX_POWER_ACK 84 1407#define IWX_UCODE_TLV_CAPA_D3_DEBUG 87 1408#define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88 1409#define IWX_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT 89 1410#define IWX_UCODE_TLV_CAPA_CSI_REPORTING 90 1411#define IWX_UCODE_TLV_CAPA_CSI_REPORTING_V2 91 1412#define IWX_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP 92 1413#define IWX_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP 93 1414#define IWX_UCODE_TLV_CAPA_MLME_OFFLOAD 96 1415#define IWX_UCODE_TLV_CAPA_BIGTK_SUPPORT 100 1416#define IWX_UCODE_TLV_CAPA_RFIM_SUPPORT 102 1417 1418#define IWX_NUM_UCODE_TLV_CAPA 128 1419 1420/* 1421 * For 16.0 uCode and above, there is no differentiation between sections, 1422 * just an offset to the HW address. 1423 */ 1424#define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 1425#define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB 1426 1427/* uCode version contains 4 values: Major/Minor/API/Serial */ 1428#define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 1429#define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 1430#define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 1431#define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 1432 1433/* 1434 * Calibration control struct. 1435 * Sent as part of the phy configuration command. 1436 * @flow_trigger: bitmap for which calibrations to perform according to 1437 * flow triggers. 1438 * @event_trigger: bitmap for which calibrations to perform according to 1439 * event triggers. 1440 */ 1441struct iwx_tlv_calib_ctrl { 1442 uint32_t flow_trigger; 1443 uint32_t event_trigger; 1444} __packed; 1445 1446#define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0 1447#define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS) 1448#define IWX_FW_PHY_CFG_RADIO_STEP_POS 2 1449#define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS) 1450#define IWX_FW_PHY_CFG_RADIO_DASH_POS 4 1451#define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS) 1452#define IWX_FW_PHY_CFG_TX_CHAIN_POS 16 1453#define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS) 1454#define IWX_FW_PHY_CFG_RX_CHAIN_POS 20 1455#define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS) 1456 1457/** 1458 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW. 1459 * @cipher: a cipher suite selector 1460 * @flags: cipher scheme flags (currently reserved for a future use) 1461 * @hdr_len: a size of MPDU security header 1462 * @pn_len: a size of PN 1463 * @pn_off: an offset of pn from the beginning of the security header 1464 * @key_idx_off: an offset of key index byte in the security header 1465 * @key_idx_mask: a bit mask of key_idx bits 1466 * @key_idx_shift: bit shift needed to get key_idx 1467 * @mic_len: mic length in bytes 1468 * @hw_cipher: a HW cipher index used in host commands 1469 */ 1470struct iwx_fw_cipher_scheme { 1471 uint32_t cipher; 1472 uint8_t flags; 1473 uint8_t hdr_len; 1474 uint8_t pn_len; 1475 uint8_t pn_off; 1476 uint8_t key_idx_off; 1477 uint8_t key_idx_mask; 1478 uint8_t key_idx_shift; 1479 uint8_t mic_len; 1480 uint8_t hw_cipher; 1481} __packed; 1482 1483/** 1484 * struct iwx_fw_cscheme_list - a cipher scheme list 1485 * @size: a number of entries 1486 * @cs: cipher scheme entries 1487 */ 1488struct iwx_fw_cscheme_list { 1489 uint8_t size; 1490 struct iwx_fw_cipher_scheme cs[]; 1491} __packed; 1492 1493/* v1/v2 uCode file layout */ 1494struct iwx_ucode_header { 1495 uint32_t ver; /* major/minor/API/serial */ 1496 union { 1497 struct { 1498 uint32_t inst_size; /* bytes of runtime code */ 1499 uint32_t data_size; /* bytes of runtime data */ 1500 uint32_t init_size; /* bytes of init code */ 1501 uint32_t init_data_size; /* bytes of init data */ 1502 uint32_t boot_size; /* bytes of bootstrap code */ 1503 uint8_t data[0]; /* in same order as sizes */ 1504 } v1; 1505 struct { 1506 uint32_t build; /* build number */ 1507 uint32_t inst_size; /* bytes of runtime code */ 1508 uint32_t data_size; /* bytes of runtime data */ 1509 uint32_t init_size; /* bytes of init code */ 1510 uint32_t init_data_size; /* bytes of init data */ 1511 uint32_t boot_size; /* bytes of bootstrap code */ 1512 uint8_t data[0]; /* in same order as sizes */ 1513 } v2; 1514 } u; 1515}; 1516 1517/* 1518 * new TLV uCode file layout 1519 * 1520 * The new TLV file format contains TLVs, that each specify 1521 * some piece of data. 1522 */ 1523 1524#define IWX_UCODE_TLV_INVALID 0 /* unused */ 1525#define IWX_UCODE_TLV_INST 1 1526#define IWX_UCODE_TLV_DATA 2 1527#define IWX_UCODE_TLV_INIT 3 1528#define IWX_UCODE_TLV_INIT_DATA 4 1529#define IWX_UCODE_TLV_BOOT 5 1530#define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 1531#define IWX_UCODE_TLV_PAN 7 1532#define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8 1533#define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9 1534#define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10 1535#define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11 1536#define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12 1537#define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13 1538#define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14 1539#define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15 1540#define IWX_UCODE_TLV_WOWLAN_INST 16 1541#define IWX_UCODE_TLV_WOWLAN_DATA 17 1542#define IWX_UCODE_TLV_FLAGS 18 1543#define IWX_UCODE_TLV_SEC_RT 19 1544#define IWX_UCODE_TLV_SEC_INIT 20 1545#define IWX_UCODE_TLV_SEC_WOWLAN 21 1546#define IWX_UCODE_TLV_DEF_CALIB 22 1547#define IWX_UCODE_TLV_PHY_SKU 23 1548#define IWX_UCODE_TLV_SECURE_SEC_RT 24 1549#define IWX_UCODE_TLV_SECURE_SEC_INIT 25 1550#define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26 1551#define IWX_UCODE_TLV_NUM_OF_CPU 27 1552#define IWX_UCODE_TLV_CSCHEME 28 1553#define IWX_UCODE_TLV_API_CHANGES_SET 29 1554#define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30 1555#define IWX_UCODE_TLV_N_SCAN_CHANNELS 31 1556#define IWX_UCODE_TLV_PAGING 32 1557#define IWX_UCODE_TLV_SEC_RT_USNIFFER 34 1558#define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35 1559#define IWX_UCODE_TLV_FW_VERSION 36 1560#define IWX_UCODE_TLV_FW_DBG_DEST 38 1561#define IWX_UCODE_TLV_FW_DBG_CONF 39 1562#define IWX_UCODE_TLV_FW_DBG_TRIGGER 40 1563#define IWX_UCODE_TLV_CMD_VERSIONS 48 1564#define IWX_UCODE_TLV_FW_GSCAN_CAPA 50 1565#define IWX_UCODE_TLV_FW_MEM_SEG 51 1566#define IWX_UCODE_TLV_IML 52 1567#define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53 1568#define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54 1569#define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55 1570#define IWX_UCODE_TLV_FW_RECOVERY_INFO 57 1571#define IWX_UCODE_TLV_HW_TYPE 58 1572#define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59 1573#define IWX_UCODE_TLV_FW_FSEQ_VERSION 60 1574#define IWX_UCODE_TLV_PHY_INTEGRATION_VERSION 61 1575#define IWX_UCODE_TLV_PNVM_VERSION 62 1576#define IWX_UCODE_TLV_PNVM_SKU 64 1577 1578#define IWX_UCODE_TLV_SEC_TABLE_ADDR 66 1579#define IWX_UCODE_TLV_D3_KEK_KCK_ADDR 67 1580#define IWX_UCODE_TLV_CURRENT_PC 68 1581 1582#define IWX_UCODE_TLV_CONST_BASE 0x100 1583#define IWX_UCODE_TLV_FW_NUM_STATIONS (IWX_UCODE_TLV_CONST_BASE + 0) 1584#define IWX_UCODE_TLV_FW_NUM_BEACONS (IWX_UCODE_TLV_CONST_BASE + 2) 1585 1586#define IWX_UCODE_TLV_DEBUG_BASE 0x1000005 1587#define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0) 1588#define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1) 1589#define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2) 1590#define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3) 1591#define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4) 1592#define IWX_UCODE_TLV_TYPE_CONF_SET (IWX_UCODE_TLV_DEBUG_BASE + 5) 1593#define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_CONF_SET 1594 1595 1596struct iwx_ucode_tlv { 1597 uint32_t type; /* see above */ 1598 uint32_t length; /* not including type/length fields */ 1599 uint8_t data[0]; 1600}; 1601 1602struct iwx_ucode_api { 1603 uint32_t api_index; 1604 uint32_t api_flags; 1605} __packed; 1606 1607struct iwx_ucode_capa { 1608 uint32_t api_index; 1609 uint32_t api_capa; 1610} __packed; 1611 1612#define IWX_TLV_UCODE_MAGIC 0x0a4c5749 1613 1614struct iwx_tlv_ucode_header { 1615 /* 1616 * The TLV style ucode header is distinguished from 1617 * the v1/v2 style header by first four bytes being 1618 * zero, as such is an invalid combination of 1619 * major/minor/API/serial versions. 1620 */ 1621 uint32_t zero; 1622 uint32_t magic; 1623 uint8_t human_readable[64]; 1624 uint32_t ver; /* major/minor/API/serial */ 1625 uint32_t build; 1626 uint64_t ignore; 1627 /* 1628 * The data contained herein has a TLV layout, 1629 * see above for the TLV header and types. 1630 * Note that each TLV is padded to a length 1631 * that is a multiple of 4 for alignment. 1632 */ 1633 uint8_t data[0]; 1634}; 1635 1636/* 1637 * Registers in this file are internal, not PCI bus memory mapped. 1638 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers. 1639 */ 1640#define IWX_PRPH_BASE (0x00000) 1641#define IWX_PRPH_END (0xFFFFF) 1642 1643/****************************/ 1644/* Flow Handler Definitions */ 1645/****************************/ 1646 1647/** 1648 * struct iwx_rb_status - receive buffer status 1649 * host memory mapped FH registers 1650 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1651 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1652 * @finished_rb_num [0:11] - Indicates the index of the current RB 1653 * in which the last frame was written to 1654 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1655 * which was transferred 1656 */ 1657struct iwx_rb_status { 1658 uint16_t closed_rb_num; 1659 uint16_t closed_fr_num; 1660 uint16_t finished_rb_num; 1661 uint16_t finished_fr_nam; 1662 uint32_t unused; 1663} __packed; 1664 1665 1666#define IWX_TFD_QUEUE_SIZE_MAX (256) 1667#define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536) 1668/* cb size is the exponent - 3 */ 1669#define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3) 1670#define IWX_TFD_QUEUE_SIZE_BC_DUP (64) 1671#define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \ 1672 IWX_TFD_QUEUE_SIZE_BC_DUP) 1673#define IWX_TFD_QUEUE_BC_SIZE_GEN3_AX210 1024 1674#define IWX_TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4) 1675#define IWX_TFH_NUM_TBS 25 1676 1677/** 1678 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor 1679 * 1680 * This structure contains dma address and length of transmission address 1681 * 1682 * @tb_len length of the tx buffer 1683 * @addr 64 bits dma address 1684 */ 1685struct iwx_tfh_tb { 1686 uint16_t tb_len; 1687 uint64_t addr; 1688} __packed; 1689 1690/** 1691 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1692 * Both driver and device share these circular buffers, each of which must be 1693 * contiguous 256 TFDs. 1694 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 1695 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 1696 * 1697 * Each TFD contains pointer/size information for up to 25 data buffers 1698 * in host DRAM. These buffers collectively contain the (one) frame described 1699 * by the TFD. Each buffer must be a single contiguous block of memory within 1700 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1701 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1702 * Tx frame, up to 8 KBytes in size. 1703 * 1704 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1705 */ 1706 1707/** 1708 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD) 1709 * @ num_tbs 0-4 number of active tbs 1710 * 5 -15 reserved 1711 * @ tbs[25] transmit frame buffer descriptors 1712 * @ __pad padding 1713 */ 1714struct iwx_tfh_tfd { 1715 uint16_t num_tbs; 1716 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS]; 1717 uint32_t __pad; 1718} __packed; 1719 1720/* Fixed (non-configurable) rx data from phy */ 1721 1722/** 1723 * struct iwx_agn_schedq_bc_tbl scheduler byte count table 1724 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR 1725 * @tfd_offset 0-11 - tx command byte count 1726 * 12-13 - number of 64 byte chunks 1727 * 14-15 - reserved 1728 */ 1729struct iwx_agn_scd_bc_tbl { 1730 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE]; 1731} __packed; 1732 1733/** 1734 * struct iwx_gen3_bc_tbl_entry scheduler byte count table entry gen3 1735 * For AX210 and up, the table no longer needs to be contiguous in memory. 1736 * @tfd_offset: 0-13 - tx command byte count 1737 * 14-15 - number of 64 byte chunks 1738 */ 1739struct iwx_gen3_bc_tbl_entry { 1740 uint16_t tfd_offset; 1741} __packed; 1742 1743/** 1744 * DQA - Dynamic Queue Allocation -introduction 1745 * 1746 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1747 * to allow dynamic allocation of queues on-demand, rather than allocate them 1748 * statically ahead of time. Ideally, we would like to allocate one queue 1749 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1750 * even if it also needs to send traffic to a sleeping STA1, without being 1751 * blocked by the sleeping station. 1752 * 1753 * Although the queues in DQA mode are dynamically allocated, there are still 1754 * some queues that are statically allocated: 1755 * TXQ #0 - command queue 1756 * TXQ #1 - aux frames 1757 */ 1758 1759/* static DQA Tx queue numbers */ 1760#define IWX_DQA_CMD_QUEUE 0 1761#define IWX_DQA_AUX_QUEUE 1 1762 1763#define IWX_DQA_INJECT_MONITOR_QUEUE 2 /* used in monitor mode only */ 1764#define IWX_DQA_MGMT_QUEUE 1 /* default queue other modes */ 1765 1766/* Reserve 8 DQA Tx queues for QoS data frames. */ 1767#define IWX_MAX_TID_COUNT 8 1768#define IWX_FIRST_AGG_TX_QUEUE (IWX_DQA_MGMT_QUEUE + 1) 1769#define IWX_LAST_AGG_TX_QUEUE (IWX_FIRST_AGG_TX_QUEUE + IWX_MAX_TID_COUNT - 1) 1770#define IWX_NUM_TX_QUEUES (IWX_LAST_AGG_TX_QUEUE + 1) 1771 1772/** 1773 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1774 * can keep track of at one time when creating block-ack chains of frames. 1775 * Note that "64" matches the number of ack bits in a block-ack packet. 1776 */ 1777#define IWX_FRAME_LIMIT 64 1778 1779#define IWX_TX_FIFO_BK 0 1780#define IWX_TX_FIFO_BE 1 1781#define IWX_TX_FIFO_VI 2 1782#define IWX_TX_FIFO_VO 3 1783#define IWX_TX_FIFO_MCAST 5 1784#define IWX_TX_FIFO_CMD 7 1785 1786enum iwx_gen2_tx_fifo { 1787 IWX_GEN2_TX_FIFO_CMD = 0, 1788 IWX_GEN2_EDCA_TX_FIFO_BK, 1789 IWX_GEN2_EDCA_TX_FIFO_BE, 1790 IWX_GEN2_EDCA_TX_FIFO_VI, 1791 IWX_GEN2_EDCA_TX_FIFO_VO, 1792 IWX_GEN2_TRIG_TX_FIFO_BK, 1793 IWX_GEN2_TRIG_TX_FIFO_BE, 1794 IWX_GEN2_TRIG_TX_FIFO_VI, 1795 IWX_GEN2_TRIG_TX_FIFO_VO, 1796}; 1797 1798/** 1799 * TXQ config options 1800 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue 1801 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format 1802 */ 1803#define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0) 1804#define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1) 1805 1806#define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX 1807 1808/** 1809 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command 1810 * @sta_id: station id 1811 * @tid: tid of the queue 1812 * @flags: see &enum iwl_tx_queue_cfg_actions 1813 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3. 1814 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) 1815 * @byte_cnt_addr: address of byte count table 1816 * @tfdq_addr: address of TFD circular buffer 1817 */ 1818struct iwx_tx_queue_cfg_cmd { 1819 uint8_t sta_id; 1820 uint8_t tid; 1821 uint16_t flags; 1822 uint32_t cb_size; 1823 uint64_t byte_cnt_addr; 1824 uint64_t tfdq_addr; 1825} __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ 1826 1827/** 1828 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config 1829 * @queue_number: queue number assigned to this RA -TID 1830 * @flags: set on failure 1831 * @write_pointer: initial value for write pointer 1832 * @reserved: reserved 1833 */ 1834struct iwx_tx_queue_cfg_rsp { 1835 uint16_t queue_number; 1836 uint16_t flags; 1837 uint16_t write_pointer; 1838 uint16_t reserved; 1839} __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ 1840 1841 1842/* 1843 * Commands 1844 */ 1845#define IWX_ALIVE 0x1 1846#define IWX_REPLY_ERROR 0x2 1847#define IWX_INIT_COMPLETE_NOTIF 0x4 1848 1849/* PHY context commands */ 1850#define IWX_PHY_CONTEXT_CMD 0x8 1851#define IWX_DBG_CFG 0x9 1852 1853/* UMAC scan commands */ 1854#define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1855#define IWX_SCAN_CFG_CMD 0xc 1856#define IWX_SCAN_REQ_UMAC 0xd 1857#define IWX_SCAN_ABORT_UMAC 0xe 1858#define IWX_SCAN_COMPLETE_UMAC 0xf 1859 1860/* station table */ 1861#define IWX_ADD_STA_KEY 0x17 1862#define IWX_ADD_STA 0x18 1863#define IWX_REMOVE_STA 0x19 1864 1865/* TX */ 1866#define IWX_TX_CMD 0x1c 1867#define IWX_TXPATH_FLUSH 0x1e 1868#define IWX_MGMT_MCAST_KEY 0x1f 1869 1870/* scheduler config */ 1871#define IWX_SCD_QUEUE_CFG 0x1d 1872 1873/* global key */ 1874#define IWX_WEP_KEY 0x20 1875 1876/* MAC and Binding commands */ 1877#define IWX_MAC_CONTEXT_CMD 0x28 1878#define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1879#define IWX_TIME_EVENT_NOTIFICATION 0x2a 1880#define IWX_BINDING_CONTEXT_CMD 0x2b 1881#define IWX_TIME_QUOTA_CMD 0x2c 1882#define IWX_NON_QOS_TX_COUNTER_CMD 0x2d 1883 1884/* Calibration */ 1885#define IWX_TEMPERATURE_NOTIFICATION 0x62 1886#define IWX_CALIBRATION_CFG_CMD 0x65 1887#define IWX_CALIBRATION_RES_NOTIFICATION 0x66 1888#define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1889#define IWX_RADIO_VERSION_NOTIFICATION 0x68 1890 1891/* Phy */ 1892#define IWX_PHY_CONFIGURATION_CMD 0x6a 1893 1894/* Power - legacy power table command */ 1895#define IWX_POWER_TABLE_CMD 0x77 1896#define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1897#define IWX_LTR_CONFIG 0xee 1898 1899/* NVM */ 1900#define IWX_NVM_ACCESS_CMD 0x88 1901 1902#define IWX_SET_CALIB_DEFAULT_CMD 0x8e 1903 1904#define IWX_BEACON_NOTIFICATION 0x90 1905#define IWX_BEACON_TEMPLATE_CMD 0x91 1906#define IWX_TX_ANT_CONFIGURATION_CMD 0x98 1907#define IWX_BT_CONFIG 0x9b 1908#define IWX_STATISTICS_CMD 0x9c 1909#define IWX_STATISTICS_NOTIFICATION 0x9d 1910#define IWX_REDUCE_TX_POWER_CMD 0x9f 1911 1912/* RF-KILL commands and notifications */ 1913#define IWX_CARD_STATE_CMD 0xa0 1914#define IWX_CARD_STATE_NOTIFICATION 0xa1 1915 1916#define IWX_MISSED_BEACONS_NOTIFICATION 0xa2 1917 1918#define IWX_MFUART_LOAD_NOTIFICATION 0xb1 1919 1920/* Power - new power table command */ 1921#define IWX_MAC_PM_POWER_TABLE 0xa9 1922 1923#define IWX_REPLY_RX_PHY_CMD 0xc0 1924#define IWX_REPLY_RX_MPDU_CMD 0xc1 1925#define IWX_BAR_FRAME_RELEASE 0xc2 1926#define IWX_FRAME_RELEASE 0xc3 1927#define IWX_BA_NOTIF 0xc5 1928 1929/* Location Aware Regulatory */ 1930#define IWX_MCC_UPDATE_CMD 0xc8 1931#define IWX_MCC_CHUB_UPDATE_CMD 0xc9 1932 1933/* BT Coex */ 1934#define IWX_BT_COEX_PRIO_TABLE 0xcc 1935#define IWX_BT_COEX_PROT_ENV 0xcd 1936#define IWX_BT_PROFILE_NOTIFICATION 0xce 1937#define IWX_BT_COEX_CI 0x5d 1938 1939#define IWX_REPLY_SF_CFG_CMD 0xd1 1940#define IWX_REPLY_BEACON_FILTERING_CMD 0xd2 1941 1942/* DTS measurements */ 1943#define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 1944#define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd 1945 1946#define IWX_REPLY_DEBUG_CMD 0xf0 1947#define IWX_DEBUG_LOG_MSG 0xf7 1948 1949#define IWX_MCAST_FILTER_CMD 0xd0 1950 1951/* D3 commands/notifications */ 1952#define IWX_D3_CONFIG_CMD 0xd3 1953#define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4 1954#define IWX_OFFLOADS_QUERY_CMD 0xd5 1955#define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6 1956 1957/* for WoWLAN in particular */ 1958#define IWX_WOWLAN_PATTERNS 0xe0 1959#define IWX_WOWLAN_CONFIGURATION 0xe1 1960#define IWX_WOWLAN_TSC_RSC_PARAM 0xe2 1961#define IWX_WOWLAN_TKIP_PARAM 0xe3 1962#define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4 1963#define IWX_WOWLAN_GET_STATUSES 0xe5 1964#define IWX_WOWLAN_TX_POWER_PER_DB 0xe6 1965 1966/* and for NetDetect */ 1967#define IWX_NET_DETECT_CONFIG_CMD 0x54 1968#define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56 1969#define IWX_NET_DETECT_PROFILES_CMD 0x57 1970#define IWX_NET_DETECT_HOTSPOTS_CMD 0x58 1971#define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 1972 1973/* system group command IDs */ 1974#define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 1975 1976#define IWX_REPLY_MAX 0xff 1977 1978/* PHY_OPS subcommand IDs */ 1979#define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 1980#define IWX_CTDP_CONFIG_CMD 0x03 1981#define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04 1982#define IWX_CT_KILL_NOTIFICATION 0xFE 1983#define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 1984 1985/* command groups */ 1986#define IWX_LEGACY_GROUP 0x0 1987#define IWX_LONG_GROUP 0x1 1988#define IWX_SYSTEM_GROUP 0x2 1989#define IWX_MAC_CONF_GROUP 0x3 1990#define IWX_PHY_OPS_GROUP 0x4 1991#define IWX_DATA_PATH_GROUP 0x5 1992#define IWX_PROT_OFFLOAD_GROUP 0xb 1993#define IWX_REGULATORY_AND_NVM_GROUP 0xc 1994 1995/* SYSTEM_GROUP group subcommand IDs */ 1996 1997#define IWX_SHARED_MEM_CFG_CMD 0x00 1998#define IWX_SOC_CONFIGURATION_CMD 0x01 1999#define IWX_INIT_EXTENDED_CFG_CMD 0x03 2000#define IWX_FW_ERROR_RECOVERY_CMD 0x07 2001 2002/* MAC_CONF group subcommand IDs */ 2003#define IWX_SESSION_PROTECTION_CMD 0x05 2004#define IWX_SESSION_PROTECTION_NOTIF 0xfb 2005 2006/* DATA_PATH group subcommand IDs */ 2007#define IWX_DQA_ENABLE_CMD 0x00 2008#define IWX_RLC_CONFIG_CMD 0x08 2009#define IWX_TLC_MNG_CONFIG_CMD 0x0f 2010#define IWX_RX_BAID_ALLOCATION_CONFIG_CMD 0x16 2011#define IWX_SCD_QUEUE_CONFIG_CMD 0x17 2012#define IWX_RX_NO_DATA_NOTIF 0xf5 2013#define IWX_THERMAL_DUAL_CHAIN_REQUEST 0xf6 2014#define IWX_TLC_MNG_UPDATE_NOTIF 0xf7 2015 2016/* REGULATORY_AND_NVM group subcommand IDs */ 2017#define IWX_NVM_ACCESS_COMPLETE 0x00 2018#define IWX_NVM_GET_INFO 0x02 2019#define IWX_NVM_GET_INFO 0x02 2020#define IWX_PNVM_INIT_COMPLETE 0xfe 2021 2022/* 2023 * struct iwx_dqa_enable_cmd 2024 * @cmd_queue: the TXQ number of the command queue 2025 */ 2026struct iwx_dqa_enable_cmd { 2027 uint32_t cmd_queue; 2028} __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 2029 2030/** 2031 * struct iwx_cmd_response - generic response struct for most commands 2032 * @status: status of the command asked, changes for each one 2033 */ 2034struct iwx_cmd_response { 2035 uint32_t status; 2036}; 2037 2038/* 2039 * struct iwx_tx_ant_cfg_cmd 2040 * @valid: valid antenna configuration 2041 */ 2042struct iwx_tx_ant_cfg_cmd { 2043 uint32_t valid; 2044} __packed; 2045 2046/* 2047 * Calibration control struct. 2048 * Sent as part of the phy configuration command. 2049 * @flow_trigger: bitmap for which calibrations to perform according to 2050 * flow triggers. 2051 * @event_trigger: bitmap for which calibrations to perform according to 2052 * event triggers. 2053 */ 2054struct iwx_calib_ctrl { 2055 uint32_t flow_trigger; 2056 uint32_t event_trigger; 2057} __packed; 2058 2059/* This defines the bitmap of various calibrations to enable in both 2060 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD. 2061 */ 2062#define IWX_CALIB_CFG_XTAL_IDX (1 << 0) 2063#define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 2064#define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 2065#define IWX_CALIB_CFG_PAPD_IDX (1 << 3) 2066#define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4) 2067#define IWX_CALIB_CFG_DC_IDX (1 << 5) 2068#define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6) 2069#define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 2070#define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8) 2071#define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 2072#define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10) 2073#define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 2074#define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 2075#define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 2076#define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 2077#define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 2078#define IWX_CALIB_CFG_DAC_IDX (1 << 16) 2079#define IWX_CALIB_CFG_ABS_IDX (1 << 17) 2080#define IWX_CALIB_CFG_AGC_IDX (1 << 18) 2081 2082/* 2083 * Phy configuration command. 2084 */ 2085struct iwx_phy_cfg_cmd { 2086 uint32_t phy_cfg; 2087 struct iwx_calib_ctrl calib_control; 2088} __packed; 2089 2090#define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2091#define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2092#define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2093#define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2094#define IWX_PHY_CFG_TX_CHAIN_A (1 << 8) 2095#define IWX_PHY_CFG_TX_CHAIN_B (1 << 9) 2096#define IWX_PHY_CFG_TX_CHAIN_C (1 << 10) 2097#define IWX_PHY_CFG_RX_CHAIN_A (1 << 12) 2098#define IWX_PHY_CFG_RX_CHAIN_B (1 << 13) 2099#define IWX_PHY_CFG_RX_CHAIN_C (1 << 14) 2100 2101#define IWX_MAX_DTS_TRIPS 8 2102 2103/** 2104 * struct iwx_ct_kill_notif - CT-kill entry notification 2105 * 2106 * @temperature: the current temperature in celsius 2107 * @reserved: reserved 2108 */ 2109struct iwx_ct_kill_notif { 2110 uint16_t temperature; 2111 uint16_t reserved; 2112} __packed; /* GRP_PHY_CT_KILL_NTF */ 2113 2114/** 2115 * struct iwx_temp_report_ths_cmd - set temperature thresholds 2116 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD) 2117 * 2118 * @num_temps: number of temperature thresholds passed 2119 * @thresholds: array with the thresholds to be configured 2120 */ 2121struct iwx_temp_report_ths_cmd { 2122 uint32_t num_temps; 2123 uint16_t thresholds[IWX_MAX_DTS_TRIPS]; 2124} __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 2125 2126/* 2127 * channel flags in NVM 2128 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2129 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel 2130 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed 2131 * @IWX_NVM_CHANNEL_RADAR: radar detection required 2132 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 2133 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 2134 * on same channel on 2.4 or same UNII band on 5.2 2135 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate 2136 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2137 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2138 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2139 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2140 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 2141 */ 2142#define IWX_NVM_CHANNEL_VALID (1 << 0) 2143#define IWX_NVM_CHANNEL_IBSS (1 << 1) 2144#define IWX_NVM_CHANNEL_ACTIVE (1 << 3) 2145#define IWX_NVM_CHANNEL_RADAR (1 << 4) 2146#define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5) 2147#define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6) 2148#define IWX_NVM_CHANNEL_DFS (1 << 7) 2149#define IWX_NVM_CHANNEL_WIDE (1 << 8) 2150#define IWX_NVM_CHANNEL_40MHZ (1 << 9) 2151#define IWX_NVM_CHANNEL_80MHZ (1 << 10) 2152#define IWX_NVM_CHANNEL_160MHZ (1 << 11) 2153#define IWX_NVM_CHANNEL_DC_HIGH (1 << 12) 2154 2155/** 2156 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed 2157 * @reserved: reserved 2158 */ 2159struct iwx_nvm_access_complete_cmd { 2160 uint32_t reserved; 2161} __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */ 2162 2163/* 2164 * struct iwx_nvm_get_info - request to get NVM data 2165 */ 2166struct iwx_nvm_get_info { 2167 uint32_t reserved; 2168} __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */ 2169 2170/** 2171 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp 2172 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty 2173 */ 2174#define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0) 2175 2176/** 2177 * struct iwx_nvm_get_info_general - general NVM data 2178 * @flags: bit 0: 1 - empty, 0 - non-empty 2179 * @nvm_version: nvm version 2180 * @board_type: board type 2181 * @n_hw_addrs: number of reserved MAC addresses 2182 */ 2183struct iwx_nvm_get_info_general { 2184 uint32_t flags; 2185 uint16_t nvm_version; 2186 uint8_t board_type; 2187 uint8_t n_hw_addrs; 2188} __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */ 2189 2190/** 2191 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku 2192 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled 2193 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled 2194 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled 2195 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled 2196 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled 2197 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled 2198 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled 2199 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled 2200 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled 2201 */ 2202#define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0) 2203#define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1) 2204#define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2) 2205#define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3) 2206#define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4) 2207#define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5) 2208#define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8) 2209#define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14) 2210#define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15) 2211 2212/** 2213 * struct iwx_nvm_get_info_sku - mac information 2214 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags 2215 */ 2216struct iwx_nvm_get_info_sku { 2217 uint32_t mac_sku_flags; 2218} __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */ 2219 2220/** 2221 * struct iwx_nvm_get_info_phy - phy information 2222 * @tx_chains: BIT 0 chain A, BIT 1 chain B 2223 * @rx_chains: BIT 0 chain A, BIT 1 chain B 2224 */ 2225struct iwx_nvm_get_info_phy { 2226 uint32_t tx_chains; 2227 uint32_t rx_chains; 2228} __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */ 2229 2230#define IWX_NUM_CHANNELS_V1 51 2231#define IWX_NUM_CHANNELS 110 2232 2233/** 2234 * struct iwx_nvm_get_info_regulatory - regulatory information 2235 * @lar_enabled: is LAR enabled 2236 * @channel_profile: regulatory data of this channel 2237 * @reserved: reserved 2238 */ 2239struct iwx_nvm_get_info_regulatory_v1 { 2240 uint32_t lar_enabled; 2241 uint16_t channel_profile[IWX_NUM_CHANNELS_V1]; 2242 uint16_t reserved; 2243} __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */ 2244 2245/** 2246 * struct iwx_nvm_get_info_regulatory - regulatory information 2247 * @lar_enabled: is LAR enabled 2248 * @n_channels: number of valid channels in the array 2249 * @channel_profile: regulatory data of this channel 2250 */ 2251struct iwx_nvm_get_info_regulatory { 2252 uint32_t lar_enabled; 2253 uint32_t n_channels; 2254 uint32_t channel_profile[IWX_NUM_CHANNELS]; 2255} __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */ 2256 2257/** 2258 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data 2259 * @general: general NVM data 2260 * @mac_sku: data relating to MAC sku 2261 * @phy_sku: data relating to PHY sku 2262 * @regulatory: regulatory data 2263 */ 2264struct iwx_nvm_get_info_rsp_v3 { 2265 struct iwx_nvm_get_info_general general; 2266 struct iwx_nvm_get_info_sku mac_sku; 2267 struct iwx_nvm_get_info_phy phy_sku; 2268 struct iwx_nvm_get_info_regulatory_v1 regulatory; 2269} __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */ 2270 2271/** 2272 * struct iwx_nvm_get_info_rsp - response to get NVM data 2273 * @general: general NVM data 2274 * @mac_sku: data relating to MAC sku 2275 * @phy_sku: data relating to PHY sku 2276 * @regulatory: regulatory data 2277 */ 2278struct iwx_nvm_get_info_rsp { 2279 struct iwx_nvm_get_info_general general; 2280 struct iwx_nvm_get_info_sku mac_sku; 2281 struct iwx_nvm_get_info_phy phy_sku; 2282 struct iwx_nvm_get_info_regulatory regulatory; 2283} __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */ 2284 2285 2286#define IWX_ALIVE_STATUS_ERR 0xDEAD 2287#define IWX_ALIVE_STATUS_OK 0xCAFE 2288 2289struct iwx_lmac_debug_addrs { 2290 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2291 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2292 uint32_t cpu_register_ptr; 2293 uint32_t dbgm_config_ptr; 2294 uint32_t alive_counter_ptr; 2295 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2296 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2297 uint32_t st_fwrd_size; 2298} __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */ 2299 2300struct iwx_lmac_alive { 2301 uint32_t ucode_major; 2302 uint32_t ucode_minor; 2303 uint8_t ver_subtype; 2304 uint8_t ver_type; 2305 uint8_t mac; 2306 uint8_t opt; 2307 uint32_t timestamp; 2308 struct iwx_lmac_debug_addrs dbg_ptrs; 2309} __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 2310 2311struct iwx_umac_debug_addrs { 2312 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2313 uint32_t dbg_print_buff_addr; 2314} __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */ 2315 2316struct iwx_umac_alive { 2317 uint32_t umac_major; /* UMAC version: major */ 2318 uint32_t umac_minor; /* UMAC version: minor */ 2319 struct iwx_umac_debug_addrs dbg_ptrs; 2320} __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 2321 2322struct iwx_alive_resp_v4 { 2323 uint16_t status; 2324 uint16_t flags; 2325 struct iwx_lmac_alive lmac_data[2]; 2326 struct iwx_umac_alive umac_data; 2327} __packed; /* ALIVE_RES_API_S_VER_4 */ 2328 2329struct iwx_sku_id { 2330 uint32_t data[3]; 2331} __packed; /* SKU_ID_API_S_VER_1 */ 2332 2333struct iwx_alive_resp_v5 { 2334 uint16_t status; 2335 uint16_t flags; 2336 struct iwx_lmac_alive lmac_data[2]; 2337 struct iwx_umac_alive umac_data; 2338 struct iwx_sku_id sku_id; 2339} __packed; /* UCODE_ALIVE_NTFY_API_S_VER_5 */ 2340 2341struct iwx_imr_alive_info { 2342 uint64_t base_addr; 2343 uint32_t size; 2344 uint32_t enabled; 2345} __packed; /* IMR_ALIVE_INFO_API_S_VER_1 */ 2346 2347struct iwx_alive_resp_v6 { 2348 uint16_t status; 2349 uint16_t flags; 2350 struct iwx_lmac_alive lmac_data[2]; 2351 struct iwx_umac_alive umac_data; 2352 struct iwx_sku_id sku_id; 2353 struct iwx_imr_alive_info imr; 2354} __packed; /* UCODE_ALIVE_NTFY_API_S_VER_6 */ 2355 2356 2357#define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 2358#define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 2359 2360#define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 2361#define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 2362#define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1 2363#define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 2364#define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 2365 2366/** 2367 * struct iwx_soc_configuration_cmd - Set device stabilization latency 2368 * 2369 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 2370 * flag, because the FW treats the whole value as an integer. In 2371 * VER_2, we can set the bits independently. 2372 * @latency: time for SOC to ensure stable power & XTAL 2373 */ 2374struct iwx_soc_configuration_cmd { 2375 uint32_t flags; 2376 uint32_t latency; 2377} __packed; /* 2378 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 2379 * SOC_CONFIGURATION_CMD_S_VER_2 2380 */ 2381 2382/** 2383 * commands driver may send before finishing init flow 2384 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command 2385 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands 2386 */ 2387#define IWX_INIT_DEBUG_CFG (1 << 0) 2388#define IWX_INIT_NVM (1 << 1) 2389 2390/** 2391 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for 2392 * before finishing init flows 2393 * @init_flags: IWX_INIT_* flag bits 2394 */ 2395struct iwx_init_extended_cfg_cmd { 2396 uint32_t init_flags; 2397} __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */ 2398 2399/* Error response/notification */ 2400#define IWX_FW_ERR_UNKNOWN_CMD 0x0 2401#define IWX_FW_ERR_INVALID_CMD_PARAM 0x1 2402#define IWX_FW_ERR_SERVICE 0x2 2403#define IWX_FW_ERR_ARC_MEMORY 0x3 2404#define IWX_FW_ERR_ARC_CODE 0x4 2405#define IWX_FW_ERR_WATCH_DOG 0x5 2406#define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10 2407#define IWX_FW_ERR_WEP_KEY_SIZE 0x11 2408#define IWX_FW_ERR_OBSOLETE_FUNC 0x12 2409#define IWX_FW_ERR_UNEXPECTED 0xFE 2410#define IWX_FW_ERR_FATAL 0xFF 2411 2412/** 2413 * struct iwx_error_resp - FW error indication 2414 * ( IWX_REPLY_ERROR = 0x2 ) 2415 * @error_type: one of IWX_FW_ERR_* 2416 * @cmd_id: the command ID for which the error occurred 2417 * @bad_cmd_seq_num: sequence number of the erroneous command 2418 * @error_service: which service created the error, applicable only if 2419 * error_type = 2, otherwise 0 2420 * @timestamp: TSF in usecs. 2421 */ 2422struct iwx_error_resp { 2423 uint32_t error_type; 2424 uint8_t cmd_id; 2425 uint8_t reserved1; 2426 uint16_t bad_cmd_seq_num; 2427 uint32_t error_service; 2428 uint64_t timestamp; 2429} __packed; 2430 2431enum iwx_fw_dbg_reg_operator { 2432 CSR_ASSIGN, 2433 CSR_SETBIT, 2434 CSR_CLEARBIT, 2435 2436 PRPH_ASSIGN, 2437 PRPH_SETBIT, 2438 PRPH_CLEARBIT, 2439 2440 INDIRECT_ASSIGN, 2441 INDIRECT_SETBIT, 2442 INDIRECT_CLEARBIT, 2443 2444 PRPH_BLOCKBIT, 2445}; 2446 2447/** 2448 * struct iwx_fw_dbg_reg_op - an operation on a register 2449 * 2450 * @op: &enum iwx_fw_dbg_reg_operator 2451 * @addr: offset of the register 2452 * @val: value 2453 */ 2454struct iwx_fw_dbg_reg_op { 2455 uint8_t op; 2456 uint8_t reserved[3]; 2457 uint32_t addr; 2458 uint32_t val; 2459} __packed; 2460 2461/** 2462 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes 2463 * 2464 * @SMEM_MODE: monitor stores the data in SMEM 2465 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM 2466 * @MARBH_MODE: monitor stores the data in MARBH buffer 2467 * @MIPI_MODE: monitor outputs the data through the MIPI interface 2468 */ 2469enum iwx_fw_dbg_monitor_mode { 2470 SMEM_MODE = 0, 2471 EXTERNAL_MODE = 1, 2472 MARBH_MODE = 2, 2473 MIPI_MODE = 3, 2474}; 2475 2476/** 2477 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments 2478 * 2479 * @data_type: the memory segment type to record 2480 * @ofs: the memory segment offset 2481 * @len: the memory segment length, in bytes 2482 * 2483 * This parses IWX_UCODE_TLV_FW_MEM_SEG 2484 */ 2485struct iwx_fw_dbg_mem_seg_tlv { 2486 uint32_t data_type; 2487 uint32_t ofs; 2488 uint32_t len; 2489} __packed; 2490 2491/** 2492 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data 2493 * 2494 * @version: version of the TLV - currently 0 2495 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode 2496 * @size_power: buffer size will be 2^(size_power + 11) 2497 * @base_reg: addr of the base addr register (PRPH) 2498 * @end_reg: addr of the end addr register (PRPH) 2499 * @write_ptr_reg: the addr of the reg of the write pointer 2500 * @wrap_count: the addr of the reg of the wrap_count 2501 * @base_shift: shift right of the base addr reg 2502 * @end_shift: shift right of the end addr reg 2503 * @reg_ops: array of registers operations 2504 * 2505 * This parses IWX_UCODE_TLV_FW_DBG_DEST 2506 */ 2507struct iwx_fw_dbg_dest_tlv_v1 { 2508 uint8_t version; 2509 uint8_t monitor_mode; 2510 uint8_t size_power; 2511 uint8_t reserved; 2512 uint32_t base_reg; 2513 uint32_t end_reg; 2514 uint32_t write_ptr_reg; 2515 uint32_t wrap_count; 2516 uint8_t base_shift; 2517 uint8_t end_shift; 2518 struct iwx_fw_dbg_reg_op reg_ops[0]; 2519} __packed; 2520 2521/* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */ 2522#define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000 2523/* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */ 2524#define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff 2525/* The smem buffer chunks are in units of 256 bits */ 2526#define IWX_M2S_UNIT_SIZE 0x100 2527 2528struct iwx_fw_dbg_dest_tlv { 2529 uint8_t version; 2530 uint8_t monitor_mode; 2531 uint8_t size_power; 2532 uint8_t reserved; 2533 uint32_t cfg_reg; 2534 uint32_t write_ptr_reg; 2535 uint32_t wrap_count; 2536 uint8_t base_shift; 2537 uint8_t size_shift; 2538 struct iwx_fw_dbg_reg_op reg_ops[0]; 2539} __packed; 2540 2541struct iwx_fw_dbg_conf_hcmd { 2542 uint8_t id; 2543 uint8_t reserved; 2544 uint16_t len; 2545 uint8_t data[0]; 2546} __packed; 2547 2548/** 2549 * enum iwx_fw_dbg_trigger_mode - triggers functionalities 2550 * 2551 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism 2552 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data 2553 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to 2554 * collect only monitor data 2555 */ 2556enum iwx_fw_dbg_trigger_mode { 2557 IWX_FW_DBG_TRIGGER_START = (1 << 0), 2558 IWX_FW_DBG_TRIGGER_STOP = (1 << 1), 2559 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2), 2560}; 2561 2562/** 2563 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers 2564 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart 2565 */ 2566enum iwx_fw_dbg_trigger_flags { 2567 IWX_FW_DBG_FORCE_RESTART = (1 << 0), 2568}; 2569 2570/** 2571 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger 2572 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type 2573 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode 2574 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode 2575 * @IWX_FW_DBG_CONF_VIF_AP: AP mode 2576 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode 2577 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode 2578 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device 2579 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device 2580 */ 2581enum iwx_fw_dbg_trigger_vif_type { 2582 IWX_FW_DBG_CONF_VIF_ANY = 0, 2583 IWX_FW_DBG_CONF_VIF_IBSS = 1, 2584 IWX_FW_DBG_CONF_VIF_STATION = 2, 2585 IWX_FW_DBG_CONF_VIF_AP = 3, 2586 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8, 2587 IWX_FW_DBG_CONF_VIF_P2P_GO = 9, 2588 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10, 2589 IWX_FW_DBG_CONF_VIF_NAN = 12, 2590}; 2591 2592/** 2593 * enum iwl_fw_dbg_trigger - triggers available 2594 * 2595 * @FW_DBG_TRIGGER_USER: trigger log collection by user 2596 * This should not be defined as a trigger to the driver, but a value the 2597 * driver should set to indicate that the trigger was initiated by the 2598 * user. 2599 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts 2600 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are 2601 * missed. 2602 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch. 2603 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a 2604 * command response or a notification. 2605 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event. 2606 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold. 2607 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon 2608 * goes below a threshold. 2609 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang 2610 * detection. 2611 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related 2612 * events. 2613 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events. 2614 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a 2615 * threshold. 2616 * @FW_DBG_TDLS: trigger log collection upon TDLS related events. 2617 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when 2618 * the firmware sends a tx reply. 2619 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space 2620 * request. 2621 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts 2622 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure 2623 * in the driver. 2624 */ 2625enum iwx_fw_dbg_trigger { 2626 IWX_FW_DBG_TRIGGER_INVALID = 0, 2627 IWX_FW_DBG_TRIGGER_USER, 2628 IWX_FW_DBG_TRIGGER_FW_ASSERT, 2629 IWX_FW_DBG_TRIGGER_MISSED_BEACONS, 2630 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH, 2631 IWX_FW_DBG_TRIGGER_FW_NOTIF, 2632 IWX_FW_DBG_TRIGGER_MLME, 2633 IWX_FW_DBG_TRIGGER_STATS, 2634 IWX_FW_DBG_TRIGGER_RSSI, 2635 IWX_FW_DBG_TRIGGER_TXQ_TIMERS, 2636 IWX_FW_DBG_TRIGGER_TIME_EVENT, 2637 IWX_FW_DBG_TRIGGER_BA, 2638 IWX_FW_DBG_TRIGGER_TX_LATENCY, 2639 IWX_FW_DBG_TRIGGER_TDLS, 2640 IWX_FW_DBG_TRIGGER_TX_STATUS, 2641 IWX_FW_DBG_TRIGGER_USER_EXTENDED, 2642 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT, 2643 IWX_FW_DBG_TRIGGER_DRIVER, 2644 2645 /* must be last */ 2646 IWX_FW_DBG_TRIGGER_MAX, 2647}; 2648 2649 2650/** 2651 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger 2652 * @id: &enum iwx_fw_dbg_trigger 2653 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type 2654 * @stop_conf_ids: bitmap of configurations this trigger relates to. 2655 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding 2656 * to the currently running configuration is set, the data should be 2657 * collected. 2658 * @stop_delay: how many milliseconds to wait before collecting the data 2659 * after the STOP trigger fires. 2660 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both 2661 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what 2662 * configuration should be applied when the triggers kicks in. 2663 * @occurrences: number of occurrences. 0 means the trigger will never fire. 2664 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this 2665 * trigger in which another occurrence should be ignored. 2666 * @flags: &enum iwx_fw_dbg_trigger_flags 2667 */ 2668struct iwx_fw_dbg_trigger_tlv { 2669 uint32_t id; 2670 uint32_t vif_type; 2671 uint32_t stop_conf_ids; 2672 uint32_t stop_delay; 2673 uint8_t mode; 2674 uint8_t start_conf_id; 2675 uint16_t occurrences; 2676 uint16_t trig_dis_ms; 2677 uint8_t flags; 2678 uint8_t reserved[5]; 2679 2680 uint8_t data[0]; 2681} __packed; 2682 2683#define IWX_FW_DBG_START_FROM_ALIVE 0 2684#define IWX_FW_DBG_CONF_MAX 32 2685#define IWX_FW_DBG_INVALID 0xff 2686 2687/** 2688 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons 2689 * @stop_consec_missed_bcon: stop recording if threshold is crossed. 2690 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed. 2691 * @start_consec_missed_bcon: start recording if threshold is crossed. 2692 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed. 2693 * @reserved1: reserved 2694 * @reserved2: reserved 2695 */ 2696struct iwx_fw_dbg_trigger_missed_bcon { 2697 uint32_t stop_consec_missed_bcon; 2698 uint32_t stop_consec_missed_bcon_since_rx; 2699 uint32_t reserved2[2]; 2700 uint32_t start_consec_missed_bcon; 2701 uint32_t start_consec_missed_bcon_since_rx; 2702 uint32_t reserved1[2]; 2703} __packed; 2704 2705/** 2706 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW. 2707 * cmds: the list of commands to trigger the collection on 2708 */ 2709struct iwx_fw_dbg_trigger_cmd { 2710 struct cmd { 2711 uint8_t cmd_id; 2712 uint8_t group_id; 2713 } __packed cmds[16]; 2714} __packed; 2715 2716/** 2717 * iwx_fw_dbg_trigger_stats - configures trigger for statistics 2718 * @stop_offset: the offset of the value to be monitored 2719 * @stop_threshold: the threshold above which to collect 2720 * @start_offset: the offset of the value to be monitored 2721 * @start_threshold: the threshold above which to start recording 2722 */ 2723struct iwx_fw_dbg_trigger_stats { 2724 uint32_t stop_offset; 2725 uint32_t stop_threshold; 2726 uint32_t start_offset; 2727 uint32_t start_threshold; 2728} __packed; 2729 2730/** 2731 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI 2732 * @rssi: RSSI value to trigger at 2733 */ 2734struct iwx_fw_dbg_trigger_low_rssi { 2735 uint32_t rssi; 2736} __packed; 2737 2738/** 2739 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events 2740 * @stop_auth_denied: number of denied authentication to collect 2741 * @stop_auth_timeout: number of authentication timeout to collect 2742 * @stop_rx_deauth: number of Rx deauth before to collect 2743 * @stop_tx_deauth: number of Tx deauth before to collect 2744 * @stop_assoc_denied: number of denied association to collect 2745 * @stop_assoc_timeout: number of association timeout to collect 2746 * @stop_connection_loss: number of connection loss to collect 2747 * @start_auth_denied: number of denied authentication to start recording 2748 * @start_auth_timeout: number of authentication timeout to start recording 2749 * @start_rx_deauth: number of Rx deauth to start recording 2750 * @start_tx_deauth: number of Tx deauth to start recording 2751 * @start_assoc_denied: number of denied association to start recording 2752 * @start_assoc_timeout: number of association timeout to start recording 2753 * @start_connection_loss: number of connection loss to start recording 2754 */ 2755struct iwx_fw_dbg_trigger_mlme { 2756 uint8_t stop_auth_denied; 2757 uint8_t stop_auth_timeout; 2758 uint8_t stop_rx_deauth; 2759 uint8_t stop_tx_deauth; 2760 2761 uint8_t stop_assoc_denied; 2762 uint8_t stop_assoc_timeout; 2763 uint8_t stop_connection_loss; 2764 uint8_t reserved; 2765 2766 uint8_t start_auth_denied; 2767 uint8_t start_auth_timeout; 2768 uint8_t start_rx_deauth; 2769 uint8_t start_tx_deauth; 2770 2771 uint8_t start_assoc_denied; 2772 uint8_t start_assoc_timeout; 2773 uint8_t start_connection_loss; 2774 uint8_t reserved2; 2775} __packed; 2776 2777/** 2778 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer 2779 * @command_queue: timeout for the command queue in ms 2780 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms 2781 * @softap: timeout for the queues of a softAP in ms 2782 * @p2p_go: timeout for the queues of a P2P GO in ms 2783 * @p2p_client: timeout for the queues of a P2P client in ms 2784 * @p2p_device: timeout for the queues of a P2P device in ms 2785 * @ibss: timeout for the queues of an IBSS in ms 2786 * @tdls: timeout for the queues of a TDLS station in ms 2787 */ 2788struct iwx_fw_dbg_trigger_txq_timer { 2789 uint32_t command_queue; 2790 uint32_t bss; 2791 uint32_t softap; 2792 uint32_t p2p_go; 2793 uint32_t p2p_client; 2794 uint32_t p2p_device; 2795 uint32_t ibss; 2796 uint32_t tdls; 2797 uint32_t reserved[4]; 2798} __packed; 2799 2800/** 2801 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger 2802 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a 2803 * trigger each time a time event notification that relates to time event 2804 * id with one of the actions in the bitmap is received and 2805 * BIT(notif->status) is set in status_bitmap. 2806 * 2807 */ 2808struct iwx_fw_dbg_trigger_time_event { 2809 struct { 2810 uint32_t id; 2811 uint32_t action_bitmap; 2812 uint32_t status_bitmap; 2813 } __packed time_events[16]; 2814} __packed; 2815 2816/** 2817 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger 2818 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur 2819 * when an Rx BlockAck session is started. 2820 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2821 * when an Rx BlockAck session is stopped. 2822 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur 2823 * when a Tx BlockAck session is started. 2824 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2825 * when a Tx BlockAck session is stopped. 2826 * rx_bar: tid bitmap to configure on what tid the trigger should occur 2827 * when a BAR is received (for a Tx BlockAck session). 2828 * tx_bar: tid bitmap to configure on what tid the trigger should occur 2829 * when a BAR is send (for an Rx BlocAck session). 2830 * frame_timeout: tid bitmap to configure on what tid the trigger should occur 2831 * when a frame times out in the reordering buffer. 2832 */ 2833struct iwx_fw_dbg_trigger_ba { 2834 uint16_t rx_ba_start; 2835 uint16_t rx_ba_stop; 2836 uint16_t tx_ba_start; 2837 uint16_t tx_ba_stop; 2838 uint16_t rx_bar; 2839 uint16_t tx_bar; 2840 uint16_t frame_timeout; 2841} __packed; 2842 2843/** 2844 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger 2845 * @thrshold: the wanted threshold. 2846 * @tid_bitmap: the tid to apply the threshold on 2847 * @mode: recording mode (Internal buffer or continues recording) 2848 * @window: the size of the window before collecting. 2849 * @reserved: reserved. 2850 */ 2851struct iwx_fw_dbg_trigger_tx_latency { 2852 uint32_t thrshold; 2853 uint16_t tid_bitmap; 2854 uint16_t mode; 2855 uint32_t window; 2856 uint32_t reserved[4]; 2857} __packed; 2858 2859/** 2860 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events. 2861 * @action_bitmap: the TDLS action to trigger the collection upon 2862 * @peer_mode: trigger on specific peer or all 2863 * @peer: the TDLS peer to trigger the collection on 2864 */ 2865struct iwx_fw_dbg_trigger_tdls { 2866 uint8_t action_bitmap; 2867 uint8_t peer_mode; 2868 uint8_t peer[ETHER_ADDR_LEN]; 2869 uint8_t reserved[4]; 2870} __packed; 2871 2872/** 2873 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response 2874 * status. 2875 * @statuses: the list of statuses to trigger the collection on 2876 */ 2877struct iwx_fw_dbg_trigger_tx_status { 2878 struct tx_status { 2879 uint8_t status; 2880 uint8_t reserved[3]; 2881 } __packed statuses[16]; 2882 uint32_t reserved[2]; 2883} __packed; 2884 2885/** 2886 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration. 2887 * @id: conf id 2888 * @usniffer: should the uSniffer image be used 2889 * @num_of_hcmds: how many HCMDs to send are present here 2890 * @hcmd: a variable length host command to be sent to apply the configuration. 2891 * If there is more than one HCMD to send, they will appear one after the 2892 * other and be sent in the order that they appear in. 2893 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to 2894 * %IWX_FW_DBG_CONF_MAX configuration per run. 2895 */ 2896struct iwx_fw_dbg_conf_tlv { 2897 uint8_t id; 2898 uint8_t usniffer; 2899 uint8_t reserved; 2900 uint8_t num_of_hcmds; 2901 struct iwx_fw_dbg_conf_hcmd hcmd; 2902} __packed; 2903 2904#define IWX_FW_CMD_VER_UNKNOWN 99 2905 2906/** 2907 * struct iwx_fw_cmd_version - firmware command version entry 2908 * @cmd: command ID 2909 * @group: group ID 2910 * @cmd_ver: command version 2911 * @notif_ver: notification version 2912 */ 2913struct iwx_fw_cmd_version { 2914 uint8_t cmd; 2915 uint8_t group; 2916 uint8_t cmd_ver; 2917 uint8_t notif_ver; 2918} __packed; 2919 2920/* Common PHY, MAC and Bindings definitions */ 2921 2922#define IWX_MAX_MACS_IN_BINDING (3) 2923#define IWX_MAX_BINDINGS (4) 2924#define IWX_AUX_BINDING_INDEX (3) 2925#define IWX_MAX_PHYS (4) 2926 2927/* Used to extract ID and color from the context dword */ 2928#define IWX_FW_CTXT_ID_POS (0) 2929#define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS) 2930#define IWX_FW_CTXT_COLOR_POS (8) 2931#define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS) 2932#define IWX_FW_CTXT_INVALID (0xffffffff) 2933 2934#define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\ 2935 (_color << IWX_FW_CTXT_COLOR_POS)) 2936 2937/* Possible actions on PHYs, MACs and Bindings */ 2938#define IWX_FW_CTXT_ACTION_STUB 0 2939#define IWX_FW_CTXT_ACTION_ADD 1 2940#define IWX_FW_CTXT_ACTION_MODIFY 2 2941#define IWX_FW_CTXT_ACTION_REMOVE 3 2942#define IWX_FW_CTXT_ACTION_NUM 4 2943/* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2944 2945/* Time Events */ 2946 2947/* Time Event types, according to MAC type */ 2948 2949/* BSS Station Events */ 2950#define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2951#define IWX_TE_BSS_STA_ASSOC 1 2952#define IWX_TE_BSS_EAP_DHCP_PROT 2 2953#define IWX_TE_BSS_QUIET_PERIOD 3 2954 2955/* P2P Device Events */ 2956#define IWX_TE_P2P_DEVICE_DISCOVERABLE 4 2957#define IWX_TE_P2P_DEVICE_LISTEN 5 2958#define IWX_TE_P2P_DEVICE_ACTION_SCAN 6 2959#define IWX_TE_P2P_DEVICE_FULL_SCAN 7 2960 2961/* P2P Client Events */ 2962#define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2963#define IWX_TE_P2P_CLIENT_ASSOC 9 2964#define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10 2965 2966/* P2P GO Events */ 2967#define IWX_TE_P2P_GO_ASSOC_PROT 11 2968#define IWX_TE_P2P_GO_REPETITIVE_NOA 12 2969#define IWX_TE_P2P_GO_CT_WINDOW 13 2970 2971/* WiDi Sync Events */ 2972#define IWX_TE_WIDI_TX_SYNC 14 2973 2974/* Time event - defines for command API */ 2975 2976/** 2977 * DOC: Time Events - what is it? 2978 * 2979 * Time Events are a fw feature that allows the driver to control the presence 2980 * of the device on the channel. Since the fw supports multiple channels 2981 * concurrently, the fw may choose to jump to another channel at any time. 2982 * In order to make sure that the fw is on a specific channel at a certain time 2983 * and for a certain duration, the driver needs to issue a time event. 2984 * 2985 * The simplest example is for BSS association. The driver issues a time event, 2986 * waits for it to start, and only then tells mac80211 that we can start the 2987 * association. This way, we make sure that the association will be done 2988 * smoothly and won't be interrupted by channel switch decided within the fw. 2989 */ 2990 2991 /** 2992 * DOC: The flow against the fw 2993 * 2994 * When the driver needs to make sure we are in a certain channel, at a certain 2995 * time and for a certain duration, it sends a Time Event. The flow against the 2996 * fw goes like this: 2997 * 1) Driver sends a TIME_EVENT_CMD to the fw 2998 * 2) Driver gets the response for that command. This response contains the 2999 * Unique ID (UID) of the event. 3000 * 3) The fw sends notification when the event starts. 3001 * 3002 * Of course the API provides various options that allow to cover parameters 3003 * of the flow. 3004 * What is the duration of the event? 3005 * What is the start time of the event? 3006 * Is there an end-time for the event? 3007 * How much can the event be delayed? 3008 * Can the event be split? 3009 * If yes what is the maximal number of chunks? 3010 * etc... 3011 */ 3012 3013/* 3014 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 3015 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 3016 * the first fragment is scheduled. 3017 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 3018 * the first 2 fragments are scheduled. 3019 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 3020 * number of fragments are valid. 3021 * 3022 * Other than the constant defined above, specifying a fragmentation value 'x' 3023 * means that the event can be fragmented but only the first 'x' will be 3024 * scheduled. 3025 */ 3026#define IWX_TE_V2_FRAG_NONE 0 3027#define IWX_TE_V2_FRAG_SINGLE 1 3028#define IWX_TE_V2_FRAG_DUAL 2 3029#define IWX_TE_V2_FRAG_MAX 0xfe 3030#define IWX_TE_V2_FRAG_ENDLESS 0xff 3031 3032/* Repeat the time event endlessly (until removed) */ 3033#define IWX_TE_V2_REPEAT_ENDLESS 0xff 3034/* If a Time Event has bounded repetitions, this is the maximal value */ 3035#define IWX_TE_V2_REPEAT_MAX 0xfe 3036 3037#define IWX_TE_V2_PLACEMENT_POS 12 3038#define IWX_TE_V2_ABSENCE_POS 15 3039 3040/* Time event policy values 3041 * A notification (both event and fragment) includes a status indicating weather 3042 * the FW was able to schedule the event or not. For fragment start/end 3043 * notification the status is always success. There is no start/end fragment 3044 * notification for monolithic events. 3045 * 3046 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 3047 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 3048 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 3049 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 3050 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 3051 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 3052 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 3053 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 3054 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 3055 * @IWX_TE_V2_DEP_OTHER: depends on another time event 3056 * @IWX_TE_V2_DEP_TSF: depends on a specific time 3057 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of the same MAC 3058 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event. 3059 */ 3060#define IWX_TE_V2_DEFAULT_POLICY 0x0 3061 3062/* notifications (event start/stop, fragment start/stop) */ 3063#define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 3064#define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 3065#define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 3066#define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 3067 3068#define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 3069#define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 3070#define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 3071#define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 3072#define IWX_T2_V2_START_IMMEDIATELY (1 << 11) 3073 3074#define IWX_TE_V2_NOTIF_MSK 0xff 3075 3076/* placement characteristics */ 3077#define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS) 3078#define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1)) 3079#define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2)) 3080 3081/* are we present or absent during the Time Event. */ 3082#define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS) 3083 3084/** 3085 * struct iwx_time_event_cmd_api - configuring Time Events 3086 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 3087 * with version 1. determined by IWX_UCODE_TLV_FLAGS) 3088 * ( IWX_TIME_EVENT_CMD = 0x29 ) 3089 * @id_and_color: ID and color of the relevant MAC 3090 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3091 * @id: this field has two meanings, depending on the action: 3092 * If the action is ADD, then it means the type of event to add. 3093 * For all other actions it is the unique event ID assigned when the 3094 * event was added by the FW. 3095 * @apply_time: When to start the Time Event (in GP2) 3096 * @max_delay: maximum delay to event's start (apply time), in TU 3097 * @depends_on: the unique ID of the event we depend on (if any) 3098 * @interval: interval between repetitions, in TU 3099 * @duration: duration of event in TU 3100 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS 3101 * @max_frags: maximal number of fragments the Time Event can be divided to 3102 * @policy: defines whether uCode shall notify the host or other uCode modules 3103 * on event and/or fragment start and/or end 3104 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF 3105 * IWX_TE_EVENT_SOCIOPATHIC 3106 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_* 3107 */ 3108struct iwx_time_event_cmd { 3109 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3110 uint32_t id_and_color; 3111 uint32_t action; 3112 uint32_t id; 3113 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 3114 uint32_t apply_time; 3115 uint32_t max_delay; 3116 uint32_t depends_on; 3117 uint32_t interval; 3118 uint32_t duration; 3119 uint8_t repeat; 3120 uint8_t max_frags; 3121 uint16_t policy; 3122} __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 3123 3124/** 3125 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd 3126 * @status: bit 0 indicates success, all others specify errors 3127 * @id: the Time Event type 3128 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 3129 * @id_and_color: ID and color of the relevant MAC 3130 */ 3131struct iwx_time_event_resp { 3132 uint32_t status; 3133 uint32_t id; 3134 uint32_t unique_id; 3135 uint32_t id_and_color; 3136} __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 3137 3138/** 3139 * struct iwx_time_event_notif - notifications of time event start/stop 3140 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a ) 3141 * @timestamp: action timestamp in GP2 3142 * @session_id: session's unique id 3143 * @unique_id: unique id of the Time Event itself 3144 * @id_and_color: ID and color of the relevant MAC 3145 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END 3146 * @status: true if scheduled, false otherwise (not executed) 3147 */ 3148struct iwx_time_event_notif { 3149 uint32_t timestamp; 3150 uint32_t session_id; 3151 uint32_t unique_id; 3152 uint32_t id_and_color; 3153 uint32_t action; 3154 uint32_t status; 3155} __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 3156 3157/** 3158 * enum iwx_session_prot_conf_id - session protection's configurations 3159 * @SESSION_PROTECT_CONF_ASSOC: Start a session protection for association. 3160 * The firmware will allocate two events. 3161 * Valid for BSS_STA and P2P_STA. 3162 * * A rather short event that can't be fragmented and with a very 3163 * high priority. If every goes well (99% of the cases) the 3164 * association should complete within this first event. During 3165 * that event, no other activity will happen in the firmware, 3166 * which is why it can't be too long. 3167 * The length of this event is hard-coded in the firmware: 300TUs. 3168 * * Another event which can be much longer (its duration is 3169 * configurable by the driver) which has a slightly lower 3170 * priority and that can be fragmented allowing other activities 3171 * to run while this event is running. 3172 * The firmware will automatically remove both events once the driver sets 3173 * the BSS MAC as associated. Neither of the events will be removed 3174 * for the P2P_STA MAC. 3175 * Only the duration is configurable for this protection. 3176 * @SESSION_PROTECT_CONF_GO_CLIENT_ASSOC: not used 3177 * @SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV: Schedule the P2P Device to be in 3178 * listen mode. Will be fragmented. Valid only on the P2P Device MAC. 3179 * Valid only on the P2P Device MAC. The firmware will take into account 3180 * the duration, the interval and the repetition count. 3181 * @SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION: Schedule the P2P Device to be be 3182 * able to run the GO Negotiation. Will not be fragmented and not 3183 * repetitive. Valid only on the P2P Device MAC. Only the duration will 3184 * be taken into account. 3185 * @SESSION_PROTECT_CONF_MAX_ID: not used 3186 */ 3187enum iwx_session_prot_conf_id { 3188 IWX_SESSION_PROTECT_CONF_ASSOC, 3189 IWX_SESSION_PROTECT_CONF_GO_CLIENT_ASSOC, 3190 IWX_SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV, 3191 IWX_SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION, 3192 IWX_SESSION_PROTECT_CONF_MAX_ID, 3193}; /* SESSION_PROTECTION_CONF_ID_E_VER_1 */ 3194 3195/** 3196 * struct iwx_session_prot_cmd - configure a session protection 3197 * @id_and_color: the id and color of the mac for which this session protection 3198 * is sent 3199 * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE 3200 * @conf_id: see &enum iwx_mvm_session_prot_conf_id 3201 * @duration_tu: the duration of the whole protection in TUs. 3202 * @repetition_count: not used 3203 * @interval: not used 3204 * 3205 * Note: the session protection will always be scheduled to start as 3206 * early as possible, but the maximum delay is configuration dependent. 3207 * The firmware supports only one concurrent session protection per vif. 3208 * Adding a new session protection will remove any currently running session. 3209 */ 3210struct iwx_session_prot_cmd { 3211 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */ 3212 uint32_t id_and_color; 3213 uint32_t action; 3214 uint32_t conf_id; 3215 uint32_t duration_tu; 3216 uint32_t repetition_count; 3217 uint32_t interval; 3218} __packed; /* SESSION_PROTECTION_CMD_API_S_VER_1 */ 3219 3220/** 3221 * struct iwx_session_prot_notif - session protection started / ended 3222 * @mac_id: the mac id for which the session protection started / ended 3223 * @status: 1 means success, 0 means failure 3224 * @start: 1 means the session protection started, 0 means it ended 3225 * @conf_id: see &enum iwx_mvm_session_prot_conf_id 3226 * 3227 * Note that any session protection will always get two notifications: start 3228 * and end even the firmware could not schedule it. 3229 */ 3230struct iwx_session_prot_notif { 3231 uint32_t mac_id; 3232 uint32_t status; 3233 uint32_t start; 3234 uint32_t conf_id; 3235} __packed; /* SESSION_PROTECTION_NOTIFICATION_API_S_VER_2 */ 3236 3237 3238/* Bindings and Time Quota */ 3239 3240/** 3241 * struct iwx_binding_cmd - configuring bindings 3242 * ( IWX_BINDING_CONTEXT_CMD = 0x2b ) 3243 * @id_and_color: ID and color of the relevant Binding 3244 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3245 * @macs: array of MAC id and colors which belong to the binding 3246 * @phy: PHY id and color which belongs to the binding 3247 * @lmac_id: the lmac id the binding belongs to 3248 */ 3249struct iwx_binding_cmd { 3250 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3251 uint32_t id_and_color; 3252 uint32_t action; 3253 /* IWX_BINDING_DATA_API_S_VER_1 */ 3254 uint32_t macs[IWX_MAX_MACS_IN_BINDING]; 3255 uint32_t phy; 3256 uint32_t lmac_id; 3257} __packed; /* IWX_BINDING_CMD_API_S_VER_2 */ 3258 3259#define IWX_LMAC_24G_INDEX 0 3260#define IWX_LMAC_5G_INDEX 1 3261 3262/* The maximal number of fragments in the FW's schedule session */ 3263#define IWX_MAX_QUOTA 128 3264 3265/** 3266 * struct iwx_time_quota_data - configuration of time quota per binding 3267 * @id_and_color: ID and color of the relevant Binding 3268 * @quota: absolute time quota in TU. The scheduler will try to divide the 3269 * remaining quota (after Time Events) according to this quota. 3270 * @max_duration: max uninterrupted context duration in TU 3271 */ 3272struct iwx_time_quota_data { 3273 uint32_t id_and_color; 3274 uint32_t quota; 3275 uint32_t max_duration; 3276} __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */ 3277 3278/** 3279 * struct iwx_time_quota_cmd - configuration of time quota between bindings 3280 * ( IWX_TIME_QUOTA_CMD = 0x2c ) 3281 * @quotas: allocations per binding 3282 */ 3283struct iwx_time_quota_cmd { 3284 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS]; 3285} __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 3286 3287 3288/* PHY context */ 3289 3290/* Supported bands */ 3291#define IWX_PHY_BAND_5 (0) 3292#define IWX_PHY_BAND_24 (1) 3293 3294/* Supported channel width, vary if there is VHT support */ 3295#define IWX_PHY_VHT_CHANNEL_MODE20 (0x0) 3296#define IWX_PHY_VHT_CHANNEL_MODE40 (0x1) 3297#define IWX_PHY_VHT_CHANNEL_MODE80 (0x2) 3298#define IWX_PHY_VHT_CHANNEL_MODE160 (0x3) 3299 3300/* 3301 * Control channel position: 3302 * For legacy set bit means upper channel, otherwise lower. 3303 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 3304 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 3305 * center_freq 3306 * | 3307 * 40Mhz |_______|_______| 3308 * 80Mhz |_______|_______|_______|_______| 3309 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 3310 * code 011 010 001 000 | 100 101 110 111 3311 */ 3312#define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0) 3313#define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1) 3314#define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2) 3315#define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3) 3316#define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 3317#define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 3318#define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 3319#define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 3320 3321/* 3322 * @band: IWX_PHY_BAND_* 3323 * @channel: channel number 3324 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3325 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3326 */ 3327struct iwx_fw_channel_info_v1 { 3328 uint8_t band; 3329 uint8_t channel; 3330 uint8_t width; 3331 uint8_t ctrl_pos; 3332} __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 3333 3334/* 3335 * struct iwx_fw_channel_info - channel information 3336 * 3337 * @channel: channel number 3338 * @band: PHY_BAND_* 3339 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3340 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3341 * @reserved: for future use and alignment 3342 */ 3343struct iwx_fw_channel_info { 3344 uint32_t channel; 3345 uint8_t band; 3346 uint8_t width; 3347 uint8_t ctrl_pos; 3348 uint8_t reserved; 3349} __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ 3350 3351#define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 3352#define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 3353 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS) 3354#define IWX_PHY_RX_CHAIN_VALID_POS (1) 3355#define IWX_PHY_RX_CHAIN_VALID_MSK \ 3356 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS) 3357#define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4) 3358#define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \ 3359 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS) 3360#define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 3361#define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 3362 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 3363#define IWX_PHY_RX_CHAIN_CNT_POS (10) 3364#define IWX_PHY_RX_CHAIN_CNT_MSK \ 3365 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS) 3366#define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12) 3367#define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \ 3368 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS) 3369#define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 3370#define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 3371 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS) 3372 3373/* TODO: fix the value, make it depend on firmware at runtime? */ 3374#define IWX_NUM_PHY_CTX 3 3375 3376/** 3377 * struct iwl_phy_context_cmd - config of the PHY context 3378 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 3379 * @id_and_color: ID and color of the relevant Binding 3380 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3381 * @lmac_id: the lmac id the phy context belongs to 3382 * @ci: channel info 3383 * @rxchain_info: ??? 3384 * @dsp_cfg_flags: set to 0 3385 * @reserved: reserved to align to 64 bit 3386 */ 3387struct iwx_phy_context_cmd_uhb { 3388 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3389 uint32_t id_and_color; 3390 uint32_t action; 3391 /* PHY_CONTEXT_DATA_API_S_VER_3 */ 3392 struct iwx_fw_channel_info ci; 3393 uint32_t lmac_id; 3394 uint32_t rxchain_info; 3395 uint32_t dsp_cfg_flags; 3396 uint32_t reserved; 3397} __packed; /* PHY_CONTEXT_CMD_API_VER_3 */ 3398struct iwx_phy_context_cmd { 3399 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3400 uint32_t id_and_color; 3401 uint32_t action; 3402 /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */ 3403 struct iwx_fw_channel_info_v1 ci; 3404 uint32_t lmac_id; 3405 uint32_t rxchain_info; /* reserved in _VER_4 */ 3406 uint32_t dsp_cfg_flags; 3407 uint32_t reserved; 3408} __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */ 3409 3410/* TODO: complete missing documentation */ 3411/** 3412 * struct iwx_phy_context_cmd - config of the PHY context 3413 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 3414 * @id_and_color: ID and color of the relevant Binding 3415 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3416 * @apply_time: 0 means immediate apply and context switch. 3417 * other value means apply new params after X usecs 3418 * @tx_param_color: ??? 3419 * @channel_info: 3420 * @txchain_info: ??? 3421 * @rxchain_info: ??? 3422 * @acquisition_data: ??? 3423 * @dsp_cfg_flags: set to 0 3424 */ 3425/* 3426 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 3427 * the size of fw_channel_info from v1 to v2. 3428 * To keep things simple we define two versions of this struct, and both 3429 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 3430 * magic with pointers to struct members instead.) 3431 */ 3432/* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 3433struct iwx_phy_context_cmd_uhb_v1 { 3434 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3435 uint32_t id_and_color; 3436 uint32_t action; 3437 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 3438 uint32_t apply_time; 3439 uint32_t tx_param_color; 3440 struct iwx_fw_channel_info ci; 3441 uint32_t txchain_info; 3442 uint32_t rxchain_info; 3443 uint32_t acquisition_data; 3444 uint32_t dsp_cfg_flags; 3445} __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 3446/* This version must be used otherwise: */ 3447struct iwx_phy_context_cmd_v1 { 3448 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3449 uint32_t id_and_color; 3450 uint32_t action; 3451 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 3452 uint32_t apply_time; 3453 uint32_t tx_param_color; 3454 struct iwx_fw_channel_info_v1 ci; 3455 uint32_t txchain_info; 3456 uint32_t rxchain_info; 3457 uint32_t acquisition_data; 3458 uint32_t dsp_cfg_flags; 3459} __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 3460 3461 3462#define IWX_RX_INFO_PHY_CNT 8 3463#define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1 3464#define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 3465#define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 3466#define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 3467#define IWX_RX_INFO_ENERGY_ANT_A_POS 0 3468#define IWX_RX_INFO_ENERGY_ANT_B_POS 8 3469#define IWX_RX_INFO_ENERGY_ANT_C_POS 16 3470 3471#define IWX_RX_INFO_AGC_IDX 1 3472#define IWX_RX_INFO_RSSI_AB_IDX 2 3473#define IWX_OFDM_AGC_A_MSK 0x0000007f 3474#define IWX_OFDM_AGC_A_POS 0 3475#define IWX_OFDM_AGC_B_MSK 0x00003f80 3476#define IWX_OFDM_AGC_B_POS 7 3477#define IWX_OFDM_AGC_CODE_MSK 0x3fe00000 3478#define IWX_OFDM_AGC_CODE_POS 20 3479#define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff 3480#define IWX_OFDM_RSSI_A_POS 0 3481#define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00 3482#define IWX_OFDM_RSSI_ALLBAND_A_POS 8 3483#define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000 3484#define IWX_OFDM_RSSI_B_POS 16 3485#define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 3486#define IWX_OFDM_RSSI_ALLBAND_B_POS 24 3487 3488/** 3489 * struct iwx_rx_phy_info - phy info 3490 * (IWX_REPLY_RX_PHY_CMD = 0xc0) 3491 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 3492 * @cfg_phy_cnt: configurable DSP phy data byte count 3493 * @stat_id: configurable DSP phy data set ID 3494 * @reserved1: 3495 * @system_timestamp: GP2 at on air rise 3496 * @timestamp: TSF at on air rise 3497 * @beacon_time_stamp: beacon at on-air rise 3498 * @phy_flags: general phy flags: band, modulation, ... 3499 * @channel: channel number 3500 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 3501 * @rate_n_flags: IWX_RATE_MCS_* 3502 * @byte_count: frame's byte-count 3503 * @frame_time: frame's time on the air, based on byte count and frame rate 3504 * calculation 3505 * @mac_active_msk: what MACs were active when the frame was received 3506 * 3507 * Before each Rx, the device sends this data. It contains PHY information 3508 * about the reception of the packet. 3509 */ 3510struct iwx_rx_phy_info { 3511 uint8_t non_cfg_phy_cnt; 3512 uint8_t cfg_phy_cnt; 3513 uint8_t stat_id; 3514 uint8_t reserved1; 3515 uint32_t system_timestamp; 3516 uint64_t timestamp; 3517 uint32_t beacon_time_stamp; 3518 uint16_t phy_flags; 3519#define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 3520 uint16_t channel; 3521 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT]; 3522 uint32_t rate_n_flags; 3523 uint32_t byte_count; 3524 uint16_t mac_active_msk; 3525 uint16_t frame_time; 3526} __packed; 3527 3528struct iwx_rx_mpdu_res_start { 3529 uint16_t byte_count; 3530 uint16_t reserved; 3531} __packed; 3532 3533/** 3534 * Values to parse %iwx_rx_phy_info phy_flags 3535 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 3536 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK: 3537 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 3538 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND: 3539 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 3540 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 3541 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 3542 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 3543 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 3544 */ 3545#define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 3546#define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3547#define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3548#define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3549#define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3550#define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3551#define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7) 3552#define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3553#define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3554#define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3555 3556/** 3557 * Values written by fw for each Rx packet 3558 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3559 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3560 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3561 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID: 3562 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3563 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3564 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3565 * in the driver. 3566 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3567 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3568 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3569 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3570 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3571 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3572 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3573 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3574 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3575 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3576 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3577 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3578 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3579 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3580 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3581 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3582 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3583 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK: 3584 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL: 3585 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK: 3586 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3587 */ 3588#define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3589#define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3590#define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3591#define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3592#define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3593#define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3594#define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3595#define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3596#define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3597#define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3598#define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3599#define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3600#define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3601#define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3602#define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3603#define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3604#define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3605#define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3606#define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3607#define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3608#define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3609#define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3610#define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3611#define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3612#define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3613#define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3614#define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3615 3616#define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3617#define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3618#define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3619 3620#define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3621#define IWX_RX_MPDU_MFLG2_PAD 0x20 3622#define IWX_RX_MPDU_MFLG2_AMSDU 0x40 3623 3624#define IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f 3625#define IWX_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80 3626 3627#define IWX_RX_MPDU_PHY_AMPDU (1 << 5) 3628#define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3629#define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3630#define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3631#define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3632 3633struct iwx_rx_mpdu_desc_v3 { 3634 union { 3635 uint32_t filter_match; 3636 uint32_t phy_data3; 3637 }; 3638 union { 3639 uint32_t rss_hash; 3640 uint32_t phy_data2; 3641 }; 3642 uint32_t partial_hash; /* ip/tcp header hash w/o some fields */ 3643 uint16_t raw_xsum; 3644 uint16_t reserved_xsum; 3645 uint32_t rate_n_flags; 3646 uint8_t energy_a; 3647 uint8_t energy_b; 3648 uint8_t channel; 3649 uint8_t mac_context; 3650 uint32_t gp2_on_air_rise; 3651 union { 3652 /* 3653 * TSF value on air rise (INA), only valid if 3654 * IWX_RX_MPDU_PHY_TSF_OVERLOAD isn't set 3655 */ 3656 struct { 3657 uint32_t tsf_on_air_rise0; 3658 uint32_t tsf_on_air_rise1; 3659 }; 3660 3661 struct { 3662 uint32_t phy_data0; 3663 3664 /* Only valid if IWX_RX_MPDU_PHY_TSF_OVERLOAD is set. */ 3665 uint32_t phy_data1; 3666 }; 3667 }; 3668 uint32_t reserved[2]; 3669} __packed; /* RX_MPDU_RES_START_API_S_VER_3, 3670 RX_MPDU_RES_START_API_S_VER_5 */ 3671 3672struct iwx_rx_mpdu_desc_v1 { 3673 union { 3674 uint32_t rss_hash; 3675 uint32_t phy_data2; 3676 }; 3677 union { 3678 uint32_t filter_match; 3679 uint32_t phy_data3; 3680 }; 3681 uint32_t rate_n_flags; 3682 uint8_t energy_a; 3683 uint8_t energy_b; 3684 uint8_t channel; 3685 uint8_t mac_context; 3686 uint32_t gp2_on_air_rise; 3687 union { 3688 struct { 3689 uint32_t tsf_on_air_rise0; 3690 uint32_t tsf_on_air_rise1; 3691 }; 3692 struct { 3693 uint32_t phy_data0; 3694 uint32_t phy_data1; 3695 }; 3696 }; 3697} __packed; 3698 3699#define IWX_RX_REORDER_DATA_INVALID_BAID 0x7f 3700 3701#define IWX_RX_MPDU_REORDER_NSSN_MASK 0x00000fff 3702#define IWX_RX_MPDU_REORDER_SN_MASK 0x00fff000 3703#define IWX_RX_MPDU_REORDER_SN_SHIFT 12 3704#define IWX_RX_MPDU_REORDER_BAID_MASK 0x7f000000 3705#define IWX_RX_MPDU_REORDER_BAID_SHIFT 24 3706#define IWX_RX_MPDU_REORDER_BA_OLD_SN 0x80000000 3707 3708struct iwx_rx_mpdu_desc { 3709 uint16_t mpdu_len; 3710 uint8_t mac_flags1; 3711 uint8_t mac_flags2; 3712 uint8_t amsdu_info; 3713 uint16_t phy_info; 3714 uint8_t mac_phy_idx; 3715 uint16_t raw_csum; 3716 union { 3717 uint16_t l3l4_flags; 3718 uint16_t phy_data4; 3719 }; 3720 uint16_t status; 3721 uint8_t hash_filter; 3722 uint8_t sta_id_flags; 3723 uint32_t reorder_data; 3724 union { 3725 struct iwx_rx_mpdu_desc_v1 v1; 3726 struct iwx_rx_mpdu_desc_v3 v3; 3727 }; 3728} __packed; /* RX_MPDU_RES_START_API_S_VER_3, 3729 RX_MPDU_RES_START_API_S_VER_4, 3730 RX_MPDU_RES_START_API_S_VER_5 */ 3731 3732#define IWX_RX_DESC_SIZE_V1 ((sizeof(struct iwx_rx_mpdu_desc) - \ 3733 sizeof(struct iwx_rx_mpdu_desc_v3)) + sizeof(struct iwx_rx_mpdu_desc_v1)) 3734 3735struct iwx_frame_release { 3736 uint8_t baid; 3737 uint8_t reserved; 3738 uint16_t nssn; 3739}; 3740 3741/** 3742 * enum iwx_bar_frame_release_sta_tid - STA/TID information for BAR release 3743 * @IWX_BAR_FRAME_RELEASE_TID_MASK: TID mask 3744 * @IWX_BAR_FRAME_RELEASE_STA_MASK: STA mask 3745 */ 3746#define IWX_BAR_FRAME_RELEASE_TID_MASK 0x0000000f 3747#define IWX_BAR_FRAME_RELEASE_STA_MASK 0x000001f0 3748#define IWX_BAR_FRAME_RELEASE_STA_SHIFT 4 3749 3750/** 3751 * enum iwx_bar_frame_release_ba_info - BA information for BAR release 3752 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 3753 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 3754 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 3755 */ 3756#define IWX_BAR_FRAME_RELEASE_NSSN_MASK 0x00000fff 3757#define IWX_BAR_FRAME_RELEASE_SN_MASK 0x00fff000 3758#define IWX_BAR_FRAME_RELEASE_SN_SHIFT 12 3759#define IWX_BAR_FRAME_RELEASE_BAID_MASK 0x3f000000 3760#define IWX_BAR_FRAME_RELEASE_BAID_SHIFT 24 3761 3762/** 3763 * struct iwx_bar_frame_release - frame release from BAR info 3764 * @sta_tid: STA & TID information, see &enum iwx_bar_frame_release_sta_tid. 3765 * @ba_info: BA information, see &enum iwx_bar_frame_release_ba_info. 3766 */ 3767struct iwx_bar_frame_release { 3768 uint32_t sta_tid; 3769 uint32_t ba_info; 3770} __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 3771 3772/** 3773 * struct iwx_radio_version_notif - information on the radio version 3774 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 ) 3775 * @radio_flavor: 3776 * @radio_step: 3777 * @radio_dash: 3778 */ 3779struct iwx_radio_version_notif { 3780 uint32_t radio_flavor; 3781 uint32_t radio_step; 3782 uint32_t radio_dash; 3783} __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3784 3785#define IWX_CARD_ENABLED 0x00 3786#define IWX_HW_CARD_DISABLED 0x01 3787#define IWX_SW_CARD_DISABLED 0x02 3788#define IWX_CT_KILL_CARD_DISABLED 0x04 3789#define IWX_HALT_CARD_DISABLED 0x08 3790#define IWX_CARD_DISABLED_MSK 0x0f 3791#define IWX_CARD_IS_RX_ON 0x10 3792 3793/** 3794 * struct iwx_radio_version_notif - information on the radio version 3795 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 ) 3796 * @flags: %iwx_card_state_flags 3797 */ 3798struct iwx_card_state_notif { 3799 uint32_t flags; 3800} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3801 3802/** 3803 * struct iwx_missed_beacons_notif - information on missed beacons 3804 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3805 * @mac_id: interface ID 3806 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3807 * beacons since last RX. 3808 * @consec_missed_beacons: number of consecutive missed beacons 3809 * @num_expected_beacons: 3810 * @num_recvd_beacons: 3811 */ 3812struct iwx_missed_beacons_notif { 3813 uint32_t mac_id; 3814 uint32_t consec_missed_beacons_since_last_rx; 3815 uint32_t consec_missed_beacons; 3816 uint32_t num_expected_beacons; 3817 uint32_t num_recvd_beacons; 3818} __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */ 3819 3820/** 3821 * struct iwx_mfuart_load_notif - mfuart image version & status 3822 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3823 * @installed_ver: installed image version 3824 * @external_ver: external image version 3825 * @status: MFUART loading status 3826 * @duration: MFUART loading time 3827*/ 3828struct iwx_mfuart_load_notif { 3829 uint32_t installed_ver; 3830 uint32_t external_ver; 3831 uint32_t status; 3832 uint32_t duration; 3833} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3834 3835/** 3836 * struct iwx_set_calib_default_cmd - set default value for calibration. 3837 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e ) 3838 * @calib_index: the calibration to set value for 3839 * @length: of data 3840 * @data: the value to set for the calibration result 3841 */ 3842struct iwx_set_calib_default_cmd { 3843 uint16_t calib_index; 3844 uint16_t length; 3845 uint8_t data[0]; 3846} __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */ 3847 3848#define IWX_MAX_PORT_ID_NUM 2 3849#define IWX_MAX_MCAST_FILTERING_ADDRESSES 256 3850 3851/** 3852 * struct iwx_mcast_filter_cmd - configure multicast filter. 3853 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3854 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3855 * to identify network interface adopted in host-device IF. 3856 * It is used by FW as index in array of addresses. This array has 3857 * IWX_MAX_PORT_ID_NUM members. 3858 * @count: Number of MAC addresses in the array 3859 * @pass_all: Set 1 to pass all multicast packets. 3860 * @bssid: current association BSSID. 3861 * @addr_list: Place holder for array of MAC addresses. 3862 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3863 */ 3864struct iwx_mcast_filter_cmd { 3865 uint8_t filter_own; 3866 uint8_t port_id; 3867 uint8_t count; 3868 uint8_t pass_all; 3869 uint8_t bssid[6]; 3870 uint8_t reserved[2]; 3871 uint8_t addr_list[0]; 3872} __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */ 3873 3874struct iwx_statistics_dbg { 3875 uint32_t burst_check; 3876 uint32_t burst_count; 3877 uint32_t wait_for_silence_timeout_cnt; 3878 uint32_t reserved[3]; 3879} __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */ 3880 3881struct iwx_statistics_div { 3882 uint32_t tx_on_a; 3883 uint32_t tx_on_b; 3884 uint32_t exec_time; 3885 uint32_t probe_time; 3886 uint32_t rssi_ant; 3887 uint32_t reserved2; 3888} __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3889 3890struct iwx_statistics_bt_activity { 3891 uint32_t hi_priority_tx_req_cnt; 3892 uint32_t hi_priority_tx_denied_cnt; 3893 uint32_t lo_priority_tx_req_cnt; 3894 uint32_t lo_priority_tx_denied_cnt; 3895 uint32_t hi_priority_rx_req_cnt; 3896 uint32_t hi_priority_rx_denied_cnt; 3897 uint32_t lo_priority_rx_req_cnt; 3898 uint32_t lo_priority_rx_denied_cnt; 3899} __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3900 3901struct iwx_statistics_general_common { 3902 uint32_t radio_temperature; 3903 struct iwx_statistics_dbg dbg; 3904 uint32_t sleep_time; 3905 uint32_t slots_out; 3906 uint32_t slots_idle; 3907 uint32_t ttl_timestamp; 3908 struct iwx_statistics_div slow_div; 3909 uint32_t rx_enable_counter; 3910 /* 3911 * num_of_sos_states: 3912 * count the number of times we have to re-tune 3913 * in order to get out of bad PHY status 3914 */ 3915 uint32_t num_of_sos_states; 3916 uint32_t beacon_filtered; 3917 uint32_t missed_beacons; 3918 uint8_t beacon_filter_average_energy; 3919 uint8_t beacon_filter_reason; 3920 uint8_t beacon_filter_current_energy; 3921 uint8_t beacon_filter_reserved; 3922 uint32_t beacon_filter_delta_time; 3923 struct iwx_statistics_bt_activity bt_activity; 3924 uint64_t rx_time; 3925 uint64_t on_time_rf; 3926 uint64_t on_time_scan; 3927 uint64_t tx_time; 3928} __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3929 3930struct iwx_statistics_rx_non_phy { 3931 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3932 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3933 uint32_t non_bssid_frames; /* number of frames with BSSID that 3934 * doesn't belong to the STA BSSID */ 3935 uint32_t filtered_frames; /* count frames that were dumped in the 3936 * filtering process */ 3937 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3938 * our serving channel */ 3939 uint32_t channel_beacons; /* beacons with our bss id and in our 3940 * serving channel */ 3941 uint32_t num_missed_bcon; /* number of missed beacons */ 3942 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3943 * ADC was in saturation */ 3944 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3945 * for INA */ 3946 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3947 uint32_t interference_data_flag; /* flag for interference data 3948 * availability. 1 when data is 3949 * available. */ 3950 uint32_t channel_load; /* counts RX Enable time in uSec */ 3951 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3952 * and CCK) counter */ 3953 uint32_t beacon_rssi_a; 3954 uint32_t beacon_rssi_b; 3955 uint32_t beacon_rssi_c; 3956 uint32_t beacon_energy_a; 3957 uint32_t beacon_energy_b; 3958 uint32_t beacon_energy_c; 3959 uint32_t num_bt_kills; 3960 uint32_t mac_id; 3961 uint32_t directed_data_mpdu; 3962} __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3963 3964struct iwx_statistics_rx_phy { 3965 uint32_t ina_cnt; 3966 uint32_t fina_cnt; 3967 uint32_t plcp_err; 3968 uint32_t crc32_err; 3969 uint32_t overrun_err; 3970 uint32_t early_overrun_err; 3971 uint32_t crc32_good; 3972 uint32_t false_alarm_cnt; 3973 uint32_t fina_sync_err_cnt; 3974 uint32_t sfd_timeout; 3975 uint32_t fina_timeout; 3976 uint32_t unresponded_rts; 3977 uint32_t rxe_frame_limit_overrun; 3978 uint32_t sent_ack_cnt; 3979 uint32_t sent_cts_cnt; 3980 uint32_t sent_ba_rsp_cnt; 3981 uint32_t dsp_self_kill; 3982 uint32_t mh_format_err; 3983 uint32_t re_acq_main_rssi_sum; 3984 uint32_t reserved; 3985} __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */ 3986 3987struct iwx_statistics_rx_ht_phy { 3988 uint32_t plcp_err; 3989 uint32_t overrun_err; 3990 uint32_t early_overrun_err; 3991 uint32_t crc32_good; 3992 uint32_t crc32_err; 3993 uint32_t mh_format_err; 3994 uint32_t agg_crc32_good; 3995 uint32_t agg_mpdu_cnt; 3996 uint32_t agg_cnt; 3997 uint32_t unsupport_mcs; 3998} __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3999 4000/* 4001 * The first MAC indices (starting from 0) 4002 * are available to the driver, AUX follows 4003 */ 4004#define IWX_MAC_INDEX_AUX 4 4005#define IWX_MAC_INDEX_MIN_DRIVER 0 4006#define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX 4007 4008#define IWX_STATION_COUNT 16 4009 4010#define IWX_MAX_CHAINS 3 4011 4012struct iwx_statistics_tx_non_phy_agg { 4013 uint32_t ba_timeout; 4014 uint32_t ba_reschedule_frames; 4015 uint32_t scd_query_agg_frame_cnt; 4016 uint32_t scd_query_no_agg; 4017 uint32_t scd_query_agg; 4018 uint32_t scd_query_mismatch; 4019 uint32_t frame_not_ready; 4020 uint32_t underrun; 4021 uint32_t bt_prio_kill; 4022 uint32_t rx_ba_rsp_cnt; 4023 int8_t txpower[IWX_MAX_CHAINS]; 4024 int8_t reserved; 4025 uint32_t reserved2; 4026} __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 4027 4028struct iwx_statistics_tx_channel_width { 4029 uint32_t ext_cca_narrow_ch20[1]; 4030 uint32_t ext_cca_narrow_ch40[2]; 4031 uint32_t ext_cca_narrow_ch80[3]; 4032 uint32_t ext_cca_narrow_ch160[4]; 4033 uint32_t last_tx_ch_width_indx; 4034 uint32_t rx_detected_per_ch_width[4]; 4035 uint32_t success_per_ch_width[4]; 4036 uint32_t fail_per_ch_width[4]; 4037}; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 4038 4039struct iwx_statistics_tx { 4040 uint32_t preamble_cnt; 4041 uint32_t rx_detected_cnt; 4042 uint32_t bt_prio_defer_cnt; 4043 uint32_t bt_prio_kill_cnt; 4044 uint32_t few_bytes_cnt; 4045 uint32_t cts_timeout; 4046 uint32_t ack_timeout; 4047 uint32_t expected_ack_cnt; 4048 uint32_t actual_ack_cnt; 4049 uint32_t dump_msdu_cnt; 4050 uint32_t burst_abort_next_frame_mismatch_cnt; 4051 uint32_t burst_abort_missing_next_frame_cnt; 4052 uint32_t cts_timeout_collision; 4053 uint32_t ack_or_ba_timeout_collision; 4054 struct iwx_statistics_tx_non_phy_agg agg; 4055 struct iwx_statistics_tx_channel_width channel_width; 4056} __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */ 4057 4058struct iwx_statistics_general { 4059 struct iwx_statistics_general_common common; 4060 uint32_t beacon_counter[IWX_MAC_INDEX_AUX]; 4061 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX]; 4062 uint8_t reserved[8 - IWX_MAC_INDEX_AUX]; 4063} __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 4064 4065struct iwx_statistics_rx { 4066 struct iwx_statistics_rx_phy ofdm; 4067 struct iwx_statistics_rx_phy cck; 4068 struct iwx_statistics_rx_non_phy general; 4069 struct iwx_statistics_rx_ht_phy ofdm_ht; 4070} __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */ 4071 4072/* 4073 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 4074 * 4075 * By default, uCode issues this notification after receiving a beacon 4076 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 4077 * IWX_REPLY_STATISTICS_CMD 0x9c, above. 4078 * 4079 * Statistics counters continue to increment beacon after beacon, but are 4080 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD 4081 * 0x9c with CLEAR_STATS bit set (see above). 4082 * 4083 * uCode also issues this notification during scans. uCode clears statistics 4084 * appropriately so that each notification contains statistics for only the 4085 * one channel that has just been scanned. 4086 */ 4087 4088/** 4089 * struct iwx_statistics_load - RX statistics for multi-queue devices 4090 * @air_time: accumulated air time, per mac 4091 * @byte_count: accumulated byte count, per mac 4092 * @pkt_count: accumulated packet count, per mac 4093 * @avg_energy: average RSSI, per station 4094 */ 4095struct iwx_statistics_load { 4096 uint32_t air_time[IWX_MAC_INDEX_AUX]; 4097 uint32_t byte_count[IWX_MAC_INDEX_AUX]; 4098 uint32_t pkt_count[IWX_MAC_INDEX_AUX]; 4099 uint8_t avg_energy[IWX_STATION_COUNT]; 4100} __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */ 4101 4102struct iwx_notif_statistics { 4103 uint32_t flag; 4104 struct iwx_statistics_rx rx; 4105 struct iwx_statistics_tx tx; 4106 struct iwx_statistics_general general; 4107 struct iwx_statistics_load load_stats; 4108} __packed; /* STATISTICS_NTFY_API_S_VER_13 */ 4109 4110 4111/** 4112 * flags used in statistics notification 4113 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report 4114 */ 4115#define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01 4116 4117/** 4118 * flags used in statistics command 4119 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report 4120 * that's sent after this command 4121 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics 4122 * notifications 4123 */ 4124#define IWX_STATISTICS_FLG_CLEAR 0x01 4125#define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02 4126 4127/** 4128 * struct iwx_statistics_cmd - statistics config command 4129 * @flags: IWX_STATISTICS_* flags 4130 */ 4131struct iwx_statistics_cmd { 4132 uint32_t flags; 4133} __packed; /* STATISTICS_CMD_API_S_VER_1 */ 4134 4135 4136/*********************************** 4137 * Smart Fifo API 4138 ***********************************/ 4139/* Smart Fifo state */ 4140#define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 4141#define IWX_SF_FULL_ON 1 4142#define IWX_SF_UNINIT 2 4143#define IWX_SF_INIT_OFF 3 4144#define IWX_SF_HW_NUM_STATES 4 4145 4146/* Smart Fifo possible scenario */ 4147#define IWX_SF_SCENARIO_SINGLE_UNICAST 0 4148#define IWX_SF_SCENARIO_AGG_UNICAST 1 4149#define IWX_SF_SCENARIO_MULTICAST 2 4150#define IWX_SF_SCENARIO_BA_RESP 3 4151#define IWX_SF_SCENARIO_TX_RESP 4 4152#define IWX_SF_NUM_SCENARIO 5 4153 4154#define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */ 4155#define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 4156 4157/* smart FIFO default values */ 4158#define IWX_SF_W_MARK_SISO 4096 4159#define IWX_SF_W_MARK_MIMO2 8192 4160#define IWX_SF_W_MARK_MIMO3 6144 4161#define IWX_SF_W_MARK_LEGACY 4096 4162#define IWX_SF_W_MARK_SCAN 4096 4163 4164/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 4165#define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 4166#define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4167#define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 4168#define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4169#define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 4170#define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4171#define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 4172#define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4173#define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 4174#define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4175 4176/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 4177#define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 4178#define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 4179#define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 4180#define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 4181#define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 4182#define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 4183#define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 4184#define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 4185#define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 4186#define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 4187 4188#define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 4189 4190#define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 4191 4192/** 4193 * Smart Fifo configuration command. 4194 * @state: smart fifo state, types listed in enum %iwx_sf_state. 4195 * @watermark: Minimum allowed available free space in RXF for transient state. 4196 * @long_delay_timeouts: aging and idle timer values for each scenario 4197 * in long delay state. 4198 * @full_on_timeouts: timer values for each scenario in full on state. 4199 */ 4200struct iwx_sf_cfg_cmd { 4201 uint32_t state; 4202 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER]; 4203 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 4204 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 4205} __packed; /* IWX_SF_CFG_API_S_VER_2 */ 4206 4207#define IWX_AC_BK 0 4208#define IWX_AC_BE 1 4209#define IWX_AC_VI 2 4210#define IWX_AC_VO 3 4211#define IWX_AC_NUM 4 4212 4213/** 4214 * MAC context flags 4215 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 4216 * this will require CCK RTS/CTS2self. 4217 * RTS/CTS will protect full burst time. 4218 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection 4219 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 4220 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 4221 */ 4222#define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 4223#define IWX_MAC_PROT_FLG_HT_PROT (1 << 23) 4224#define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24) 4225#define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 4226 4227#define IWX_MAC_FLG_SHORT_SLOT (1 << 4) 4228#define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5) 4229 4230/** 4231 * Supported MAC types 4232 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type 4233 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 4234 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 4235 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 4236 * @IWX_FW_MAC_TYPE_IBSS: IBSS 4237 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station 4238 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device 4239 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client 4240 * @IWX_FW_MAC_TYPE_GO: P2P GO 4241 * @IWX_FW_MAC_TYPE_TEST: ? 4242 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type 4243 */ 4244#define IWX_FW_MAC_TYPE_FIRST 1 4245#define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST 4246#define IWX_FW_MAC_TYPE_LISTENER 2 4247#define IWX_FW_MAC_TYPE_PIBSS 3 4248#define IWX_FW_MAC_TYPE_IBSS 4 4249#define IWX_FW_MAC_TYPE_BSS_STA 5 4250#define IWX_FW_MAC_TYPE_P2P_DEVICE 6 4251#define IWX_FW_MAC_TYPE_P2P_STA 7 4252#define IWX_FW_MAC_TYPE_GO 8 4253#define IWX_FW_MAC_TYPE_TEST 9 4254#define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST 4255/* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */ 4256 4257/** 4258 * TSF hw timer ID 4259 * @IWX_TSF_ID_A: use TSF A 4260 * @IWX_TSF_ID_B: use TSF B 4261 * @IWX_TSF_ID_C: use TSF C 4262 * @IWX_TSF_ID_D: use TSF D 4263 * @IWX_NUM_TSF_IDS: number of TSF timers available 4264 */ 4265#define IWX_TSF_ID_A 0 4266#define IWX_TSF_ID_B 1 4267#define IWX_TSF_ID_C 2 4268#define IWX_TSF_ID_D 3 4269#define IWX_NUM_TSF_IDS 4 4270/* IWX_TSF_ID_API_E_VER_1 */ 4271 4272/** 4273 * struct iwx_mac_data_ap - configuration data for AP MAC context 4274 * @beacon_time: beacon transmit time in system time 4275 * @beacon_tsf: beacon transmit time in TSF 4276 * @bi: beacon interval in TU 4277 * @bi_reciprocal: 2^32 / bi 4278 * @dtim_interval: dtim transmit time in TU 4279 * @dtim_reciprocal: 2^32 / dtim_interval 4280 * @mcast_qid: queue ID for multicast traffic 4281 * NOTE: obsolete from VER2 and on 4282 * @beacon_template: beacon template ID 4283 */ 4284struct iwx_mac_data_ap { 4285 uint32_t beacon_time; 4286 uint64_t beacon_tsf; 4287 uint32_t bi; 4288 uint32_t bi_reciprocal; 4289 uint32_t dtim_interval; 4290 uint32_t dtim_reciprocal; 4291 uint32_t mcast_qid; 4292 uint32_t beacon_template; 4293} __packed; /* AP_MAC_DATA_API_S_VER_2 */ 4294 4295/** 4296 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context 4297 * @beacon_time: beacon transmit time in system time 4298 * @beacon_tsf: beacon transmit time in TSF 4299 * @bi: beacon interval in TU 4300 * @bi_reciprocal: 2^32 / bi 4301 * @beacon_template: beacon template ID 4302 */ 4303struct iwx_mac_data_ibss { 4304 uint32_t beacon_time; 4305 uint64_t beacon_tsf; 4306 uint32_t bi; 4307 uint32_t bi_reciprocal; 4308 uint32_t beacon_template; 4309} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 4310 4311/** 4312 * enum iwx_mac_data_policy - policy of the data path for this MAC 4313 * @TWT_SUPPORTED: twt is supported 4314 * @MORE_DATA_ACK_SUPPORTED: AP supports More Data Ack according to 4315 * paragraph 9.4.1.17 in P802.11ax_D4 specification. Used for TWT 4316 * early termination detection. 4317 * @FLEXIBLE_TWT_SUPPORTED: AP supports flexible TWT schedule 4318 * @PROTECTED_TWT_SUPPORTED: AP supports protected TWT frames (with 11w) 4319 * @BROADCAST_TWT_SUPPORTED: AP and STA support broadcast TWT 4320 * @COEX_HIGH_PRIORITY_ENABLE: high priority mode for BT coex, to be used 4321 * during 802.1X negotiation (and allowed during 4-way-HS) 4322 */ 4323#define IWX_TWT_SUPPORTED BIT (1 << 0) 4324#define IWX_MORE_DATA_ACK_SUPPORTED (1 << 1) 4325#define IWX_FLEXIBLE_TWT_SUPPORTED (1 << 2) 4326#define IWX_PROTECTED_TWT_SUPPORTED (1 << 3) 4327#define IWX_BROADCAST_TWT_SUPPORTED (1 << 4) 4328#define IWX_COEX_HIGH_PRIORITY_ENABLE (1 << 5) 4329 4330/** 4331 * struct iwx_mac_data_sta - configuration data for station MAC context 4332 * @is_assoc: 1 for associated state, 0 otherwise 4333 * @dtim_time: DTIM arrival time in system time 4334 * @dtim_tsf: DTIM arrival time in TSF 4335 * @bi: beacon interval in TU, applicable only when associated 4336 * @data_policy: see &enum iwl_mac_data_policy 4337 * @dtim_interval: DTIM interval in TU, applicable only when associated 4338 * @listen_interval: in beacon intervals, applicable only when associated 4339 * @assoc_id: unique ID assigned by the AP during association 4340 */ 4341struct iwx_mac_data_sta { 4342 uint32_t is_assoc; 4343 uint32_t dtim_time; 4344 uint64_t dtim_tsf; 4345 uint32_t bi; 4346 uint32_t reserved1; 4347 uint32_t dtim_interval; 4348 uint32_t data_policy; 4349 uint32_t listen_interval; 4350 uint32_t assoc_id; 4351 uint32_t assoc_beacon_arrive_time; 4352} __packed; /* IWX_STA_MAC_DATA_API_S_VER_2 */ 4353 4354/** 4355 * struct iwx_mac_data_go - configuration data for P2P GO MAC context 4356 * @ap: iwx_mac_data_ap struct with most config data 4357 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 4358 * 0 indicates that there is no CT window. 4359 * @opp_ps_enabled: indicate that opportunistic PS allowed 4360 */ 4361struct iwx_mac_data_go { 4362 struct iwx_mac_data_ap ap; 4363 uint32_t ctwin; 4364 uint32_t opp_ps_enabled; 4365} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 4366 4367/** 4368 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context 4369 * @sta: iwx_mac_data_sta struct with most config data 4370 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 4371 * 0 indicates that there is no CT window. 4372 */ 4373struct iwx_mac_data_p2p_sta { 4374 struct iwx_mac_data_sta sta; 4375 uint32_t ctwin; 4376} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 4377 4378/** 4379 * struct iwx_mac_data_pibss - Pseudo IBSS config data 4380 * @stats_interval: interval in TU between statistics notifications to host. 4381 */ 4382struct iwx_mac_data_pibss { 4383 uint32_t stats_interval; 4384} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 4385 4386/* 4387 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC 4388 * context. 4389 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 4390 * other channels as well. This should be to true only in case that the 4391 * device is discoverable and there is an active GO. Note that setting this 4392 * field when not needed, will increase the number of interrupts and have 4393 * effect on the platform power, as this setting opens the Rx filters on 4394 * all macs. 4395 */ 4396struct iwx_mac_data_p2p_dev { 4397 uint32_t is_disc_extended; 4398} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 4399 4400/** 4401 * MAC context filter flags 4402 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames 4403 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all management and 4404 * control frames to the host 4405 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames 4406 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 4407 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 4408 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 4409 * (in station mode when associated) 4410 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 4411 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 4412 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 4413 */ 4414#define IWX_MAC_FILTER_IN_PROMISC (1 << 0) 4415#define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 4416#define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2) 4417#define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3) 4418#define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 4419#define IWX_MAC_FILTER_IN_BEACON (1 << 6) 4420#define IWX_MAC_FILTER_OUT_BCAST (1 << 8) 4421#define IWX_MAC_FILTER_IN_CRC32 (1 << 11) 4422#define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 4423 4424/** 4425 * QoS flags 4426 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ? 4427 * @IWX_MAC_QOS_FLG_TGN: HT is enabled 4428 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ? 4429 * 4430 */ 4431#define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 4432#define IWX_MAC_QOS_FLG_TGN (1 << 1) 4433#define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 4434 4435/** 4436 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD 4437 * @cw_min: Contention window, start value in numbers of slots. 4438 * Should be a power-of-2, minus 1. Device's default is 0x0f. 4439 * @cw_max: Contention window, max value in numbers of slots. 4440 * Should be a power-of-2, minus 1. Device's default is 0x3f. 4441 * @aifsn: Number of slots in Arbitration Interframe Space (before 4442 * performing random backoff timing prior to Tx). Device default 1. 4443 * @fifos_mask: FIFOs used by this MAC for this AC 4444 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 4445 * 4446 * One instance of this config struct for each of 4 EDCA access categories 4447 * in struct iwx_qosparam_cmd. 4448 * 4449 * Device will automatically increase contention window by (2*CW) + 1 for each 4450 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 4451 * value, to cap the CW value. 4452 */ 4453struct iwx_ac_qos { 4454 uint16_t cw_min; 4455 uint16_t cw_max; 4456 uint8_t aifsn; 4457 uint8_t fifos_mask; 4458 uint16_t edca_txop; 4459} __packed; /* IWX_AC_QOS_API_S_VER_2 */ 4460 4461/** 4462 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts 4463 * ( IWX_MAC_CONTEXT_CMD = 0x28 ) 4464 * @id_and_color: ID and color of the MAC 4465 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 4466 * @mac_type: one of IWX_FW_MAC_TYPE_* 4467 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_* 4468 * @node_addr: MAC address 4469 * @bssid_addr: BSSID 4470 * @cck_rates: basic rates available for CCK 4471 * @ofdm_rates: basic rates available for OFDM 4472 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_* 4473 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 4474 * @short_slot: 0x10 for enabling short slots, 0 otherwise 4475 * @filter_flags: combination of IWX_MAC_FILTER_* 4476 * @qos_flags: from IWX_MAC_QOS_FLG_* 4477 * @ac: one iwx_mac_qos configuration for each AC 4478 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type 4479 */ 4480struct iwx_mac_ctx_cmd { 4481 /* COMMON_INDEX_HDR_API_S_VER_1 */ 4482 uint32_t id_and_color; 4483 uint32_t action; 4484 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 4485 uint32_t mac_type; 4486 uint32_t tsf_id; 4487 uint8_t node_addr[6]; 4488 uint16_t reserved_for_node_addr; 4489 uint8_t bssid_addr[6]; 4490 uint16_t reserved_for_bssid_addr; 4491 uint32_t cck_rates; 4492 uint32_t ofdm_rates; 4493 uint32_t protection_flags; 4494 uint32_t cck_short_preamble; 4495 uint32_t short_slot; 4496 uint32_t filter_flags; 4497 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */ 4498 uint32_t qos_flags; 4499 struct iwx_ac_qos ac[IWX_AC_NUM+1]; 4500 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */ 4501 union { 4502 struct iwx_mac_data_ap ap; 4503 struct iwx_mac_data_go go; 4504 struct iwx_mac_data_sta sta; 4505 struct iwx_mac_data_p2p_sta p2p_sta; 4506 struct iwx_mac_data_p2p_dev p2p_dev; 4507 struct iwx_mac_data_pibss pibss; 4508 struct iwx_mac_data_ibss ibss; 4509 }; 4510} __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */ 4511 4512static inline uint32_t iwx_reciprocal(uint32_t v) 4513{ 4514 if (!v) 4515 return 0; 4516 return 0xFFFFFFFF / v; 4517} 4518 4519/* Power Management Commands, Responses, Notifications */ 4520 4521/** 4522 * masks for LTR config command flags 4523 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 4524 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 4525 * memory access 4526 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 4527 * reg change 4528 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 4529 * D0 to D3 4530 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 4531 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 4532 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 4533 */ 4534#define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 4535#define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 4536#define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 4537#define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 4538#define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 4539#define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 4540#define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 4541 4542#define IWX_LTR_VALID_STATES_NUM 4 4543 4544/** 4545 * struct iwx_ltr_config_cmd - configures the LTR 4546 * @flags: See %enum iwx_ltr_config_flags 4547 * @static_long: 4548 * @static_short: 4549 * @ltr_cfg_values: 4550 * @ltr_short_idle_timeout: 4551 */ 4552struct iwx_ltr_config_cmd { 4553 uint32_t flags; 4554 uint32_t static_long; 4555 uint32_t static_short; 4556 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM]; 4557 uint32_t ltr_short_idle_timeout; 4558} __packed; /* LTR_CAPABLE_API_S_VER_2 */ 4559 4560/* Radio LP RX Energy Threshold measured in dBm */ 4561#define IWX_POWER_LPRX_RSSI_THRESHOLD 75 4562#define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94 4563#define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30 4564 4565/** 4566 * Masks for iwx_mac_power_cmd command flags 4567 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 4568 * receiver and transmitter. '0' - does not allow. 4569 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 4570 * '1' Driver enables PM (use rest of parameters) 4571 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 4572 * '1' PM could sleep over DTIM till listen Interval. 4573 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 4574 * access categories are both delivery and trigger enabled. 4575 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 4576 * PBW Snoozing enabled 4577 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 4578 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 4579 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 4580 * detection enablement 4581*/ 4582#define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4583#define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 4584#define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 4585#define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 4586#define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8) 4587#define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 4588#define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 4589#define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 4590 4591#define IWX_POWER_VEC_SIZE 5 4592 4593/** 4594 * Masks for device power command flags 4595 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 4596 * '1' Allow to save power by turning off receiver and transmitter. 4597 * '0' Do not allow. This flag should be always set to '1' unless 4598 * one needs to disable actual power down for debug purposes. 4599 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK: 4600 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 4601 * '0' Power management is enabled, one of the power schemes is applied. 4602 */ 4603#define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4604#define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 4605 4606/** 4607 * struct iwx_device_power_cmd - device wide power command. 4608 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 4609 * 4610 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_* 4611 */ 4612struct iwx_device_power_cmd { 4613 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 4614 uint16_t flags; 4615 uint16_t reserved; 4616} __packed; 4617 4618/** 4619 * struct iwx_mac_power_cmd - New power command containing uAPSD support 4620 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 4621 * @id_and_color: MAC context identifier 4622 * @flags: Power table command flags from POWER_FLAGS_* 4623 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 4624 * Minimum allowed:- 3 * DTIM. Keep alive period must be 4625 * set regardless of power scheme or current power state. 4626 * FW use this value also when PM is disabled. 4627 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 4628 * PSM transition - legacy PM 4629 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 4630 * PSM transition - legacy PM 4631 * @sleep_interval: not in use 4632 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 4633 * is set. For example, if it is required to skip over 4634 * one DTIM, this value need to be set to 2 (DTIM periods). 4635 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 4636 * PSM transition - uAPSD 4637 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 4638 * PSM transition - uAPSD 4639 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 4640 * Default: 80dbm 4641 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 4642 * @snooze_interval: Maximum time between attempts to retrieve buffered data 4643 * from the AP [msec] 4644 * @snooze_window: A window of time in which PBW snoozing insures that all 4645 * packets received. It is also the minimum time from last 4646 * received unicast RX packet, before client stops snoozing 4647 * for data. [msec] 4648 * @snooze_step: TBD 4649 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 4650 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4651 * each corresponding AC. 4652 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4653 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4654 * values. 4655 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4656 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4657 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4658 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4659 * @limited_ps_threshold: 4660*/ 4661struct iwx_mac_power_cmd { 4662 /* CONTEXT_DESC_API_T_VER_1 */ 4663 uint32_t id_and_color; 4664 4665 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4666 uint16_t flags; 4667 uint16_t keep_alive_seconds; 4668 uint32_t rx_data_timeout; 4669 uint32_t tx_data_timeout; 4670 uint32_t rx_data_timeout_uapsd; 4671 uint32_t tx_data_timeout_uapsd; 4672 uint8_t lprx_rssi_threshold; 4673 uint8_t skip_dtim_periods; 4674 uint16_t snooze_interval; 4675 uint16_t snooze_window; 4676 uint8_t snooze_step; 4677 uint8_t qndp_tid; 4678 uint8_t uapsd_ac_flags; 4679 uint8_t uapsd_max_sp; 4680 uint8_t heavy_tx_thld_packets; 4681 uint8_t heavy_rx_thld_packets; 4682 uint8_t heavy_tx_thld_percentage; 4683 uint8_t heavy_rx_thld_percentage; 4684 uint8_t limited_ps_threshold; 4685 uint8_t reserved; 4686} __packed; 4687 4688#define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4689#define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4690 4691/* 4692 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when 4693 * associated AP is identified as improperly implementing uAPSD protocol. 4694 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4695 * @sta_id: index of station in uCode's station table - associated AP ID in 4696 * this context. 4697 */ 4698struct iwx_uapsd_misbehaving_ap_notif { 4699 uint32_t sta_id; 4700 uint8_t mac_id; 4701 uint8_t reserved[3]; 4702} __packed; 4703 4704/** 4705 * struct iwx_beacon_filter_cmd 4706 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4707 * @id_and_color: MAC context identifier 4708 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4709 * to driver if delta in Energy values calculated for this and last 4710 * passed beacon is greater than this threshold. Zero value means that 4711 * the Energy change is ignored for beacon filtering, and beacon will 4712 * not be forced to be sent to driver regardless of this delta. Typical 4713 * energy delta 5dB. 4714 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4715 * Send beacon to driver if delta in Energy values calculated for this 4716 * and last passed beacon is greater than this threshold. Zero value 4717 * means that the Energy change is ignored for beacon filtering while in 4718 * Roaming state, typical energy delta 1dB. 4719 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4720 * calculated for current beacon is less than the threshold, use 4721 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4722 * Threshold. Typical energy threshold is -72dBm. 4723 * @bf_temp_threshold: This threshold determines the type of temperature 4724 * filtering (Slow or Fast) that is selected (Units are in Celsius): 4725 * If the current temperature is above this threshold - Fast filter 4726 * will be used, If the current temperature is below this threshold - 4727 * Slow filter will be used. 4728 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4729 * calculated for this and the last passed beacon is greater than this 4730 * threshold. Zero value means that the temperature change is ignored for 4731 * beacon filtering; beacons will not be forced to be sent to driver 4732 * regardless of whether its temperature has been changed. 4733 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4734 * calculated for this and the last passed beacon is greater than this 4735 * threshold. Zero value means that the temperature change is ignored for 4736 * beacon filtering; beacons will not be forced to be sent to driver 4737 * regardless of whether its temperature has been changed. 4738 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4739 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4740 * for a specific period of time. Units: Beacons. 4741 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4742 * for a longer period of time then this escape-timeout. Units: Beacons. 4743 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4744 * @bf_threshold_absolute_low: See below. 4745 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated 4746 * for this beacon crossed this absolute threshold. For the 'Increase' 4747 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease' 4748 * direction the bf_energy_absolute_high[i] is used. Zero value means 4749 * that this specific threshold is ignored for beacon filtering, and 4750 * beacon will not be forced to be sent to driver due to this setting. 4751 */ 4752struct iwx_beacon_filter_cmd { 4753 uint32_t bf_energy_delta; 4754 uint32_t bf_roaming_energy_delta; 4755 uint32_t bf_roaming_state; 4756 uint32_t bf_temp_threshold; 4757 uint32_t bf_temp_fast_filter; 4758 uint32_t bf_temp_slow_filter; 4759 uint32_t bf_enable_beacon_filter; 4760 uint32_t bf_debug_flag; 4761 uint32_t bf_escape_timer; 4762 uint32_t ba_escape_timer; 4763 uint32_t ba_enable_beacon_abort; 4764 uint32_t bf_threshold_absolute_low[2]; 4765 uint32_t bf_threshold_absolute_high[2]; 4766} __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */ 4767 4768/* Beacon filtering and beacon abort */ 4769#define IWX_BF_ENERGY_DELTA_DEFAULT 5 4770#define IWX_BF_ENERGY_DELTA_MAX 255 4771#define IWX_BF_ENERGY_DELTA_MIN 0 4772 4773#define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4774#define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255 4775#define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0 4776 4777#define IWX_BF_ROAMING_STATE_DEFAULT 72 4778#define IWX_BF_ROAMING_STATE_MAX 255 4779#define IWX_BF_ROAMING_STATE_MIN 0 4780 4781#define IWX_BF_TEMP_THRESHOLD_DEFAULT 112 4782#define IWX_BF_TEMP_THRESHOLD_MAX 255 4783#define IWX_BF_TEMP_THRESHOLD_MIN 0 4784 4785#define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1 4786#define IWX_BF_TEMP_FAST_FILTER_MAX 255 4787#define IWX_BF_TEMP_FAST_FILTER_MIN 0 4788 4789#define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5 4790#define IWX_BF_TEMP_SLOW_FILTER_MAX 255 4791#define IWX_BF_TEMP_SLOW_FILTER_MIN 0 4792 4793#define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4794 4795#define IWX_BF_DEBUG_FLAG_DEFAULT 0 4796 4797#define IWX_BF_ESCAPE_TIMER_DEFAULT 50 4798#define IWX_BF_ESCAPE_TIMER_MAX 1024 4799#define IWX_BF_ESCAPE_TIMER_MIN 0 4800 4801#define IWX_BA_ESCAPE_TIMER_DEFAULT 6 4802#define IWX_BA_ESCAPE_TIMER_D3 9 4803#define IWX_BA_ESCAPE_TIMER_MAX 1024 4804#define IWX_BA_ESCAPE_TIMER_MIN 0 4805 4806#define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4807 4808#define IWX_BF_CMD_CONFIG_DEFAULTS \ 4809 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \ 4810 .bf_roaming_energy_delta = \ 4811 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4812 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \ 4813 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \ 4814 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \ 4815 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4816 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \ 4817 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \ 4818 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT) 4819 4820/* uCode API values for HT/VHT bit rates */ 4821#define IWX_RATE_HT_SISO_MCS_0_PLCP 0 4822#define IWX_RATE_HT_SISO_MCS_1_PLCP 1 4823#define IWX_RATE_HT_SISO_MCS_2_PLCP 2 4824#define IWX_RATE_HT_SISO_MCS_3_PLCP 3 4825#define IWX_RATE_HT_SISO_MCS_4_PLCP 4 4826#define IWX_RATE_HT_SISO_MCS_5_PLCP 5 4827#define IWX_RATE_HT_SISO_MCS_6_PLCP 6 4828#define IWX_RATE_HT_SISO_MCS_7_PLCP 7 4829#define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4830#define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4831#define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4832#define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4833#define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4834#define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4835#define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4836#define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4837#define IWX_RATE_VHT_SISO_MCS_0_PLCP 0 4838#define IWX_RATE_VHT_SISO_MCS_1_PLCP 1 4839#define IWX_RATE_VHT_SISO_MCS_2_PLCP 2 4840#define IWX_RATE_VHT_SISO_MCS_3_PLCP 3 4841#define IWX_RATE_VHT_SISO_MCS_4_PLCP 4 4842#define IWX_RATE_VHT_SISO_MCS_5_PLCP 5 4843#define IWX_RATE_VHT_SISO_MCS_6_PLCP 6 4844#define IWX_RATE_VHT_SISO_MCS_7_PLCP 7 4845#define IWX_RATE_VHT_SISO_MCS_8_PLCP 8 4846#define IWX_RATE_VHT_SISO_MCS_9_PLCP 9 4847#define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4848#define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4849#define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4850#define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4851#define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4852#define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4853#define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4854#define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4855#define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4856#define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4857#define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20 4858#define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4859#define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4860#define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4861#define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4862#define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4863 4864/* 4865 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX]. 4866 */ 4867enum { 4868 IWX_RATE_1M_INDEX = 0, 4869 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX, 4870 IWX_RATE_2M_INDEX, 4871 IWX_RATE_5M_INDEX, 4872 IWX_RATE_11M_INDEX, 4873 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX, 4874 IWX_RATE_6M_INDEX, 4875 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX, 4876 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX, 4877 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX, 4878 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX, 4879 IWX_RATE_9M_INDEX, 4880 IWX_RATE_12M_INDEX, 4881 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX, 4882 IWX_RATE_MCS_8_INDEX, 4883 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX, 4884 IWX_RATE_18M_INDEX, 4885 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX, 4886 IWX_RATE_24M_INDEX, 4887 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX, 4888 IWX_RATE_MCS_9_INDEX, 4889 IWX_RATE_36M_INDEX, 4890 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX, 4891 IWX_RATE_MCS_10_INDEX, 4892 IWX_RATE_48M_INDEX, 4893 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX, 4894 IWX_RATE_MCS_11_INDEX, 4895 IWX_RATE_54M_INDEX, 4896 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX, 4897 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX, 4898 IWX_RATE_MCS_7_INDEX, 4899 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX, 4900 IWX_RATE_MCS_12_INDEX, 4901 IWX_RATE_MCS_13_INDEX, 4902 IWX_RATE_MCS_14_INDEX, 4903 IWX_RATE_MCS_15_INDEX, 4904 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX, 4905 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX, 4906 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1, 4907 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1, 4908}; 4909 4910#define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX)) 4911 4912/* fw API values for legacy bit rates, both OFDM and CCK */ 4913#define IWX_RATE_6M_PLCP 13 4914#define IWX_RATE_9M_PLCP 15 4915#define IWX_RATE_12M_PLCP 5 4916#define IWX_RATE_18M_PLCP 7 4917#define IWX_RATE_24M_PLCP 9 4918#define IWX_RATE_36M_PLCP 11 4919#define IWX_RATE_48M_PLCP 1 4920#define IWX_RATE_54M_PLCP 3 4921#define IWX_RATE_1M_PLCP 10 4922#define IWX_RATE_2M_PLCP 20 4923#define IWX_RATE_5M_PLCP 55 4924#define IWX_RATE_11M_PLCP 110 4925#define IWX_RATE_INVM_PLCP 0xff 4926 4927/* 4928 * rate_n_flags bit fields version 1 4929 * 4930 * The 32-bit value has different layouts in the low 8 bites depending on the 4931 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4932 * for CCK and OFDM). 4933 * 4934 * High-throughput (HT) rate format 4935 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4936 * Very High-throughput (VHT) rate format 4937 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4938 * Legacy OFDM rate format for bits 7:0 4939 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4940 * Legacy CCK rate format for bits 7:0: 4941 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4942 */ 4943 4944/* Bit 8: (1) HT format, (0) legacy or VHT format */ 4945#define IWX_RATE_MCS_HT_POS 8 4946#define IWX_RATE_MCS_HT_MSK_V1 (1 << IWX_RATE_MCS_HT_POS) 4947 4948/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4949#define IWX_RATE_MCS_CCK_POS_V1 9 4950#define IWX_RATE_MCS_CCK_MSK_V1 (1 << IWX_RATE_MCS_CCK_POS_V1) 4951 4952/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4953#define IWX_RATE_MCS_VHT_POS_V1 26 4954#define IWX_RATE_MCS_VHT_MSK_V1 (1 << IWX_RATE_MCS_VHT_POS_V1) 4955 4956 4957/* 4958 * High-throughput (HT) rate format for bits 7:0 4959 * 4960 * 2-0: MCS rate base 4961 * 0) 6 Mbps 4962 * 1) 12 Mbps 4963 * 2) 18 Mbps 4964 * 3) 24 Mbps 4965 * 4) 36 Mbps 4966 * 5) 48 Mbps 4967 * 6) 54 Mbps 4968 * 7) 60 Mbps 4969 * 4-3: 0) Single stream (SISO) 4970 * 1) Dual stream (MIMO) 4971 * 2) Triple stream (MIMO) 4972 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4973 * (bits 7-6 are zero) 4974 * 4975 * Together the low 5 bits work out to the MCS index because we don't 4976 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4977 * streams and 16-23 have three streams. We could also support MCS 32 4978 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4979 */ 4980#define IWX_RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 4981#define IWX_RATE_HT_MCS_NSS_POS_V1 3 4982#define IWX_RATE_HT_MCS_NSS_MSK_V1 (3 << IWX_RATE_HT_MCS_NSS_POS_V1) 4983#define IWX_RATE_HT_MCS_MIMO2_MSK_V1 (1 << IWX_RATE_HT_MCS_NSS_POS_V1) 4984 4985/* Bit 10: (1) Use Green Field preamble */ 4986#define IWX_RATE_HT_MCS_GF_POS 10 4987#define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS) 4988 4989#define IWX_RATE_HT_MCS_INDEX_MSK_V1 0x3f 4990 4991/* 4992 * Very High-throughput (VHT) rate format for bits 7:0 4993 * 4994 * 3-0: VHT MCS (0-9) 4995 * 5-4: number of streams - 1: 4996 * 0) Single stream (SISO) 4997 * 1) Dual stream (MIMO) 4998 * 2) Triple stream (MIMO) 4999 */ 5000 5001/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 5002#define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf 5003#define IWX_RATE_VHT_MCS_NSS_POS 4 5004#define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS) 5005#define IWX_RATE_VHT_MCS_MIMO2_MSK (1 << IWX_RATE_VHT_MCS_NSS_POS) 5006 5007/* 5008 * Legacy OFDM rate format for bits 7:0 5009 * 5010 * 3-0: 0xD) 6 Mbps 5011 * 0xF) 9 Mbps 5012 * 0x5) 12 Mbps 5013 * 0x7) 18 Mbps 5014 * 0x9) 24 Mbps 5015 * 0xB) 36 Mbps 5016 * 0x1) 48 Mbps 5017 * 0x3) 54 Mbps 5018 * (bits 7-4 are 0) 5019 * 5020 * Legacy CCK rate format for bits 7:0: 5021 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 5022 * 5023 * 6-0: 10) 1 Mbps 5024 * 20) 2 Mbps 5025 * 55) 5.5 Mbps 5026 * 110) 11 Mbps 5027 * (bit 7 is 0) 5028 */ 5029#define IWX_RATE_LEGACY_RATE_MSK_V1 0xff 5030 5031/* Bit 10 - OFDM HE */ 5032#define IWX_RATE_MCS_HE_POS_V1 10 5033#define IWX_RATE_MCS_HE_MSK_V1 (1 << RATE_MCS_HE_POS_V1) 5034 5035/* 5036 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 5037 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 5038 */ 5039#define IWX_RATE_MCS_CHAN_WIDTH_POS 11 5040#define IWX_RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5041#define IWX_RATE_MCS_CHAN_WIDTH_20_V1 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5042#define IWX_RATE_MCS_CHAN_WIDTH_40_V1 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5043#define IWX_RATE_MCS_CHAN_WIDTH_80_V1 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5044#define IWX_RATE_MCS_CHAN_WIDTH_160_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5045 5046/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 5047#define IWX_RATE_MCS_SGI_POS_V1 13 5048#define IWX_RATE_MCS_SGI_MSK_V1 (1 << IWX_RATE_MCS_SGI_POS_V1) 5049 5050/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C (unused) */ 5051#define IWX_RATE_MCS_ANT_POS 14 5052#define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS) 5053#define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS) 5054#define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \ 5055 IWX_RATE_MCS_ANT_B_MSK) 5056#define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK 5057#define IWX_RATE_MCS_ANT_NUM 2 5058 5059/* Bit 17: (0) SS, (1) SS*2 */ 5060#define IWX_RATE_MCS_STBC_POS 17 5061#define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS) 5062 5063/* Bit 18: OFDM-HE dual carrier mode */ 5064#define IWX_RATE_HE_DUAL_CARRIER_MODE 18 5065#define IWX_RATE_HE_DUAL_CARRIER_MODE_MSK (1 << IWX_RATE_HE_DUAL_CARRIER_MODE) 5066 5067/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 5068#define IWX_RATE_MCS_BF_POS 19 5069#define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS) 5070 5071/* 5072 * Bit 20-21: HE LTF type and guard interval 5073 * HE (ext) SU: 5074 * 0 1xLTF+0.8us 5075 * 1 2xLTF+0.8us 5076 * 2 2xLTF+1.6us 5077 * 3 & SGI (bit 13) clear 4xLTF+3.2us 5078 * 3 & SGI (bit 13) set 4xLTF+0.8us 5079 * HE MU: 5080 * 0 4xLTF+0.8us 5081 * 1 2xLTF+0.8us 5082 * 2 2xLTF+1.6us 5083 * 3 4xLTF+3.2us 5084 * HE TRIG: 5085 * 0 1xLTF+1.6us 5086 * 1 2xLTF+1.6us 5087 * 2 4xLTF+3.2us 5088 * 3 (does not occur) 5089 */ 5090#define IWX_RATE_MCS_HE_GI_LTF_POS 20 5091#define IWX_RATE_MCS_HE_GI_LTF_MSK_V1 (3 << IWX_RATE_MCS_HE_GI_LTF_POS) 5092 5093/* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 5094#define IWX_RATE_MCS_HE_TYPE_POS_V1 22 5095#define IWX_RATE_MCS_HE_TYPE_SU_V1 (0 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5096#define IWX_RATE_MCS_HE_TYPE_EXT_SU_V1 (1 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5097#define IWX_RATE_MCS_HE_TYPE_MU_V1 (2 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5098#define IWX_RATE_MCS_HE_TYPE_TRIG_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5099#define IWX_RATE_MCS_HE_TYPE_MSK_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5100 5101/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 5102#define IWX_RATE_MCS_DUP_POS_V1 24 5103#define IWX_RATE_MCS_DUP_MSK_V1 (3 << IWX_RATE_MCS_DUP_POS_V1) 5104 5105/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 5106#define IWX_RATE_MCS_LDPC_POS_V1 27 5107#define IWX_RATE_MCS_LDPC_MSK_V1 (1 << IWX_RATE_MCS_LDPC_POS_V1) 5108 5109/* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 5110#define IWX_RATE_MCS_HE_106T_POS_V1 28 5111#define IWX_RATE_MCS_HE_106T_MSK_V1 (1 << IWX_RATE_MCS_HE_106T_POS_V1) 5112 5113/* Bit 30-31: (1) RTS, (2) CTS */ 5114#define IWX_RATE_MCS_RTS_REQUIRED_POS (30) 5115#define IWX_RATE_MCS_RTS_REQUIRED_MSK (1 << IWX_RATE_MCS_RTS_REQUIRED_POS) 5116#define IWX_RATE_MCS_CTS_REQUIRED_POS (31) 5117#define IWX_RATE_MCS_CTS_REQUIRED_MSK (1 << IWX_RATE_MCS_CTS_REQUIRED_POS) 5118 5119 5120/* rate_n_flags bit field version 2 5121 * 5122 * The 32-bit value has different layouts in the low 8 bits depending on the 5123 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 5124 * for CCK and OFDM). 5125 * 5126 */ 5127 5128/* Bits 10-8: rate format 5129 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 5130 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 5131 * (5) Extremely High-throughput (EHT) 5132 */ 5133#define IWX_RATE_MCS_MOD_TYPE_POS 8 5134#define IWX_RATE_MCS_MOD_TYPE_MSK (0x7 << IWX_RATE_MCS_MOD_TYPE_POS) 5135#define IWX_RATE_MCS_CCK_MSK (0 << IWX_RATE_MCS_MOD_TYPE_POS) 5136#define IWX_RATE_MCS_LEGACY_OFDM_MSK (1 << IWX_RATE_MCS_MOD_TYPE_POS) 5137#define IWX_RATE_MCS_HT_MSK (2 << IWX_RATE_MCS_MOD_TYPE_POS) 5138#define IWX_RATE_MCS_VHT_MSK (3 << IWX_RATE_MCS_MOD_TYPE_POS) 5139#define IWX_RATE_MCS_HE_MSK (4 << IWX_RATE_MCS_MOD_TYPE_POS) 5140#define IWX_RATE_MCS_EHT_MSK (5 << IWX_RATE_MCS_MOD_TYPE_POS) 5141 5142/* 5143 * Legacy CCK rate format for bits 0:3: 5144 * 5145 * (0) 0xa - 1 Mbps 5146 * (1) 0x14 - 2 Mbps 5147 * (2) 0x37 - 5.5 Mbps 5148 * (3) 0x6e - 11 nbps 5149 * 5150 * Legacy OFDM rate format for bits 0:3: 5151 * 5152 * (0) 6 Mbps 5153 * (1) 9 Mbps 5154 * (2) 12 Mbps 5155 * (3) 18 Mbps 5156 * (4) 24 Mbps 5157 * (5) 36 Mbps 5158 * (6) 48 Mbps 5159 * (7) 54 Mbps 5160 * 5161 */ 5162#define IWX_RATE_LEGACY_RATE_MSK 0x7 5163 5164/* 5165 * HT, VHT, HE, EHT rate format for bits 3:0 5166 * 3-0: MCS 5167 * 5168 */ 5169#define IWX_RATE_HT_MCS_CODE_MSK 0x7 5170#define IWX_RATE_MCS_NSS_POS 4 5171#define IWX_RATE_MCS_NSS_MSK (1 << IWX_RATE_MCS_NSS_POS) 5172#define IWX_RATE_MCS_CODE_MSK 0xf 5173#define IWX_RATE_HT_MCS_INDEX(r) ((((r) & IWX_RATE_MCS_NSS_MSK) >> 1) | \ 5174 ((r) & IWX_RATE_HT_MCS_CODE_MSK)) 5175 5176/* Bits 7-5: reserved */ 5177 5178/* 5179 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 5180 */ 5181#define IWX_RATE_MCS_CHAN_WIDTH_MSK (0x7 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5182#define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5183#define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5184#define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5185#define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5186#define IWX_RATE_MCS_CHAN_WIDTH_320 (4 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5187 5188/* Bit 15-14: Antenna selection: 5189 * Bit 14: Ant A active 5190 * Bit 15: Ant B active 5191 * 5192 * All relevant definitions are same as in v1 5193 */ 5194 5195/* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 5196#define IWX_RATE_MCS_LDPC_POS 16 5197#define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS) 5198 5199/* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 5200 5201/* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 5202 5203/* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 5204 5205/* 5206 * Bit 22-20: HE LTF type and guard interval 5207 * CCK: 5208 * 0 long preamble 5209 * 1 short preamble 5210 * HT/VHT: 5211 * 0 0.8us 5212 * 1 0.4us 5213 * HE (ext) SU: 5214 * 0 1xLTF+0.8us 5215 * 1 2xLTF+0.8us 5216 * 2 2xLTF+1.6us 5217 * 3 4xLTF+3.2us 5218 * 4 4xLTF+0.8us 5219 * HE MU: 5220 * 0 4xLTF+0.8us 5221 * 1 2xLTF+0.8us 5222 * 2 2xLTF+1.6us 5223 * 3 4xLTF+3.2us 5224 * HE TRIG: 5225 * 0 1xLTF+1.6us 5226 * 1 2xLTF+1.6us 5227 * 2 4xLTF+3.2us 5228 * */ 5229#define IWX_RATE_MCS_HE_GI_LTF_MSK (0x7 << IWX_RATE_MCS_HE_GI_LTF_POS) 5230#define IWX_RATE_MCS_SGI_POS IWX_RATE_MCS_HE_GI_LTF_POS 5231#define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS) 5232#define IWX_RATE_MCS_HE_SU_4_LTF 3 5233#define IWX_RATE_MCS_HE_SU_4_LTF_08_GI 4 5234 5235/* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 5236#define IWX_RATE_MCS_HE_TYPE_POS 23 5237#define IWX_RATE_MCS_HE_TYPE_SU (0 << IWX_RATE_MCS_HE_TYPE_POS) 5238#define IWX_RATE_MCS_HE_TYPE_EXT_SU (1 << IWX_RATE_MCS_HE_TYPE_POS) 5239#define IWX_RATE_MCS_HE_TYPE_MU (2 << IWX_RATE_MCS_HE_TYPE_POS) 5240#define IWX_RATE_MCS_HE_TYPE_TRIG (3 << IWX_RATE_MCS_HE_TYPE_POS) 5241#define IWX_RATE_MCS_HE_TYPE_MSK (3 << IWX_RATE_MCS_HE_TYPE_POS) 5242 5243/* Bit 25: duplicate channel enabled 5244 * 5245 * if this bit is set, duplicate is according to BW (bits 11-13): 5246 * 5247 * CCK: 2x 20MHz 5248 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 5249 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 5250 * */ 5251#define IWX_RATE_MCS_DUP_POS 25 5252#define IWX_RATE_MCS_DUP_MSK (1 << IWX_RATE_MCS_DUP_POS) 5253 5254/* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 5255#define IWX_RATE_MCS_HE_106T_POS 26 5256#define IWX_RATE_MCS_HE_106T_MSK (1 << IWX_RATE_MCS_HE_106T_POS) 5257 5258/* Bit 27: EHT extra LTF: 5259 * instead of 1 LTF for SISO use 2 LTFs, 5260 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 5261#define IWX_RATE_MCS_EHT_EXTRA_LTF_POS 27 5262#define IWX_RATE_MCS_EHT_EXTRA_LTF_MSK (1 << IWX_RATE_MCS_EHT_EXTRA_LTF_POS) 5263 5264/* Bit 31-28: reserved */ 5265 5266 5267/* Link Quality definitions */ 5268 5269/* # entries in rate scale table to support Tx retries */ 5270#define IWX_LQ_MAX_RETRY_NUM 16 5271 5272/* Link quality command flags bit fields */ 5273 5274/* Bit 0: (0) Don't use RTS (1) Use RTS */ 5275#define IWX_LQ_FLAG_USE_RTS_POS 0 5276#define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS) 5277 5278/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 5279#define IWX_LQ_FLAG_COLOR_POS 1 5280#define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS) 5281 5282/* Bit 4-5: Tx RTS BW Signalling 5283 * (0) No RTS BW signalling 5284 * (1) Static BW signalling 5285 * (2) Dynamic BW signalling 5286 */ 5287#define IWX_LQ_FLAG_RTS_BW_SIG_POS 4 5288#define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5289#define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5290#define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5291 5292/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 5293 * Dynamic BW selection allows Tx with narrower BW then requested in rates 5294 */ 5295#define IWX_LQ_FLAG_DYNAMIC_BW_POS 6 5296#define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS) 5297 5298#define IWX_RLC_CHAIN_INFO_DRIVER_FORCE (1 << 0) 5299#define IWL_RLC_CHAIN_INFO_VALID 0x000e 5300#define IWL_RLC_CHAIN_INFO_FORCE 0x0070 5301#define IWL_RLC_CHAIN_INFO_FORCE_MIMO 0x0380 5302#define IWL_RLC_CHAIN_INFO_COUNT 0x0c00 5303#define IWL_RLC_CHAIN_INFO_MIMO_COUNT 0x3000 5304 5305/** 5306 * struct iwx_rlc_properties - RLC properties 5307 * @rx_chain_info: RX chain info, IWX_RLC_CHAIN_INFO_* 5308 * @reserved: reserved 5309 */ 5310struct iwx_rlc_properties { 5311 uint32_t rx_chain_info; 5312 uint32_t reserved; 5313} __packed; /* RLC_PROPERTIES_S_VER_1 */ 5314 5315#define IWX_SAD_MODE_ENABLED (1 << 0) 5316#define IWX_SAD_MODE_DEFAULT_ANT_MSK 0x6 5317#define IWX_SAD_MODE_DEFAULT_ANT_FW 0x0 5318#define IWX_SAD_MODE_DEFAULT_ANT_A 0x2 5319#define IWX_SAD_MODE_DEFAULT_ANT_B 0x4 5320 5321/** 5322 * struct iwx_sad_properties - SAD properties 5323 * @chain_a_sad_mode: chain A SAD mode, IWX_SAD_MODE_* 5324 * @chain_b_sad_mode: chain B SAD mode, IWX_SAD_MODE_* 5325 * @mac_id: MAC index 5326 * @reserved: reserved 5327 */ 5328struct iwx_sad_properties { 5329 uint32_t chain_a_sad_mode; 5330 uint32_t chain_b_sad_mode; 5331 uint32_t mac_id; 5332 uint32_t reserved; 5333} __packed; 5334 5335/** 5336 * struct iwx_rlc_config_cmd - RLC configuration 5337 * @phy_id: PHY index 5338 * @rlc: RLC properties, &struct iwx_rlc_properties 5339 * @sad: SAD (single antenna diversity) options, &struct iwx_sad_properties 5340 * @flags: flags, IWX_RLC_FLAGS_* 5341 * @reserved: reserved 5342 */ 5343struct iwx_rlc_config_cmd { 5344 uint32_t phy_id; 5345 struct iwx_rlc_properties rlc; 5346 struct iwx_sad_properties sad; 5347 uint8_t flags; 5348 uint8_t reserved[3]; 5349} __packed; /* RLC_CONFIG_CMD_API_S_VER_2 */ 5350 5351#define IWX_MAX_BAID_OLD 16 /* MAX_IMMEDIATE_BA_API_D_VER_2 */ 5352#define IWX_MAX_BAID 32 /* MAX_IMMEDIATE_BA_API_D_VER_3 */ 5353 5354/** 5355 * BAID allocation/config action 5356 * @IWX_RX_BAID_ACTION_ADD: add a new BAID session 5357 * @IWX_RX_BAID_ACTION_MODIFY: modify the BAID session 5358 * @IWX_RX_BAID_ACTION_REMOVE: remove the BAID session 5359 */ 5360#define IWX_RX_BAID_ACTION_ADD 0 5361#define IWX_RX_BAID_ACTION_MODIFY 1 5362#define IWX_RX_BAID_ACTION_REMOVE 2 5363/* RX_BAID_ALLOCATION_ACTION_E_VER_1 */ 5364 5365/** 5366 * struct iwx_rx_baid_cfg_cmd_alloc - BAID allocation data 5367 * @sta_id_mask: station ID mask 5368 * @tid: the TID for this session 5369 * @reserved: reserved 5370 * @ssn: the starting sequence number 5371 * @win_size: RX BA session window size 5372 */ 5373struct iwx_rx_baid_cfg_cmd_alloc { 5374 uint32_t sta_id_mask; 5375 uint8_t tid; 5376 uint8_t reserved[3]; 5377 uint16_t ssn; 5378 uint16_t win_size; 5379} __packed; /* RX_BAID_ALLOCATION_ADD_CMD_API_S_VER_1 */ 5380 5381/** 5382 * struct iwx_rx_baid_cfg_cmd_modify - BAID modification data 5383 * @old_sta_id_mask: old station ID mask 5384 * @new_sta_id_mask: new station ID mask 5385 * @tid: TID of the BAID 5386 */ 5387struct iwx_rx_baid_cfg_cmd_modify { 5388 uint32_t old_sta_id_mask; 5389 uint32_t new_sta_id_mask; 5390 uint32_t tid; 5391} __packed; /* RX_BAID_ALLOCATION_MODIFY_CMD_API_S_VER_2 */ 5392 5393/** 5394 * struct iwx_rx_baid_cfg_cmd_remove_v1 - BAID removal data 5395 * @baid: the BAID to remove 5396 */ 5397struct iwx_rx_baid_cfg_cmd_remove_v1 { 5398 uint32_t baid; 5399} __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_1 */ 5400 5401/** 5402 * struct iwx_rx_baid_cfg_cmd_remove - BAID removal data 5403 * @sta_id_mask: the station mask of the BAID to remove 5404 * @tid: the TID of the BAID to remove 5405 */ 5406struct iwx_rx_baid_cfg_cmd_remove { 5407 uint32_t sta_id_mask; 5408 uint32_t tid; 5409} __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_2 */ 5410 5411/** 5412 * struct iwx_rx_baid_cfg_cmd - BAID allocation/config command 5413 * @action: the action, from &enum iwx_rx_baid_action 5414 */ 5415struct iwx_rx_baid_cfg_cmd { 5416 uint32_t action; 5417 union { 5418 struct iwx_rx_baid_cfg_cmd_alloc alloc; 5419 struct iwx_rx_baid_cfg_cmd_modify modify; 5420 struct iwx_rx_baid_cfg_cmd_remove_v1 remove_v1; 5421 struct iwx_rx_baid_cfg_cmd_remove remove; 5422 }; /* RX_BAID_ALLOCATION_OPERATION_API_U_VER_2 */ 5423} __packed; /* RX_BAID_ALLOCATION_CONFIG_CMD_API_S_VER_2 */ 5424 5425/** 5426 * struct iwx_rx_baid_cfg_resp - BAID allocation response 5427 * @baid: the allocated BAID 5428 */ 5429struct iwx_rx_baid_cfg_resp { 5430 uint32_t baid; 5431}; /* RX_BAID_ALLOCATION_RESPONSE_API_S_VER_1 */ 5432 5433/** 5434 * scheduler queue operation 5435 * @IWX_SCD_QUEUE_ADD: allocate a new queue 5436 * @IWX_SCD_QUEUE_REMOVE: remove a queue 5437 * @IWX_SCD_QUEUE_MODIFY: modify a queue 5438 */ 5439#define IWX_SCD_QUEUE_ADD 0 5440#define IWX_SCD_QUEUE_REMOVE 1 5441#define IWX_SCD_QUEUE_MODIFY 2 5442 5443/** 5444 * struct iwx_scd_queue_cfg_cmd - scheduler queue allocation command 5445 * @operation: the operation, see &enum iwl_scd_queue_cfg_operation 5446 * @u.add.sta_mask: station mask 5447 * @u.add.tid: TID 5448 * @u.add.reserved: reserved 5449 * @u.add.flags: flags from &enum iwl_tx_queue_cfg_actions, except 5450 * %TX_QUEUE_CFG_ENABLE_QUEUE is not valid 5451 * @u.add.cb_size: size code 5452 * @u.add.bc_dram_addr: byte-count table IOVA 5453 * @u.add.tfdq_dram_addr: TFD queue IOVA 5454 * @u.remove.sta_mask: station mask of queue to remove 5455 * @u.remove.tid: TID of queue to remove 5456 * @u.modify.old_sta_mask: old station mask for modify 5457 * @u.modify.tid: TID of queue to modify 5458 * @u.modify.new_sta_mask: new station mask for modify 5459 */ 5460struct iwx_scd_queue_cfg_cmd { 5461 uint32_t operation; 5462 union { 5463 struct { 5464 uint32_t sta_mask; 5465 uint8_t tid; 5466 uint8_t reserved[3]; 5467 uint32_t flags; 5468 uint32_t cb_size; 5469 uint64_t bc_dram_addr; 5470 uint64_t tfdq_dram_addr; 5471 } __packed add; /* TX_QUEUE_CFG_CMD_ADD_API_S_VER_1 */ 5472 struct { 5473 uint32_t sta_mask; 5474 uint32_t tid; 5475 } __packed remove; /* TX_QUEUE_CFG_CMD_REMOVE_API_S_VER_1 */ 5476 struct { 5477 uint32_t old_sta_mask; 5478 uint32_t tid; 5479 uint32_t new_sta_mask; 5480 } __packed modify; /* TX_QUEUE_CFG_CMD_MODIFY_API_S_VER_1 */ 5481 } __packed u; /* TX_QUEUE_CFG_CMD_OPERATION_API_U_VER_1 */ 5482} __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_3 */ 5483 5484/** 5485 * Options for TLC config flags 5486 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 5487 * bandwidths <= 80MHz 5488 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 5489 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 5490 * bandwidth 5491 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 5492 * for BPSK (MCS 0) with 1 spatial 5493 * stream 5494 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 5495 * for BPSK (MCS 0) with 2 spatial 5496 * streams 5497 */ 5498#define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0) 5499#define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1) 5500#define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2) 5501#define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3) 5502#define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4) 5503 5504/** 5505 * enum iwx_tlc_mng_cfg_cw - channel width options 5506 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 5507 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 5508 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 5509 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 5510 * @IWX_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 5511 */ 5512enum iwx_tlc_mng_cfg_cw { 5513 IWX_TLC_MNG_CH_WIDTH_20MHZ, 5514 IWX_TLC_MNG_CH_WIDTH_40MHZ, 5515 IWX_TLC_MNG_CH_WIDTH_80MHZ, 5516 IWX_TLC_MNG_CH_WIDTH_160MHZ, 5517 IWX_TLC_MNG_CH_WIDTH_320MHZ, 5518}; 5519 5520/** 5521 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A 5522 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B 5523 */ 5524#define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0) 5525#define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1) 5526 5527/** 5528 * enum iwx_tlc_mng_cfg_mode - supported modes 5529 * @IWX_TLC_MNG_MODE_CCK: enable CCK 5530 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 5531 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT 5532 * @IWX_TLC_MNG_MODE_HT: enable HT 5533 * @IWX_TLC_MNG_MODE_VHT: enable VHT 5534 * @IWX_TLC_MNG_MODE_HE: enable HE 5535 * @IWX_TLC_MNG_MODE_EHT: enable EHT 5536 */ 5537enum iwx_tlc_mng_cfg_mode { 5538 IWX_TLC_MNG_MODE_CCK = 0, 5539 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK, 5540 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK, 5541 IWX_TLC_MNG_MODE_HT, 5542 IWX_TLC_MNG_MODE_VHT, 5543 IWX_TLC_MNG_MODE_HE, 5544 IWX_TLC_MNG_MODE_EHT, 5545}; 5546 5547/** 5548 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0 5549 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1 5550 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2 5551 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3 5552 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4 5553 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5 5554 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6 5555 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7 5556 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8 5557 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9 5558 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10 5559 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11 5560 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 5561 */ 5562enum iwx_tlc_mng_ht_rates { 5563 IWX_TLC_MNG_HT_RATE_MCS0 = 0, 5564 IWX_TLC_MNG_HT_RATE_MCS1, 5565 IWX_TLC_MNG_HT_RATE_MCS2, 5566 IWX_TLC_MNG_HT_RATE_MCS3, 5567 IWX_TLC_MNG_HT_RATE_MCS4, 5568 IWX_TLC_MNG_HT_RATE_MCS5, 5569 IWX_TLC_MNG_HT_RATE_MCS6, 5570 IWX_TLC_MNG_HT_RATE_MCS7, 5571 IWX_TLC_MNG_HT_RATE_MCS8, 5572 IWX_TLC_MNG_HT_RATE_MCS9, 5573 IWX_TLC_MNG_HT_RATE_MCS10, 5574 IWX_TLC_MNG_HT_RATE_MCS11, 5575 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11, 5576}; 5577 5578#define IWX_TLC_NSS_1 0 5579#define IWX_TLC_NSS_2 1 5580#define IWX_TLC_NSS_MAX 2 5581 5582 5583/** 5584 * IWX_TLC_MCS_PER_BW - mcs index per BW 5585 * @IWX_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 5586 * @IWX_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 5587 * @IWX_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 5588 * @IWX_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 5589 * @IWX_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 5590 */ 5591#define IWX_TLC_MCS_PER_BW_80 0 5592#define IWX_TLC_MCS_PER_BW_160 1 5593#define IWX_TLC_MCS_PER_BW_320 2 5594#define IWX_TLC_MCS_PER_BW_NUM_V3 (IWX_TLC_MCS_PER_BW_160 + 1) 5595#define IWX_TLC_MCS_PER_BW_NUM_V4 (IWX_TLC_MCS_PER_BW_320 + 1) 5596 5597/** 5598 * struct iwx_tlc_config_cmd_v3 - TLC configuration version 3 5599 * @sta_id: station id 5600 * @reserved1: reserved 5601 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 5602 * @mode: &enum iwx_tlc_mng_cfg_mode 5603 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 5604 * @amsdu: 1 = TX amsdu is supported, 0 = not supported 5605 * @flags: bitmask of IWX_TLC_MNG_CFG_* 5606 * @non_ht_rates: bitmap of supported legacy rates 5607 * @ht_rates: MCS index 0 - 11, per <nss, channel-width> 5608 * pair (0 - 80mhz width and below, 1 - 160mhz). 5609 * @max_mpdu_len: max MPDU length, in bytes 5610 * @sgi_ch_width_supp: bitmap of SGI support per channel width 5611 * use (1 << IWX_TLC_MNG_CFG_CW_*) 5612 * @reserved2: reserved 5613 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 5614 * set zero for no limit. 5615 */ 5616struct iwx_tlc_config_cmd_v3 { 5617 uint8_t sta_id; 5618 uint8_t reserved1[3]; 5619 uint8_t max_ch_width; 5620 uint8_t mode; 5621 uint8_t chains; 5622 uint8_t amsdu; 5623 uint16_t flags; 5624 uint16_t non_ht_rates; 5625 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V3]; 5626 uint16_t max_mpdu_len; 5627 uint8_t sgi_ch_width_supp; 5628 uint8_t reserved2; 5629 uint32_t max_tx_op; 5630} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 5631 5632/** 5633 * struct iwx_tlc_config_cmd_v4 - TLC configuration 5634 * @sta_id: station id 5635 * @reserved1: reserved 5636 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 5637 * @mode: &enum iwx_tlc_mng_cfg_mode 5638 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 5639 * @sgi_ch_width_supp: bitmap of SGI support per channel width 5640 * use (1 << IWX_TLC_MNG_CFG_CW_*) 5641 * @flags: bitmask of IWX_TLC_MNG_CFG_* 5642 * @non_ht_rates: bitmap of supported legacy rates 5643 * @ht_rates: MCS index 0 - 11, per <nss, channel-width> 5644 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 5645 * @max_mpdu_len: max MPDU length, in bytes 5646 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 5647 * set zero for no limit. 5648 */ 5649struct iwx_tlc_config_cmd_v4 { 5650 uint8_t sta_id; 5651 uint8_t reserved1[3]; 5652 uint8_t max_ch_width; 5653 uint8_t mode; 5654 uint8_t chains; 5655 uint8_t sgi_ch_width_supp; 5656 uint16_t flags; 5657 uint16_t non_ht_rates; 5658 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V4]; 5659 uint16_t max_mpdu_len; 5660 uint16_t max_tx_op; 5661} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 5662 5663/** 5664 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update 5665 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 5666 */ 5667#define IWX_TLC_NOTIF_FLAG_RATE (1 << 0) 5668#define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1) 5669 5670/** 5671 * struct iwx_tlc_update_notif - TLC notification from FW 5672 * @sta_id: station id 5673 * @reserved: reserved 5674 * @flags: bitmap of notifications reported 5675 * @rate: current initial rate; using rate_n_flags version 1 if notification 5676 * version is < 3 at run-time, else rate_n_flags version 2 5677 * @amsdu_size: Max AMSDU size, in bytes 5678 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 5679 */ 5680struct iwx_tlc_update_notif { 5681 uint8_t sta_id; 5682 uint8_t reserved[3]; 5683 uint32_t flags; 5684 uint32_t rate; 5685 uint32_t amsdu_size; 5686 uint32_t amsdu_enabled; 5687} __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */ 5688 5689/* Antenna flags. */ 5690#define IWX_ANT_A (1 << 0) 5691#define IWX_ANT_B (1 << 1) 5692#define IWX_ANT_C (1 << 2) 5693/* Shortcuts. */ 5694#define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B) 5695#define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C) 5696#define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C) 5697 5698/* 5699 * TX command security control 5700 */ 5701#define IWX_TX_CMD_SEC_WEP 0x01 5702#define IWX_TX_CMD_SEC_CCM 0x02 5703#define IWX_TX_CMD_SEC_TKIP 0x03 5704#define IWX_TX_CMD_SEC_EXT 0x04 5705#define IWX_TX_CMD_SEC_MSK 0x07 5706#define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6 5707#define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 5708#define IWX_TX_CMD_SEC_KEY128 0x08 5709 5710/* TODO: how does these values are OK with only 16 bit variable??? */ 5711/* 5712 * TX command next frame info 5713 * 5714 * bits 0:2 - security control (IWX_TX_CMD_SEC_*) 5715 * bit 3 - immediate ACK required 5716 * bit 4 - rate is taken from STA table 5717 * bit 5 - frame belongs to BA stream 5718 * bit 6 - immediate BA response expected 5719 * bit 7 - unused 5720 * bits 8:15 - Station ID 5721 * bits 16:31 - rate 5722 */ 5723#define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 5724#define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 5725#define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 5726#define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 5727#define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 5728#define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 5729#define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 5730#define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 5731#define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16) 5732 5733/* 5734 * TX command Frame life time in us - to be written in pm_frame_timeout 5735 */ 5736#define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 5737#define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 5738#define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 5739#define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 5740 5741/* 5742 * TID for non QoS frames - to be written in tid_tspec 5743 */ 5744#define IWX_TID_NON_QOS 0 5745 5746/* 5747 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 5748 */ 5749#define IWX_DEFAULT_TX_RETRY 15 5750#define IWX_MGMT_DFAULT_RETRY_LIMIT 3 5751#define IWX_RTS_DFAULT_RETRY_LIMIT 3 5752#define IWX_BAR_DFAULT_RETRY_LIMIT 60 5753#define IWX_LOW_RETRY_LIMIT 7 5754 5755/* 5756 * The FH will write back to the first TB only, so we need to copy some data 5757 * into the buffer regardless of whether it should be mapped or not. 5758 * This indicates how big the first TB must be to include the scratch buffer 5759 * and the assigned PN. 5760 * Since PN location is 8 bytes at offset 12, it's 20 now. 5761 * If we make it bigger then allocations will be bigger and copy slower, so 5762 * that's probably not useful. 5763 */ 5764#define IWX_FIRST_TB_SIZE 20 5765#define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1)) 5766 5767/** 5768 * %iwx_tx_cmd offload_assist values 5769 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 5770 * from mac header end. For normal case it is 4 words for SNAP. 5771 * note: tx_cmd, mac header and pad are not counted in the offset. 5772 * This is used to help the offload in case there is tunneling such as 5773 * IPv6 in IPv4, in such case the ip header offset should point to the 5774 * inner ip header and IPv4 checksum of the external header should be 5775 * calculated by driver. 5776 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 5777 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 5778 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 5779 * field. Doesn't include the pad. 5780 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 5781 * alignment 5782 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 5783 */ 5784#define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0) 5785#define IWX_TX_CMD_OFFLD_L4_EN (1 << 6) 5786#define IWX_TX_CMD_OFFLD_L3_EN (1 << 7) 5787#define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8) 5788#define IWX_TX_CMD_OFFLD_PAD (1 << 13) 5789#define IWX_TX_CMD_OFFLD_AMSDU (1 << 14) 5790#define IWX_TX_CMD_OFFLD_MH_MASK 0x1f 5791#define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f 5792 5793struct iwx_dram_sec_info { 5794 uint32_t pn_low; 5795 uint16_t pn_high; 5796 uint16_t aux_info; 5797} __packed; /* DRAM_SEC_INFO_API_S_VER_1 */ 5798 5799/** 5800 * bitmasks for tx_flags in TX command for 22000 5801 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command 5802 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs 5803 * to a secured STA 5804 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate 5805 * selection, retry limits and BT kill 5806 */ 5807/* Valid for TX_FLAGS_BITS_API_S_VER_3: */ 5808#define IWX_TX_FLAGS_CMD_RATE (1 << 0) 5809#define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1) 5810#define IWX_TX_FLAGS_HIGH_PRI (1 << 2) 5811/* Valid for TX_FLAGS_BITS_API_S_VER_4 and above: */ 5812#define IWX_TX_FLAGS_RTS (1 << 3) 5813#define IWX_TX_FLAGS_CTS (1 << 4) 5814/* TX_FLAGS_BITS_API_S_VER_4 */ 5815 5816/** 5817 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices 5818 * ( TX_CMD = 0x1c ) 5819 * @len: in bytes of the payload, see below for details 5820 * @offload_assist: TX offload configuration 5821 * @flags: combination of TX_FLAGS_* 5822 * @dram_info: FW internal DRAM storage 5823 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5824 * cleared. Combination of RATE_MCS_* 5825 * @hdr: 802.11 header 5826 */ 5827struct iwx_tx_cmd_gen2 { 5828 uint16_t len; 5829 uint16_t offload_assist; 5830 uint32_t flags; 5831 struct iwx_dram_sec_info dram_info; 5832 uint32_t rate_n_flags; 5833 struct ieee80211_frame hdr[0]; 5834} __packed; /* TX_CMD_API_S_VER_7, 5835 TX_CMD_API_S_VER_9 */ 5836 5837/** 5838 * struct iwx_tx_cmd_gen3 - TX command struct to FW for AX210+ devices 5839 * ( TX_CMD = 0x1c ) 5840 * @len: in bytes of the payload, see below for details 5841 * @flags: combination of TX_FLAGS_* 5842 * @offload_assist: TX offload configuration 5843 * @dram_info: FW internal DRAM storage 5844 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5845 * cleared. Combination of RATE_MCS_* 5846 * @reserved: reserved 5847 * @hdr: 802.11 header 5848 */ 5849struct iwx_tx_cmd_gen3 { 5850 uint16_t len; 5851 uint16_t flags; 5852 uint32_t offload_assist; 5853 struct iwx_dram_sec_info dram_info; 5854 uint32_t rate_n_flags; 5855 uint8_t reserved[8]; 5856 struct ieee80211_frame hdr[]; 5857} __packed; /* TX_CMD_API_S_VER_8, 5858 TX_CMD_API_S_VER_10 */ 5859 5860/* 5861 * TX response related data 5862 */ 5863 5864/* 5865 * status that is returned by the fw after attempts to Tx 5866 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 5867 * STA table 5868 * Valid only if frame_count =1 5869 */ 5870#define IWX_TX_STATUS_MSK 0x000000ff 5871#define IWX_TX_STATUS_SUCCESS 0x01 5872#define IWX_TX_STATUS_DIRECT_DONE 0x02 5873/* postpone TX */ 5874#define IWX_TX_STATUS_POSTPONE_DELAY 0x40 5875#define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41 5876#define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42 5877#define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 5878#define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44 5879/* abort TX */ 5880#define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 5881#define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82 5882#define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83 5883#define IWX_TX_STATUS_FAIL_UNDERRUN 0x84 5884#define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85 5885#define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 5886#define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 5887#define IWX_TX_STATUS_FAIL_DEST_PS 0x88 5888#define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89 5889#define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a 5890#define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b 5891#define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 5892#define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d 5893#define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 5894#define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 5895#define IWX_TX_STATUS_FAIL_FW_DROP 0x90 5896#define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 5897#define IWX_TX_STATUS_INTERNAL_ABORT 0x92 5898#define IWX_TX_MODE_MSK 0x00000f00 5899#define IWX_TX_MODE_NO_BURST 0x00000000 5900#define IWX_TX_MODE_IN_BURST_SEQ 0x00000100 5901#define IWX_TX_MODE_FIRST_IN_BURST 0x00000200 5902#define IWX_TX_QUEUE_NUM_MSK 0x0001f000 5903#define IWX_TX_NARROW_BW_MSK 0x00060000 5904#define IWX_TX_NARROW_BW_1DIV2 0x00020000 5905#define IWX_TX_NARROW_BW_1DIV4 0x00040000 5906#define IWX_TX_NARROW_BW_1DIV8 0x00060000 5907 5908/* 5909 * TX aggregation status 5910 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 5911 * occur if tx failed for this frame when it was a member of a previous 5912 * aggregation block). If rate scaling is used, retry count indicates the 5913 * rate table entry used for all frames in the new agg. 5914 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 5915 * this frame 5916 */ 5917#define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff 5918#define IWX_AGG_TX_STATE_TRANSMITTED 0x0000 5919#define IWX_AGG_TX_STATE_UNDERRUN 0x0001 5920#define IWX_AGG_TX_STATE_BT_PRIO 0x0002 5921#define IWX_AGG_TX_STATE_FEW_BYTES 0x0004 5922#define IWX_AGG_TX_STATE_ABORT 0x0008 5923#define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010 5924#define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 5925#define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 5926#define IWX_AGG_TX_STATE_SCD_QUERY 0x0080 5927#define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 5928#define IWX_AGG_TX_STATE_RESPONSE 0x01ff 5929#define IWX_AGG_TX_STATE_DUMP_TX 0x0200 5930#define IWX_AGG_TX_STATE_DELAY_TX 0x0400 5931#define IWX_AGG_TX_STATE_TRY_CNT_POS 12 5932#define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS) 5933 5934#define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \ 5935 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 5936 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL) 5937 5938/* 5939 * The mask below describes a status where we are absolutely sure that the MPDU 5940 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 5941 * written the bytes to the TXE, but we know nothing about what the DSP did. 5942 */ 5943#define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \ 5944 IWX_AGG_TX_STATE_ABORT | \ 5945 IWX_AGG_TX_STATE_SCD_QUERY) 5946 5947/* 5948 * IWX_REPLY_TX = 0x1c (response) 5949 * 5950 * This response may be in one of two slightly different formats, indicated 5951 * by the frame_count field: 5952 * 5953 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 5954 * frame. Multiple attempts, at various bit rates, may have been made for 5955 * this frame. 5956 * 5957 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 5958 * frames that used block-acknowledge. All frames were transmitted at 5959 * same rate. Rate scaling may have been used if first frame in this new 5960 * agg block failed in previous agg block(s). 5961 * 5962 * Note that, for aggregation, ACK (block-ack) status is not delivered 5963 * here; block-ack has not been received by the time the device records 5964 * this status. 5965 * This status relates to reasons the tx might have been blocked or aborted 5966 * within the device, rather than whether it was received successfully by 5967 * the destination station. 5968 */ 5969 5970/** 5971 * struct iwx_agg_tx_status - per packet TX aggregation status 5972 * @status: enum iwx_tx_agg_status 5973 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 5974 */ 5975struct iwx_agg_tx_status { 5976 uint16_t status; 5977 uint16_t sequence; 5978} __packed; 5979 5980/* 5981 * definitions for initial rate index field 5982 * bits [3:0] initial rate index 5983 * bits [6:4] rate table color, used for the initial rate 5984 * bit-7 invalid rate indication 5985 */ 5986#define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f 5987#define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70 5988#define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80 5989 5990#define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 5991#define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 5992 5993/** 5994 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet 5995 * ( IWX_REPLY_TX = 0x1c ) 5996 * @frame_count: 1 no aggregation, >1 aggregation 5997 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5998 * @failure_rts: num of failures due to unsuccessful RTS 5999 * @failure_frame: num failures due to no ACK (unused for agg) 6000 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 6001 * Tx of all the batch. IWX_RATE_MCS_* 6002 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 6003 * for agg: RTS + CTS + aggregation tx time + block-ack time. 6004 * in usec. 6005 * @pa_status: tx power info 6006 * @pa_integ_res_a: tx power info 6007 * @pa_integ_res_b: tx power info 6008 * @pa_integ_res_c: tx power info 6009 * @measurement_req_id: tx power info 6010 * @tfd_info: TFD information set by the FH 6011 * @seq_ctl: sequence control from the Tx cmd 6012 * @byte_cnt: byte count from the Tx cmd 6013 * @tlc_info: TLC rate info 6014 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 6015 * @frame_ctrl: frame control 6016 * @status: for non-agg: frame status IWX_TX_STATUS_* 6017 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields 6018 * follow this one, up to frame_count. 6019 * 6020 * After the array of statuses comes the SSN of the SCD. Look at 6021 * %iwx_get_scd_ssn for more details. 6022 */ 6023struct iwx_tx_resp_v3 { 6024 uint8_t frame_count; 6025 uint8_t bt_kill_count; 6026 uint8_t failure_rts; 6027 uint8_t failure_frame; 6028 uint32_t initial_rate; 6029 uint16_t wireless_media_time; 6030 6031 uint8_t pa_status; 6032 uint8_t pa_integ_res_a[3]; 6033 uint8_t pa_integ_res_b[3]; 6034 uint8_t pa_integ_res_c[3]; 6035 uint16_t measurement_req_id; 6036 uint16_t reserved; 6037 6038 uint32_t tfd_info; 6039 uint16_t seq_ctl; 6040 uint16_t byte_cnt; 6041 uint8_t tlc_info; 6042 uint8_t ra_tid; 6043 uint16_t frame_ctrl; 6044 6045 struct iwx_agg_tx_status status; 6046} __packed; /* IWX_TX_RSP_API_S_VER_3 */ 6047 6048/** 6049 * struct iwx_tx_resp - notifies that fw is TXing a packet 6050 * ( REPLY_TX = 0x1c ) 6051 * @frame_count: 1 no aggregation, >1 aggregation 6052 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 6053 * @failure_rts: num of failures due to unsuccessful RTS 6054 * @failure_frame: num failures due to no ACK (unused for agg) 6055 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 6056 * Tx of all the batch. RATE_MCS_* 6057 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 6058 * for agg: RTS + CTS + aggregation tx time + block-ack time. 6059 * in usec. 6060 * @pa_status: tx power info 6061 * @pa_integ_res_a: tx power info 6062 * @pa_integ_res_b: tx power info 6063 * @pa_integ_res_c: tx power info 6064 * @measurement_req_id: tx power info 6065 * @reduced_tpc: transmit power reduction used 6066 * @reserved: reserved 6067 * @tfd_info: TFD information set by the FH 6068 * @seq_ctl: sequence control from the Tx cmd 6069 * @byte_cnt: byte count from the Tx cmd 6070 * @tlc_info: TLC rate info 6071 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 6072 * @frame_ctrl: frame control 6073 * @tx_queue: TX queue for this response 6074 * @reserved2: reserved for padding/alignment 6075 * @status: for non-agg: frame status TX_STATUS_* 6076 * For version 6 TX response isn't received for aggregation at all. 6077 * 6078 * After the array of statuses comes the SSN of the SCD. Look at 6079 * %iwl_mvm_get_scd_ssn for more details. 6080 */ 6081struct iwx_tx_resp { 6082 uint8_t frame_count; 6083 uint8_t bt_kill_count; 6084 uint8_t failure_rts; 6085 uint8_t failure_frame; 6086 uint32_t initial_rate; 6087 uint16_t wireless_media_time; 6088 6089 uint8_t pa_status; 6090 uint8_t pa_integ_res_a[3]; 6091 uint8_t pa_integ_res_b[3]; 6092 uint8_t pa_integ_res_c[3]; 6093 uint16_t measurement_req_id; 6094 uint8_t reduced_tpc; 6095 uint8_t reserved; 6096 6097 uint32_t tfd_info; 6098 uint16_t seq_ctl; 6099 uint16_t byte_cnt; 6100 uint8_t tlc_info; 6101 uint8_t ra_tid; 6102 uint16_t frame_ctrl; 6103 uint16_t tx_queue; 6104 uint16_t reserved2; 6105 struct iwx_agg_tx_status status; 6106} __packed; /* TX_RSP_API_S_VER_6 */ 6107 6108/** 6109 * struct iwx_compressed_ba_tfd - progress of a TFD queue 6110 * @q_num: TFD queue number 6111 * @tfd_index: Index of first un-acked frame in the TFD queue 6112 * @scd_queue: For debug only - the physical queue the TFD queue is bound to 6113 * @tid: TID of the queue (0-7) 6114 * @reserved: reserved for alignment 6115 */ 6116struct iwx_compressed_ba_tfd { 6117 uint16_t q_num; 6118 uint16_t tfd_index; 6119 uint8_t scd_queue; 6120 uint8_t tid; 6121 uint8_t reserved[2]; 6122} __packed; /* COMPRESSED_BA_TFD_API_S_VER_1 */ 6123 6124/** 6125 * struct iwx_compressed_ba_ratid - progress of a RA TID queue 6126 * @q_num: RA TID queue number 6127 * @tid: TID of the queue 6128 * @ssn: BA window current SSN 6129 */ 6130struct iwx_compressed_ba_ratid { 6131 uint8_t q_num; 6132 uint8_t tid; 6133 uint16_t ssn; 6134} __packed; /* COMPRESSED_BA_RATID_API_S_VER_1 */ 6135 6136/* 6137 * enum iwx_ba_resp_flags - TX aggregation status 6138 * @IWX_MVM_BA_RESP_TX_AGG: generated due to BA 6139 * @IWX_MVM_BA_RESP_TX_BAR: generated due to BA after BAR 6140 * @IWX_MVM_BA_RESP_TX_AGG_FAIL: aggregation didn't receive BA 6141 * @IWX_MVM_BA_RESP_TX_UNDERRUN: aggregation got underrun 6142 * @IWX_MVM_BA_RESP_TX_BT_KILL: aggregation got BT-kill 6143 * @IWX_MVM_BA_RESP_TX_DSP_TIMEOUT: aggregation didn't finish within the 6144 * expected time 6145 */ 6146enum iwx_ba_resp_flags { 6147 IWX_MVM_BA_RESP_TX_AGG, 6148 IWX_MVM_BA_RESP_TX_BAR, 6149 IWX_MVM_BA_RESP_TX_AGG_FAIL, 6150 IWX_MVM_BA_RESP_TX_UNDERRUN, 6151 IWX_MVM_BA_RESP_TX_BT_KILL, 6152 IWX_MVM_BA_RESP_TX_DSP_TIMEOUT 6153}; 6154 6155/** 6156 * struct iwx_compressed_ba_notif - notifies about reception of BA 6157 * ( BA_NOTIF = 0xc5 ) 6158 * @flags: status flag, see the &iwx_ba_resp_flags 6159 * @sta_id: Index of recipient (BA-sending) station in fw's station table 6160 * @reduced_txp: power reduced according to TPC. This is the actual value and 6161 * not a copy from the LQ command. Thus, if not the first rate was used 6162 * for Tx-ing then this value will be set to 0 by FW. 6163 * @tlc_rate_info: TLC rate info, initial rate index, TLC table color 6164 * @retry_cnt: retry count 6165 * @query_byte_cnt: SCD query byte count 6166 * @query_frame_cnt: SCD query frame count 6167 * @txed: number of frames sent in the aggregation (all-TIDs) 6168 * @done: number of frames that were Acked by the BA (all-TIDs) 6169 * @reserved: reserved (for alignment) 6170 * @wireless_time: Wireless-media time 6171 * @tx_rate: the rate the aggregation was sent at 6172 * @tfd_cnt: number of TFD-Q elements 6173 * @ra_tid_cnt: number of RATID-Q elements 6174 * @tfd: array of TFD queue status updates. See &iwx_compressed_ba_tfd 6175 * for details. Length in @tfd_cnt. 6176 * @ra_tid: array of RA-TID queue status updates. For debug purposes only. See 6177 * &iwx_compressed_ba_ratid for more details. Length in @ra_tid_cnt. 6178 */ 6179struct iwx_compressed_ba_notif { 6180 uint32_t flags; 6181 uint8_t sta_id; 6182 uint8_t reduced_txp; 6183 uint8_t tlc_rate_info; 6184 uint8_t retry_cnt; 6185 uint32_t query_byte_cnt; 6186 uint16_t query_frame_cnt; 6187 uint16_t txed; 6188 uint16_t done; 6189 uint16_t reserved; 6190 uint32_t wireless_time; 6191 uint32_t tx_rate; 6192 uint16_t tfd_cnt; 6193 uint16_t ra_tid_cnt; 6194 struct iwx_compressed_ba_ratid ra_tid[0]; 6195 struct iwx_compressed_ba_tfd tfd[]; 6196} __packed; /* COMPRESSED_BA_RES_API_S_VER_4 */ 6197 6198 6199struct iwx_beacon_notif { 6200 struct iwx_tx_resp_v3 beacon_notify_hdr; 6201 uint64_t tsf; 6202 uint32_t ibss_mgr_status; 6203} __packed; 6204 6205/** 6206 * dump (flush) control flags 6207 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 6208 * and the TFD queues are empty. 6209 */ 6210#define IWX_DUMP_TX_FIFO_FLUSH (1 << 1) 6211 6212/** 6213 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command 6214 * @queues_ctl: bitmap of queues to flush 6215 * @flush_ctl: control flags 6216 * @reserved: reserved 6217 */ 6218struct iwx_tx_path_flush_cmd_v1 { 6219 uint32_t queues_ctl; 6220 uint16_t flush_ctl; 6221 uint16_t reserved; 6222} __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 6223 6224/** 6225 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 6226 * @sta_id: station ID to flush 6227 * @tid_mask: TID mask to flush 6228 * @reserved: reserved 6229 */ 6230struct iwx_tx_path_flush_cmd { 6231 uint32_t sta_id; 6232 uint16_t tid_mask; 6233 uint16_t reserved; 6234} __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 6235 6236#define IWX_TX_FLUSH_QUEUE_RSP 16 6237 6238/** 6239 * struct iwx_flush_queue_info - virtual flush queue info 6240 * @queue_num: virtual queue id 6241 * @read_before_flush: read pointer before flush 6242 * @read_after_flush: read pointer after flush 6243 */ 6244struct iwx_flush_queue_info { 6245 uint16_t tid; 6246 uint16_t queue_num; 6247 uint16_t read_before_flush; 6248 uint16_t read_after_flush; 6249} __packed; /* TFDQ_FLUSH_INFO_API_S_VER_1 */ 6250 6251/** 6252 * struct iwx_tx_path_flush_cmd_rsp -- queue/FIFO flush command response 6253 * @num_flushed_queues: number of queues in queues array 6254 * @queues: all flushed queues 6255 */ 6256struct iwx_tx_path_flush_cmd_rsp { 6257 uint16_t sta_id; 6258 uint16_t num_flushed_queues; 6259 struct iwx_flush_queue_info queues[IWX_TX_FLUSH_QUEUE_RSP]; 6260} __packed; /* TX_PATH_FLUSH_CMD_RSP_API_S_VER_1 */ 6261 6262 6263/** 6264 * iwx_get_scd_ssn - returns the SSN of the SCD 6265 * @tx_resp: the Tx response from the fw (agg or non-agg) 6266 * 6267 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 6268 * it can't know that everything will go well until the end of the AMPDU, it 6269 * can't know in advance the number of MPDUs that will be sent in the current 6270 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 6271 * Hence, it can't know in advance what the SSN of the SCD will be at the end 6272 * of the batch. This is why the SSN of the SCD is written at the end of the 6273 * whole struct at a variable offset. This function knows how to cope with the 6274 * variable offset and returns the SSN of the SCD. 6275 */ 6276static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp) 6277{ 6278 return le32_to_cpup((uint32_t *)&tx_resp->status + 6279 tx_resp->frame_count) & 0xfff; 6280} 6281 6282/** 6283 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command 6284 * @token: 6285 * @sta_id: station id 6286 * @tid: 6287 * @scd_queue: scheduler queue to config 6288 * @enable: 1 queue enable, 0 queue disable 6289 * @aggregate: 1 aggregated queue, 0 otherwise 6290 * @tx_fifo: %enum iwx_tx_fifo 6291 * @window: BA window size 6292 * @ssn: SSN for the BA agreement 6293 */ 6294struct iwx_scd_txq_cfg_cmd { 6295 uint8_t token; 6296 uint8_t sta_id; 6297 uint8_t tid; 6298 uint8_t scd_queue; 6299 uint8_t enable; 6300 uint8_t aggregate; 6301 uint8_t tx_fifo; 6302 uint8_t window; 6303 uint16_t ssn; 6304 uint16_t reserved; 6305} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 6306 6307/** 6308 * struct iwx_scd_txq_cfg_rsp 6309 * @token: taken from the command 6310 * @sta_id: station id from the command 6311 * @tid: tid from the command 6312 * @scd_queue: scd_queue from the command 6313 */ 6314struct iwx_scd_txq_cfg_rsp { 6315 uint8_t token; 6316 uint8_t sta_id; 6317 uint8_t tid; 6318 uint8_t scd_queue; 6319} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 6320 6321 6322/* Scan Commands, Responses, Notifications */ 6323 6324/* Max number of IEs for direct SSID scans in a command */ 6325#define IWX_PROBE_OPTION_MAX 20 6326 6327/** 6328 * struct iwx_ssid_ie - directed scan network information element 6329 * 6330 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD, 6331 * selected by "type" bit field in struct iwx_scan_channel; 6332 * each channel may select different ssids from among the 20 entries. 6333 * SSID IEs get transmitted in reverse order of entry. 6334 */ 6335struct iwx_ssid_ie { 6336 uint8_t id; 6337 uint8_t len; 6338 uint8_t ssid[IEEE80211_NWID_LEN]; 6339} __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 6340 6341/* scan offload */ 6342#define IWX_SCAN_MAX_BLACKLIST_LEN 64 6343#define IWX_SCAN_SHORT_BLACKLIST_LEN 16 6344#define IWX_SCAN_MAX_PROFILES 11 6345#define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 6346 6347/* Default watchdog (in MS) for scheduled scan iteration */ 6348#define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 6349 6350#define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 6351#define IWX_CAN_ABORT_STATUS 1 6352 6353#define IWX_FULL_SCAN_MULTIPLIER 5 6354#define IWX_FAST_SCHED_SCAN_ITERATIONS 3 6355#define IWX_MAX_SCHED_SCAN_PLANS 2 6356 6357/** 6358 * iwx_scan_schedule_lmac - schedule of scan offload 6359 * @delay: delay between iterations, in seconds. 6360 * @iterations: num of scan iterations 6361 * @full_scan_mul: number of partial scans before each full scan 6362 */ 6363struct iwx_scan_schedule_lmac { 6364 uint16_t delay; 6365 uint8_t iterations; 6366 uint8_t full_scan_mul; 6367} __packed; /* SCAN_SCHEDULE_API_S */ 6368 6369/** 6370 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 6371 * @tx_flags: combination of TX_CMD_FLG_* 6372 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 6373 * cleared. Combination of RATE_MCS_* 6374 * @sta_id: index of destination station in FW station table 6375 * @reserved: for alignment and future use 6376 */ 6377struct iwx_scan_req_tx_cmd { 6378 uint32_t tx_flags; 6379 uint32_t rate_n_flags; 6380 uint8_t sta_id; 6381 uint8_t reserved[3]; 6382} __packed; 6383 6384#define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 6385#define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 6386 6387/** 6388 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 6389 * @flags: bits 1-20: directed scan to i'th ssid 6390 * other bits &enum iwx_scan_channel_flags_lmac 6391 * @channel_number: channel number 1-13 etc 6392 * @iter_count: scan iteration on this channel 6393 * @iter_interval: interval in seconds between iterations on one channel 6394 */ 6395struct iwx_scan_channel_cfg_lmac { 6396 uint32_t flags; 6397 uint16_t channel_num; 6398 uint16_t iter_count; 6399 uint32_t iter_interval; 6400} __packed; 6401 6402/* 6403 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 6404 * @offset: offset in the data block 6405 * @len: length of the segment 6406 */ 6407struct iwx_scan_probe_segment { 6408 uint16_t offset; 6409 uint16_t len; 6410} __packed; 6411 6412/* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 6413 * @mac_header: first (and common) part of the probe 6414 * @band_data: band specific data 6415 * @common_data: last (and common) part of the probe 6416 * @buf: raw data block 6417 */ 6418struct iwx_scan_probe_req_v1 { 6419 struct iwx_scan_probe_segment mac_header; 6420 struct iwx_scan_probe_segment band_data[2]; 6421 struct iwx_scan_probe_segment common_data; 6422 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 6423} __packed; 6424 6425/* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 6426 * @mac_header: first (and common) part of the probe 6427 * @band_data: band specific data 6428 * @common_data: last (and common) part of the probe 6429 * @buf: raw data block 6430 */ 6431struct iwx_scan_probe_req { 6432 struct iwx_scan_probe_segment mac_header; 6433 struct iwx_scan_probe_segment band_data[3]; 6434 struct iwx_scan_probe_segment common_data; 6435 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 6436} __packed; 6437 6438 6439#define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0) 6440#define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 6441#define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 6442#define IWX_SCAN_CHANNEL_FLAG_EBS_FRAG (1 << 3) 6443#define IWX_SCAN_CHANNEL_FLAG_FORCE_EBS (1 << 4) 6444#define IWX_SCAN_CHANNEL_FLAG_ENABLE_CHAN_ORDER (1 << 5) 6445#define IWX_SCAN_CHANNEL_FLAG_6G_PSC_NO_FILTER (1 << 6) 6446 6447/* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 6448 * @flags: enum iwx_scan_channel_flags 6449 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 6450 * involved. 6451 * 1 - EBS is disabled. 6452 * 2 - every second scan will be full scan(and so on). 6453 */ 6454struct iwx_scan_channel_opt { 6455 uint16_t flags; 6456 uint16_t non_ebs_ratio; 6457} __packed; 6458 6459#define IWX_SCAN_PRIORITY_LOW 0 6460#define IWX_SCAN_PRIORITY_MEDIUM 1 6461#define IWX_SCAN_PRIORITY_HIGH 2 6462 6463enum iwx_scan_priority_ext { 6464 IWX_SCAN_PRIORITY_EXT_0_LOWEST, 6465 IWX_SCAN_PRIORITY_EXT_1, 6466 IWX_SCAN_PRIORITY_EXT_2, 6467 IWX_SCAN_PRIORITY_EXT_3, 6468 IWX_SCAN_PRIORITY_EXT_4, 6469 IWX_SCAN_PRIORITY_EXT_5, 6470 IWX_SCAN_PRIORITY_EXT_6, 6471 IWX_SCAN_PRIORITY_EXT_7_HIGHEST, 6472}; 6473 6474/** 6475 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 6476 * @last_schedule_line: last schedule line executed (fast or regular) 6477 * @last_schedule_iteration: last scan iteration executed before scan abort 6478 * @status: enum iwx_scan_offload_complete_status 6479 * @ebs_status: EBS success status &enum iwx_scan_ebs_status 6480 * @time_after_last_iter; time in seconds elapsed after last iteration 6481 */ 6482struct iwx_periodic_scan_complete { 6483 uint8_t last_schedule_line; 6484 uint8_t last_schedule_iteration; 6485 uint8_t status; 6486 uint8_t ebs_status; 6487 uint32_t time_after_last_iter; 6488 uint32_t reserved; 6489} __packed; 6490 6491/** 6492 * struct iwx_scan_results_notif - scan results for one channel - 6493 * SCAN_RESULT_NTF_API_S_VER_3 6494 * @channel: which channel the results are from 6495 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 6496 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request 6497 * @num_probe_not_sent: # of request that weren't sent due to not enough time 6498 * @duration: duration spent in channel, in usecs 6499 */ 6500struct iwx_scan_results_notif { 6501 uint8_t channel; 6502 uint8_t band; 6503 uint8_t probe_status; 6504 uint8_t num_probe_not_sent; 6505 uint32_t duration; 6506} __packed; 6507 6508#define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0) 6509#define IWX_SCAN_CLIENT_NETDETECT (1 << 1) 6510#define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 6511 6512/** 6513 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S 6514 * @ssid: MAC address to filter out 6515 * @reported_rssi: AP rssi reported to the host 6516 * @client_bitmap: clients ignore this entry - enum scan_framework_client 6517 */ 6518struct iwx_scan_offload_blacklist { 6519 uint8_t ssid[ETHER_ADDR_LEN]; 6520 uint8_t reported_rssi; 6521 uint8_t client_bitmap; 6522} __packed; 6523 6524#define IWX_NETWORK_TYPE_BSS 1 6525#define IWX_NETWORK_TYPE_IBSS 2 6526#define IWX_NETWORK_TYPE_ANY 3 6527 6528#define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4 6529#define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8 6530#define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc 6531 6532/** 6533 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S 6534 * @ssid_index: index to ssid list in fixed part 6535 * @unicast_cipher: encryption algorithm to match - bitmap 6536 * @aut_alg: authentication algorithm to match - bitmap 6537 * @network_type: enum iwx_scan_offload_network_type 6538 * @band_selection: enum iwx_scan_offload_band_selection 6539 * @client_bitmap: clients waiting for match - enum scan_framework_client 6540 */ 6541struct iwx_scan_offload_profile { 6542 uint8_t ssid_index; 6543 uint8_t unicast_cipher; 6544 uint8_t auth_alg; 6545 uint8_t network_type; 6546 uint8_t band_selection; 6547 uint8_t client_bitmap; 6548 uint8_t reserved[2]; 6549} __packed; 6550 6551/** 6552 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 6553 * @blacklist: AP list to filter off from scan results 6554 * @profiles: profiles to search for match 6555 * @blacklist_len: length of blacklist 6556 * @num_profiles: num of profiles in the list 6557 * @match_notify: clients waiting for match found notification 6558 * @pass_match: clients waiting for the results 6559 * @active_clients: active clients bitmap - enum scan_framework_client 6560 * @any_beacon_notify: clients waiting for match notification without match 6561 */ 6562struct iwx_scan_offload_profile_cfg { 6563 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES]; 6564 uint8_t blacklist_len; 6565 uint8_t num_profiles; 6566 uint8_t match_notify; 6567 uint8_t pass_match; 6568 uint8_t active_clients; 6569 uint8_t any_beacon_notify; 6570 uint8_t reserved[2]; 6571} __packed; 6572 6573#define IWX_SCAN_OFFLOAD_COMPLETED 1 6574#define IWX_SCAN_OFFLOAD_ABORTED 2 6575 6576/* UMAC Scan API */ 6577 6578#define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 6579#define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 6580#define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 6581#define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 6582#define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 6583#define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 6584#define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 6585#define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 6586#define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 6587#define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 6588#define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 6589#define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 6590#define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 6591#define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 6592#define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 6593#define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 6594#define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 6595#define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 6596 6597/* Bits 26-31 are for num of channels in channel_array */ 6598#define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 6599 6600/* OFDM basic rates */ 6601#define IWX_SCAN_CONFIG_RATE_6M (1 << 0) 6602#define IWX_SCAN_CONFIG_RATE_9M (1 << 1) 6603#define IWX_SCAN_CONFIG_RATE_12M (1 << 2) 6604#define IWX_SCAN_CONFIG_RATE_18M (1 << 3) 6605#define IWX_SCAN_CONFIG_RATE_24M (1 << 4) 6606#define IWX_SCAN_CONFIG_RATE_36M (1 << 5) 6607#define IWX_SCAN_CONFIG_RATE_48M (1 << 6) 6608#define IWX_SCAN_CONFIG_RATE_54M (1 << 7) 6609/* CCK basic rates */ 6610#define IWX_SCAN_CONFIG_RATE_1M (1 << 8) 6611#define IWX_SCAN_CONFIG_RATE_2M (1 << 9) 6612#define IWX_SCAN_CONFIG_RATE_5M (1 << 10) 6613#define IWX_SCAN_CONFIG_RATE_11M (1 << 11) 6614 6615/* Bits 16-27 are for supported rates */ 6616#define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 6617 6618#define IWX_CHANNEL_FLAG_EBS (1 << 0) 6619#define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 6620#define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2) 6621#define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 6622 6623/** 6624 * struct iwx_scan_dwell 6625 * @active: default dwell time for active scan 6626 * @passive: default dwell time for passive scan 6627 * @fragmented: default dwell time for fragmented scan 6628 * @extended: default dwell time for channels 1, 6 and 11 6629 */ 6630struct iwx_scan_dwell { 6631 uint8_t active; 6632 uint8_t passive; 6633 uint8_t fragmented; 6634 uint8_t extended; 6635} __packed; 6636 6637 6638#define IWX_SCAN_TWO_LMACS 2 6639#define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */ 6640#define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */ 6641 6642/** 6643 * struct iwl_scan_config 6644 * @enable_cam_mode: whether to enable CAM mode. 6645 * @enable_promiscuous_mode: whether to enable promiscuous mode 6646 * @bcast_sta_id: the index of the station in the fw. Deprecated starting with 6647 * API version 5. 6648 * @reserved: reserved 6649 * @tx_chains: valid_tx antenna - ANT_* definitions 6650 * @rx_chains: valid_rx antenna - ANT_* definitions 6651 */ 6652struct iwx_scan_config { 6653 uint8_t enable_cam_mode; 6654 uint8_t enable_promiscuous_mode; 6655 uint8_t bcast_sta_id; 6656 uint8_t reserved; 6657 uint32_t tx_chains; 6658 uint32_t rx_chains; 6659} __packed; /* SCAN_CONFIG_DB_CMD_API_S_5 */ 6660 6661/** 6662 * struct iwx_scan_config_v2 6663 * @flags: enum scan_config_flags 6664 * @tx_chains: valid_tx antenna - ANT_* definitions 6665 * @rx_chains: valid_rx antenna - ANT_* definitions 6666 * @legacy_rates: default legacy rates - enum scan_config_rates 6667 * @out_of_channel_time: default max out of serving channel time 6668 * @suspend_time: default max suspend time 6669 * @dwell_active: default dwell time for active scan 6670 * @dwell_passive: default dwell time for passive scan 6671 * @dwell_fragmented: default dwell time for fragmented scan 6672 * @dwell_extended: default dwell time for channels 1, 6 and 11 6673 * @mac_addr: default mac address to be used in probes 6674 * @bcast_sta_id: the index of the station in the fw 6675 * @channel_flags: default channel flags - enum iwx_channel_flags 6676 * scan_config_channel_flag 6677 * @channel_array: default supported channels 6678 */ 6679struct iwx_scan_config_v2 { 6680 uint32_t flags; 6681 uint32_t tx_chains; 6682 uint32_t rx_chains; 6683 uint32_t legacy_rates; 6684 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS]; 6685 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 6686 struct iwx_scan_dwell dwell; 6687 uint8_t mac_addr[ETHER_ADDR_LEN]; 6688 uint8_t bcast_sta_id; 6689 uint8_t channel_flags; 6690 uint8_t channel_array[]; 6691} __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */ 6692 6693/** 6694 * iwx_umac_scan_flags 6695 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 6696 * can be preempted by other scan requests with higher priority. 6697 * The low priority scan will be resumed when the higher priority scan is 6698 * completed. 6699 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 6700 * when scan starts. 6701 */ 6702#define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 6703#define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 6704 6705#define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0 6706#define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8 6707 6708#define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 6709#define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 6710#define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 6711#define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 6712#define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 6713#define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 6714#define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 6715#define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 6716#define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 6717#define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 6718#define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 6719/* Extended dwell is obsolete when adaptive dwell is used, making this 6720 * bit reusable. Hence, probe request defer is used only when adaptive 6721 * dwell is supported. */ 6722#define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 6723#define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 6724#define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 6725#define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 6726#define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 6727 6728/** 6729 * UMAC scan general flags #2 6730 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 6731 * notification per channel or not. 6732 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 6733 * reorder optimization or not. 6734 */ 6735#define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 6736#define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 6737 6738/** 6739 * UMAC scan general flags version 2 6740 * 6741 * The FW flags were reordered and hence the driver introduce version 2 6742 * 6743 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled 6744 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons 6745 * during scan iterations 6746 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification 6747 * on every iteration instead of only once after the last iteration 6748 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1 6749 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2 6750 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching 6751 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX 6752 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell 6753 * for active channel 6754 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests 6755 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start 6756 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs 6757 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned 6758 * as passive 6759 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and 6760 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover 6761 * the reported collocated APs 6762 */ 6763#define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0) 6764#define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1) 6765#define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2) 6766#define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3) 6767#define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4) 6768#define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5) 6769#define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6) 6770#define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7) 6771#define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8) 6772#define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9) 6773#define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10) 6774#define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11) 6775#define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12) 6776 6777/** 6778 * struct iwx_scan_channel_cfg_umac 6779 * @flags: bitmap - 0-19: directed scan to i'th ssid. 6780 * @channel_num: channel number 1-13 etc. 6781 * @iter_count: repetition count for the channel. 6782 * @iter_interval: interval between two scan iterations on one channel. 6783 */ 6784struct iwx_scan_channel_cfg_umac { 6785 uint32_t flags; 6786 union { 6787 struct { 6788 uint8_t channel_num; 6789 uint8_t iter_count; 6790 uint16_t iter_interval; 6791 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */ 6792 struct { 6793 uint8_t channel_num; 6794 uint8_t band; 6795 uint8_t iter_count; 6796 uint8_t iter_interval; 6797 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */ 6798 }; 6799} __packed; 6800 6801/** 6802 * struct iwx_scan_umac_schedule 6803 * @interval: interval in seconds between scan iterations 6804 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 6805 * @reserved: for alignment and future use 6806 */ 6807struct iwx_scan_umac_schedule { 6808 uint16_t interval; 6809 uint8_t iter_count; 6810 uint8_t reserved; 6811} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 6812 6813/** 6814 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 6815 * parameters following channels configuration array. 6816 * @schedule: two scheduling plans. 6817 * @delay: delay in TUs before starting the first scan iteration 6818 * @reserved: for future use and alignment 6819 * @preq: probe request with IEs blocks 6820 * @direct_scan: list of SSIDs for directed active scan 6821 */ 6822struct iwx_scan_req_umac_tail_v1 { 6823 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6824 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 6825 uint16_t delay; 6826 uint16_t reserved; 6827 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 6828 struct iwx_scan_probe_req_v1 preq; 6829 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 6830} __packed; 6831 6832/** 6833 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 6834 * parameters following channels configuration array. 6835 * @schedule: two scheduling plans. 6836 * @delay: delay in TUs before starting the first scan iteration 6837 * @reserved: for future use and alignment 6838 * @preq: probe request with IEs blocks 6839 * @direct_scan: list of SSIDs for directed active scan 6840 */ 6841struct iwx_scan_req_umac_tail_v2 { 6842 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6843 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 6844 uint16_t delay; 6845 uint16_t reserved; 6846 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 6847 struct iwx_scan_probe_req preq; 6848 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 6849} __packed; 6850 6851/** 6852 * struct iwx_scan_umac_chan_param 6853 * @flags: channel flags &enum iwl_scan_channel_flags 6854 * @count: num of channels in scan request 6855 * @reserved: for future use and alignment 6856 */ 6857struct iwx_scan_umac_chan_param { 6858 uint8_t flags; 6859 uint8_t count; 6860 uint16_t reserved; 6861} __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 6862 6863#define IWX_SCAN_LB_LMAC_IDX 0 6864#define IWX_SCAN_HB_LMAC_IDX 1 6865 6866/** 6867 * struct iwx_scan_req_umac 6868 * @flags: &enum iwl_umac_scan_flags 6869 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 6870 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 6871 * @general_flags: &enum iwl_umac_scan_general_flags 6872 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 6873 * @extended_dwell: dwell time for channels 1, 6 and 11 6874 * @active_dwell: dwell time for active scan per LMAC 6875 * @passive_dwell: dwell time for passive scan per LMAC 6876 * @fragmented_dwell: dwell time for fragmented passive scan 6877 * @adwell_default_n_aps: for adaptive dwell the default number of APs 6878 * per channel 6879 * @adwell_default_n_aps_social: for adaptive dwell the default 6880 * number of APs per social (1,6,11) channel 6881 * @general_flags2: &enum iwl_umac_scan_general_flags2 6882 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 6883 * to total scan time 6884 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 6885 * are 2 LMACs (high band and low band) 6886 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 6887 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 6888 * @num_of_fragments: Number of fragments needed for full coverage per band. 6889 * Relevant only for fragmented scan. 6890 * @channel: &struct iwx_scan_umac_chan_param 6891 * @reserved: for future use and alignment 6892 * @reserved3: for future use and alignment 6893 * @data: &struct iwx_scan_channel_cfg_umac and 6894 * &struct iwx_scan_req_umac_tail 6895 */ 6896struct iwx_scan_req_umac { 6897 uint32_t flags; 6898 uint32_t uid; 6899 uint32_t ooc_priority; 6900 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 6901 uint16_t general_flags; 6902 uint8_t reserved; 6903 uint8_t scan_start_mac_id; 6904 union { 6905 struct { 6906 uint8_t extended_dwell; 6907 uint8_t active_dwell; 6908 uint8_t passive_dwell; 6909 uint8_t fragmented_dwell; 6910 uint32_t max_out_time; 6911 uint32_t suspend_time; 6912 uint32_t scan_priority; 6913 struct iwx_scan_umac_chan_param channel; 6914 uint8_t data[]; 6915 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 6916 struct { 6917 uint8_t extended_dwell; 6918 uint8_t active_dwell; 6919 uint8_t passive_dwell; 6920 uint8_t fragmented_dwell; 6921 uint32_t max_out_time[2]; 6922 uint32_t suspend_time[2]; 6923 uint32_t scan_priority; 6924 struct iwx_scan_umac_chan_param channel; 6925 uint8_t data[]; 6926 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 6927 struct { 6928 uint8_t active_dwell; 6929 uint8_t passive_dwell; 6930 uint8_t fragmented_dwell; 6931 uint8_t adwell_default_n_aps; 6932 uint8_t adwell_default_n_aps_social; 6933 uint8_t reserved3; 6934 uint16_t adwell_max_budget; 6935 uint32_t max_out_time[2]; 6936 uint32_t suspend_time[2]; 6937 uint32_t scan_priority; 6938 struct iwx_scan_umac_chan_param channel; 6939 uint8_t data[]; 6940 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 6941 struct { 6942 uint8_t active_dwell[2]; 6943 uint8_t reserved2; 6944 uint8_t adwell_default_n_aps; 6945 uint8_t adwell_default_n_aps_social; 6946 uint8_t general_flags2; 6947 uint16_t adwell_max_budget; 6948 uint32_t max_out_time[2]; 6949 uint32_t suspend_time[2]; 6950 uint32_t scan_priority; 6951 uint8_t passive_dwell[2]; 6952 uint8_t num_of_fragments[2]; 6953 struct iwx_scan_umac_chan_param channel; 6954 uint8_t data[]; 6955 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 6956 struct { 6957 uint8_t active_dwell[2]; 6958 uint8_t adwell_default_hb_n_aps; 6959 uint8_t adwell_default_lb_n_aps; 6960 uint8_t adwell_default_n_aps_social; 6961 uint8_t general_flags2; 6962 uint16_t adwell_max_budget; 6963 uint32_t max_out_time[2]; 6964 uint32_t suspend_time[2]; 6965 uint32_t scan_priority; 6966 uint8_t passive_dwell[2]; 6967 uint8_t num_of_fragments[2]; 6968 struct iwx_scan_umac_chan_param channel; 6969 uint8_t data[]; 6970 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 6971 }; 6972} __packed; 6973 6974#define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac) 6975#define IWX_SCAN_REQ_UMAC_SIZE_V7 48 6976#define IWX_SCAN_REQ_UMAC_SIZE_V6 44 6977#define IWX_SCAN_REQ_UMAC_SIZE_V1 36 6978 6979/** 6980 * struct iwx_scan_general_params_v10 6981 * @flags: &enum iwx_umac_scan_flags 6982 * @reserved: reserved for future 6983 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 6984 * @active_dwell: dwell time for active scan per LMAC 6985 * @adwell_default_2g: adaptive dwell default number of APs 6986 * for 2.4GHz channel 6987 * @adwell_default_5g: adaptive dwell default number of APs 6988 * for 5GHz channels 6989 * @adwell_default_social_chn: adaptive dwell default number of 6990 * APs per social channel 6991 * @reserved1: reserved for future 6992 * @adwell_max_budget: the maximal number of TUs that adaptive dwell 6993 * can add to the total scan time 6994 * @max_out_of_time: max out of serving channel time, per LMAC 6995 * @suspend_time: max suspend time, per LMAC 6996 * @scan_priority: priority of the request 6997 * @passive_dwell: continues dwell time for passive channel 6998 * (without adaptive dwell) 6999 * @num_of_fragments: number of fragments needed for full fragmented 7000 * scan coverage. 7001 */ 7002struct iwx_scan_general_params_v10 { 7003 uint16_t flags; 7004 uint8_t reserved; 7005 uint8_t scan_start_mac_id; 7006 uint8_t active_dwell[IWX_SCAN_TWO_LMACS]; 7007 uint8_t adwell_default_2g; 7008 uint8_t adwell_default_5g; 7009 uint8_t adwell_default_social_chn; 7010 uint8_t reserved1; 7011 uint16_t adwell_max_budget; 7012 uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS]; 7013 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 7014 uint32_t scan_priority; 7015 uint8_t passive_dwell[IWX_SCAN_TWO_LMACS]; 7016 uint8_t num_of_fragments[IWX_SCAN_TWO_LMACS]; 7017} __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_10 */ 7018 7019/** 7020 * struct iwx_scan_channel_params_v6 7021 * @flags: channel flags &enum iwl_scan_channel_flags 7022 * @count: num of channels in scan request 7023 * @n_aps_override: override the number of APs the FW uses to calculate dwell 7024 * time when adaptive dwell is used. 7025 * Channel k will use n_aps_override[i] when BIT(20 + i) is set in 7026 * channel_config[k].flags 7027 * @channel_config: array of explicit channel configurations 7028 * for 2.4Ghz and 5.2Ghz bands 7029 */ 7030struct iwx_scan_channel_params_v6 { 7031 uint8_t flags; 7032 uint8_t count; 7033 uint8_t n_aps_override[2]; 7034 struct iwx_scan_channel_cfg_umac channel_config[67]; 7035} __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_6 */ 7036 7037/** 7038 * struct iwx_scan_periodic_parms_v1 7039 * @schedule: can scheduling parameter 7040 * @delay: initial delay of the periodic scan in seconds 7041 * @reserved: reserved for future 7042 */ 7043struct iwx_scan_periodic_parms_v1 { 7044 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 7045 uint16_t delay; 7046 uint16_t reserved; 7047} __packed; /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 7048 7049#define IWX_SCAN_SHORT_SSID_MAX_SIZE 8 7050#define IWX_SCAN_BSSID_MAX_SIZE 16 7051 7052/** 7053 * struct iwx_scan_probe_params_v4 7054 * @preq: scan probe request params 7055 * @short_ssid_num: number of valid short SSIDs in short ssid array 7056 * @bssid_num: number of valid bssid in bssids array 7057 * @reserved: reserved 7058 * @direct_scan: list of ssids 7059 * @short_ssid: array of short ssids 7060 * @bssid_array: array of bssids 7061 */ 7062struct iwx_scan_probe_params_v4 { 7063 struct iwx_scan_probe_req preq; 7064 uint8_t short_ssid_num; 7065 uint8_t bssid_num; 7066 uint16_t reserved; 7067 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 7068 uint32_t short_ssid[IWX_SCAN_SHORT_SSID_MAX_SIZE]; 7069 uint8_t bssid_array[IWX_SCAN_BSSID_MAX_SIZE][ETHER_ADDR_LEN]; 7070} __packed; /* SCAN_PROBE_PARAMS_API_S_VER_4 */ 7071 7072/** 7073 * struct iwx_scan_req_params_v14 7074 * @general_params: &struct iwx_scan_general_params_v10 7075 * @channel_params: &struct iwx_scan_channel_params_v6 7076 * @periodic_params: &struct iwx_scan_periodic_parms_v1 7077 * @probe_params: &struct iwx_scan_probe_params_v4 7078 */ 7079struct iwx_scan_req_params_v14 { 7080 struct iwx_scan_general_params_v10 general_params; 7081 struct iwx_scan_channel_params_v6 channel_params; 7082 struct iwx_scan_periodic_parms_v1 periodic_params; 7083 struct iwx_scan_probe_params_v4 probe_params; 7084} __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_14 */ 7085 7086/** 7087 * struct iwx_scan_req_umac_v14 7088 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 7089 * @ooc_priority: out of channel priority - &enum iwx_scan_priority 7090 * @scan_params: scan parameters 7091 */ 7092struct iwx_scan_req_umac_v14 { 7093 uint32_t uid; 7094 uint32_t ooc_priority; 7095 struct iwx_scan_req_params_v14 scan_params; 7096} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_14 */ 7097 7098/** 7099 * struct iwx_umac_scan_abort 7100 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7101 * @flags: reserved 7102 */ 7103struct iwx_umac_scan_abort { 7104 uint32_t uid; 7105 uint32_t flags; 7106} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 7107 7108/** 7109 * struct iwx_umac_scan_complete 7110 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7111 * @last_schedule: last scheduling line 7112 * @last_iter: last scan iteration number 7113 * @scan status: &enum iwx_scan_offload_complete_status 7114 * @ebs_status: &enum iwx_scan_ebs_status 7115 * @time_from_last_iter: time elapsed from last iteration 7116 * @reserved: for future use 7117 */ 7118struct iwx_umac_scan_complete { 7119 uint32_t uid; 7120 uint8_t last_schedule; 7121 uint8_t last_iter; 7122 uint8_t status; 7123 uint8_t ebs_status; 7124 uint32_t time_from_last_iter; 7125 uint32_t reserved; 7126} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 7127 7128#define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 7129/** 7130 * struct iwx_scan_offload_profile_match - match information 7131 * @bssid: matched bssid 7132 * @channel: channel where the match occurred 7133 * @energy: 7134 * @matching_feature: 7135 * @matching_channels: bitmap of channels that matched, referencing 7136 * the channels passed in tue scan offload request 7137 */ 7138struct iwx_scan_offload_profile_match { 7139 uint8_t bssid[ETHER_ADDR_LEN]; 7140 uint16_t reserved; 7141 uint8_t channel; 7142 uint8_t energy; 7143 uint8_t matching_feature; 7144 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 7145} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 7146 7147/** 7148 * struct iwx_scan_offload_profiles_query - match results query response 7149 * @matched_profiles: bitmap of matched profiles, referencing the 7150 * matches passed in the scan offload request 7151 * @last_scan_age: age of the last offloaded scan 7152 * @n_scans_done: number of offloaded scans done 7153 * @gp2_d0u: GP2 when D0U occurred 7154 * @gp2_invoked: GP2 when scan offload was invoked 7155 * @resume_while_scanning: not used 7156 * @self_recovery: obsolete 7157 * @reserved: reserved 7158 * @matches: array of match information, one for each match 7159 */ 7160struct iwx_scan_offload_profiles_query { 7161 uint32_t matched_profiles; 7162 uint32_t last_scan_age; 7163 uint32_t n_scans_done; 7164 uint32_t gp2_d0u; 7165 uint32_t gp2_invoked; 7166 uint8_t resume_while_scanning; 7167 uint8_t self_recovery; 7168 uint16_t reserved; 7169 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES]; 7170} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 7171 7172/** 7173 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration 7174 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7175 * @scanned_channels: number of channels scanned and number of valid elements in 7176 * results array 7177 * @status: one of SCAN_COMP_STATUS_* 7178 * @bt_status: BT on/off status 7179 * @last_channel: last channel that was scanned 7180 * @tsf_low: TSF timer (lower half) in usecs 7181 * @tsf_high: TSF timer (higher half) in usecs 7182 * @results: array of scan results, only "scanned_channels" of them are valid 7183 */ 7184struct iwx_umac_scan_iter_complete_notif { 7185 uint32_t uid; 7186 uint8_t scanned_channels; 7187 uint8_t status; 7188 uint8_t bt_status; 7189 uint8_t last_channel; 7190 uint32_t tsf_low; 7191 uint32_t tsf_high; 7192 struct iwx_scan_results_notif results[]; 7193} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 7194 7195#define IWX_GSCAN_START_CMD 0x0 7196#define IWX_GSCAN_STOP_CMD 0x1 7197#define IWX_GSCAN_SET_HOTLIST_CMD 0x2 7198#define IWX_GSCAN_RESET_HOTLIST_CMD 0x3 7199#define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 7200#define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 7201#define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 7202#define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 7203#define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 7204 7205/* STA API */ 7206 7207/** 7208 * flags for the ADD_STA host command 7209 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL: 7210 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA: 7211 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled 7212 * @IWX_STA_FLG_PS: set if STA is in Power Save 7213 * @IWX_STA_FLG_INVALID: set if STA is invalid 7214 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled 7215 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 7216 * @IWX_STA_FLG_DRAIN_FLOW: drain flow 7217 * @IWX_STA_FLG_PAN: STA is for PAN interface 7218 * @IWX_STA_FLG_CLASS_AUTH: 7219 * @IWX_STA_FLG_CLASS_ASSOC: 7220 * @IWX_STA_FLG_CLASS_MIMO_PROT: 7221 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 7222 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 7223 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 7224 * initialised by driver and can be updated by fw upon reception of 7225 * action frames that can change the channel width. When cleared the fw 7226 * will send all the frames in 20MHz even when FAT channel is requested. 7227 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 7228 * driver and can be updated by fw upon reception of action frames. 7229 * @IWX_STA_FLG_MFP_EN: Management Frame Protection 7230 */ 7231#define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 7232#define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 7233 7234#define IWX_STA_FLG_DISABLE_TX (1 << 4) 7235 7236#define IWX_STA_FLG_PS (1 << 8) 7237#define IWX_STA_FLG_DRAIN_FLOW (1 << 12) 7238#define IWX_STA_FLG_PAN (1 << 13) 7239#define IWX_STA_FLG_CLASS_AUTH (1 << 14) 7240#define IWX_STA_FLG_CLASS_ASSOC (1 << 15) 7241#define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17) 7242 7243#define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19 7244#define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7245#define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7246#define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7247#define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7248#define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7249#define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7250#define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7251#define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7252#define IWX_STA_FLG_MAX_AGG_SIZE_2M (8 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7253#define IWX_STA_FLG_MAX_AGG_SIZE_4M (9 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7254#define IWX_STA_FLG_MAX_AGG_SIZE_MSK (0xf << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7255 7256#define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23 7257#define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7258#define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7259#define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7260#define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7261#define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7262 7263#define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26) 7264#define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26) 7265#define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26) 7266#define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26) 7267#define IWX_STA_FLG_FAT_EN_MSK (3 << 26) 7268 7269#define IWX_STA_FLG_MIMO_EN_SISO (0 << 28) 7270#define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 7271#define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 7272#define IWX_STA_FLG_MIMO_EN_MSK (3 << 28) 7273 7274/** 7275 * key flags for the ADD_STA host command 7276 * @IWX_STA_KEY_FLG_NO_ENC: no encryption 7277 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm 7278 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm 7279 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm 7280 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 7281 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm 7282 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 7283 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithm value 7284 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 7285 * station info array (1 - n 1X mode) 7286 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key 7287 * @IWX_STA_KEY_NOT_VALID: key is invalid 7288 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 7289 * @IWX_STA_KEY_MULTICAST: set for multicast key 7290 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection 7291 */ 7292#define IWX_STA_KEY_FLG_NO_ENC (0 << 0) 7293#define IWX_STA_KEY_FLG_WEP (1 << 0) 7294#define IWX_STA_KEY_FLG_CCM (2 << 0) 7295#define IWX_STA_KEY_FLG_TKIP (3 << 0) 7296#define IWX_STA_KEY_FLG_EXT (4 << 0) 7297#define IWX_STA_KEY_FLG_CMAC (6 << 0) 7298#define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 7299#define IWX_STA_KEY_FLG_EN_MSK (7 << 0) 7300#define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 7301#define IWX_STA_KEY_FLG_KEYID_POS 8 7302#define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS) 7303#define IWX_STA_KEY_NOT_VALID (1 << 11) 7304#define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12) 7305#define IWX_STA_KEY_MULTICAST (1 << 14) 7306#define IWX_STA_KEY_MFP (1 << 15) 7307 7308/** 7309 * indicate to the fw what flag are being changed 7310 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 7311 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 7312 * @IWX_STA_MODIFY_TX_RATE: unused 7313 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 7314 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 7315 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 7316 * @IWX_STA_MODIFY_PROT_TH: 7317 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station 7318 */ 7319#define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 7320#define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1) 7321#define IWX_STA_MODIFY_TX_RATE (1 << 2) 7322#define IWX_STA_MODIFY_ADD_BA_TID (1 << 3) 7323#define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4) 7324#define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 7325#define IWX_STA_MODIFY_PROT_TH (1 << 6) 7326#define IWX_STA_MODIFY_QUEUES (1 << 7) 7327 7328#define IWX_STA_MODE_MODIFY 1 7329 7330/** 7331 * type of sleep of the station 7332 * @IWX_STA_SLEEP_STATE_AWAKE: 7333 * @IWX_STA_SLEEP_STATE_PS_POLL: 7334 * @IWX_STA_SLEEP_STATE_UAPSD: 7335 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on 7336 * (last) released frame 7337 */ 7338#define IWX_STA_SLEEP_STATE_AWAKE 0 7339#define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0) 7340#define IWX_STA_SLEEP_STATE_UAPSD (1 << 1) 7341#define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2) 7342 7343/* STA ID and color bits definitions */ 7344#define IWX_STA_ID_SEED (0x0f) 7345#define IWX_STA_ID_POS (0) 7346#define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS) 7347 7348#define IWX_STA_COLOR_SEED (0x7) 7349#define IWX_STA_COLOR_POS (4) 7350#define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS) 7351 7352#define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 7353 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS) 7354#define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \ 7355 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS) 7356 7357#define IWX_STA_KEY_MAX_NUM (16) 7358#define IWX_STA_KEY_IDX_INVALID (0xff) 7359#define IWX_STA_KEY_MAX_DATA_KEY_NUM (4) 7360#define IWX_MAX_GLOBAL_KEYS (4) 7361#define IWX_STA_KEY_LEN_WEP40 (5) 7362#define IWX_STA_KEY_LEN_WEP104 (13) 7363 7364/** 7365 * struct iwx_keyinfo - key information 7366 * @key_flags: type %iwx_sta_key_flag 7367 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 7368 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 7369 * @key_offset: key offset in the fw's key table 7370 * @key: 16-byte unicast decryption key 7371 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 7372 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 7373 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 7374 */ 7375struct iwx_keyinfo { 7376 uint16_t key_flags; 7377 uint8_t tkip_rx_tsc_byte2; 7378 uint8_t reserved1; 7379 uint16_t tkip_rx_ttak[5]; 7380 uint8_t key_offset; 7381 uint8_t reserved2; 7382 uint8_t key[16]; 7383 uint64_t tx_secur_seq_cnt; 7384 uint64_t hw_tkip_mic_rx_key; 7385 uint64_t hw_tkip_mic_tx_key; 7386} __packed; 7387 7388#define IWX_ADD_STA_STATUS_MASK 0xFF 7389#define IWX_ADD_STA_BAID_VALID_MASK 0x8000 7390#define IWX_ADD_STA_BAID_MASK 0x7F00 7391#define IWX_ADD_STA_BAID_SHIFT 8 7392 7393/** 7394 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table. 7395 * ( REPLY_ADD_STA = 0x18 ) 7396 * @add_modify: see &enum iwl_sta_mode 7397 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 7398 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 7399 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 7400 * @mac_id_n_color: the Mac context this station belongs to, 7401 * see &enum iwl_ctxt_id_and_color 7402 * @addr: station's MAC address 7403 * @reserved2: reserved 7404 * @sta_id: index of station in uCode's station table 7405 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 7406 * alone. 1 - modify, 0 - don't change. 7407 * @reserved3: reserved 7408 * @station_flags: look at &enum iwl_sta_flags 7409 * @station_flags_msk: what of %station_flags have changed, 7410 * also &enum iwl_sta_flags 7411 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 7412 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 7413 * add_immediate_ba_ssn. 7414 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 7415 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 7416 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 7417 * add_immediate_ba_tid. 7418 * @sleep_tx_count: number of packets to transmit to station even though it is 7419 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 7420 * keeps track of STA sleep state. 7421 * @station_type: type of this station. See &enum iwl_sta_type. 7422 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 7423 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 7424 * mac-addr. 7425 * @beamform_flags: beam forming controls 7426 * @tfd_queue_msk: tfd queues used by this station. 7427 * Obsolete for new TX API (9 and above). 7428 * @rx_ba_window: aggregation window size 7429 * @sp_length: the size of the SP in actual number of frames 7430 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 7431 * enabled ACs. 7432 * 7433 * The device contains an internal table of per-station information, with info 7434 * on security keys, aggregation parameters, and Tx rates for initial Tx 7435 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 7436 * 7437 * ADD_STA sets up the table entry for one station, either creating a new 7438 * entry, or modifying a pre-existing one. 7439 */ 7440struct iwx_add_sta_cmd { 7441 uint8_t add_modify; 7442 uint8_t awake_acs; 7443 uint16_t tid_disable_tx; 7444 uint32_t mac_id_n_color; 7445 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 7446 uint16_t reserved2; 7447 uint8_t sta_id; 7448 uint8_t modify_mask; 7449 uint16_t reserved3; 7450 uint32_t station_flags; 7451 uint32_t station_flags_msk; 7452 uint8_t add_immediate_ba_tid; 7453 uint8_t remove_immediate_ba_tid; 7454 uint16_t add_immediate_ba_ssn; 7455 uint16_t sleep_tx_count; 7456 uint8_t sleep_state_flags; 7457 uint8_t station_type; 7458 uint16_t assoc_id; 7459 uint16_t beamform_flags; 7460 uint32_t tfd_queue_msk; 7461 uint16_t rx_ba_window; 7462 uint8_t sp_length; 7463 uint8_t uapsd_acs; 7464} __packed; /* ADD_STA_CMD_API_S_VER_10 */ 7465 7466/** 7467 * FW station types 7468 * ( REPLY_ADD_STA = 0x18 ) 7469 * @IWX_STA_LINK: Link station - normal RX and TX traffic. 7470 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 7471 * and probe responses. 7472 * @IWX_STA_MULTICAST: multicast traffic, 7473 * @IWX_STA_TDLS_LINK: TDLS link station 7474 * @IWX_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on). 7475 */ 7476#define IWX_STA_LINK 0 7477#define IWX_STA_GENERAL_PURPOSE 1 7478#define IWX_STA_MULTICAST 2 7479#define IWX_STA_TDLS_LINK 3 7480#define IWX_STA_AUX_ACTIVITY 4 7481 7482/** 7483 * struct iwx_add_sta_key_common - add/modify sta key common part 7484 * ( REPLY_ADD_STA_KEY = 0x17 ) 7485 * @sta_id: index of station in uCode's station table 7486 * @key_offset: key offset in key storage 7487 * @key_flags: IWX_STA_KEY_FLG_* 7488 * @key: key material data 7489 * @rx_secur_seq_cnt: RX security sequence counter for the key 7490 */ 7491struct iwx_add_sta_key_common { 7492 uint8_t sta_id; 7493 uint8_t key_offset; 7494 uint16_t key_flags; 7495 uint8_t key[32]; 7496 uint8_t rx_secur_seq_cnt[16]; 7497} __packed; 7498 7499/** 7500 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key 7501 * @common: see &struct iwx_add_sta_key_common 7502 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 7503 * @reserved: reserved 7504 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 7505 */ 7506struct iwx_add_sta_key_cmd_v1 { 7507 struct iwx_add_sta_key_common common; 7508 uint8_t tkip_rx_tsc_byte2; 7509 uint8_t reserved; 7510 uint16_t tkip_rx_ttak[5]; 7511} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 7512 7513/** 7514 * struct iwx_add_sta_key_cmd - add/modify sta key 7515 * @common: see &struct iwx_add_sta_key_common 7516 * @rx_mic_key: TKIP RX unicast or multicast key 7517 * @tx_mic_key: TKIP TX key 7518 * @transmit_seq_cnt: TSC, transmit packet number 7519 */ 7520struct iwx_add_sta_key_cmd { 7521 struct iwx_add_sta_key_common common; 7522 uint64_t rx_mic_key; 7523 uint64_t tx_mic_key; 7524 uint64_t transmit_seq_cnt; 7525} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 7526 7527/** 7528 * status in the response to ADD_STA command 7529 * @IWX_ADD_STA_SUCCESS: operation was executed successfully 7530 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 7531 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 7532 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 7533 * that doesn't exist. 7534 */ 7535#define IWX_ADD_STA_SUCCESS 0x1 7536#define IWX_ADD_STA_STATIONS_OVERLOAD 0x2 7537#define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 7538#define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 7539 7540/** 7541 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table 7542 * ( IWX_REMOVE_STA = 0x19 ) 7543 * @sta_id: the station id of the station to be removed 7544 */ 7545struct iwx_rm_sta_cmd { 7546 uint8_t sta_id; 7547 uint8_t reserved[3]; 7548} __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */ 7549 7550/** 7551 * struct iwx_mgmt_mcast_key_cmd 7552 * ( IWX_MGMT_MCAST_KEY = 0x1f ) 7553 * @ctrl_flags: %iwx_sta_key_flag 7554 * @IGTK: 7555 * @K1: IGTK master key 7556 * @K2: IGTK sub key 7557 * @sta_id: station ID that support IGTK 7558 * @key_id: 7559 * @receive_seq_cnt: initial RSC/PN needed for replay check 7560 */ 7561struct iwx_mgmt_mcast_key_cmd { 7562 uint32_t ctrl_flags; 7563 uint8_t IGTK[16]; 7564 uint8_t K1[16]; 7565 uint8_t K2[16]; 7566 uint32_t key_id; 7567 uint32_t sta_id; 7568 uint64_t receive_seq_cnt; 7569} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 7570 7571struct iwx_wep_key { 7572 uint8_t key_index; 7573 uint8_t key_offset; 7574 uint16_t reserved1; 7575 uint8_t key_size; 7576 uint8_t reserved2[3]; 7577 uint8_t key[16]; 7578} __packed; 7579 7580struct iwx_wep_key_cmd { 7581 uint32_t mac_id_n_color; 7582 uint8_t num_keys; 7583 uint8_t decryption_type; 7584 uint8_t flags; 7585 uint8_t reserved; 7586 struct iwx_wep_key wep_key[0]; 7587} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 7588 7589/* 7590 * BT coex 7591 */ 7592 7593#define IWX_BT_COEX_DISABLE 0x0 7594#define IWX_BT_COEX_NW 0x1 7595#define IWX_BT_COEX_BT 0x2 7596#define IWX_BT_COEX_WIFI 0x3 7597/* BT_COEX_MODES_E */ 7598 7599#define IWX_BT_COEX_MPLUT_ENABLED (1 << 0) 7600#define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 7601#define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 7602#define IWX_BT_COEX_CORUN_ENABLED (1 << 3) 7603#define IWX_BT_COEX_HIGH_BAND_RET (1 << 4) 7604/* BT_COEX_MODULES_ENABLE_E_VER_1 */ 7605 7606/** 7607 * struct iwx_bt_coex_cmd - bt coex configuration command 7608 * @mode: enum %iwx_bt_coex_mode 7609 * @enabled_modules: enum %iwx_bt_coex_enabled_modules 7610 * 7611 * The structure is used for the BT_COEX command. 7612 */ 7613struct iwx_bt_coex_cmd { 7614 uint32_t mode; 7615 uint32_t enabled_modules; 7616} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 7617 7618 7619/* 7620 * Location Aware Regulatory (LAR) API - MCC updates 7621 */ 7622 7623/** 7624 * struct iwx_mcc_update_cmd - Request the device to update geographic 7625 * regulatory profile according to the given MCC (Mobile Country Code). 7626 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 7627 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 7628 * MCC in the cmd response will be the relevant MCC in the NVM. 7629 * @mcc: given mobile country code 7630 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_* 7631 * @reserved: reserved for alignment 7632 * @key: integrity key for MCC API OEM testing 7633 * @reserved2: reserved 7634 */ 7635struct iwx_mcc_update_cmd { 7636 uint16_t mcc; 7637 uint8_t source_id; 7638 uint8_t reserved; 7639 uint32_t key; 7640 uint32_t reserved2[5]; 7641} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 7642 7643/** 7644 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 7645 * Contains the new channel control profile map, if changed, and the new MCC 7646 * (mobile country code). 7647 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 7648 * @status: see &enum iwx_mcc_update_status 7649 * @mcc: the new applied MCC 7650 * @cap: capabilities for all channels which matches the MCC 7651 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 7652 * @time: time elapsed from the MCC test start (in 30 seconds TU) 7653 * @reserved: reserved. 7654 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 7655 * channels, depending on platform) 7656 * @channels: channel control data map, DWORD for each channel. Only the first 7657 * 16bits are used. 7658 */ 7659struct iwx_mcc_update_resp_v3 { 7660 uint32_t status; 7661 uint16_t mcc; 7662 uint8_t cap; 7663 uint8_t source_id; 7664 uint16_t time; 7665 uint16_t geo_info; 7666 uint32_t n_channels; 7667 uint32_t channels[0]; 7668} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 7669 7670/** 7671 * geographic information. 7672 * @GEO_NO_INFO: no special info for this geo profile. 7673 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params 7674 * for the 5 GHz band. 7675 */ 7676#define IWX_GEO_NO_INFO 0 7677#define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 7678 7679/** 7680 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD. 7681 * Contains the new channel control profile map, if changed, and the new MCC 7682 * (mobile country code). 7683 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 7684 * @status: see &enum iwl_mcc_update_status 7685 * @mcc: the new applied MCC 7686 * @cap: capabilities for all channels which matches the MCC 7687 * @time: time elapsed from the MCC test start (in units of 30 seconds) 7688 * @geo_info: geographic specific profile information 7689 * see IWX_GEO_* 7690 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 7691 * @reserved: for four bytes alignment. 7692 * @n_channels: number of channels in @channels_data. 7693 * @channels: channel control data map, DWORD for each channel. Only the first 7694 * 16bits are used. 7695 */ 7696struct iwx_mcc_update_resp { 7697 uint32_t status; 7698 uint16_t mcc; 7699 uint16_t cap; 7700 uint16_t time; 7701 uint16_t geo_info; 7702 uint8_t source_id; 7703 uint8_t reserved[3]; 7704 uint32_t n_channels; 7705 uint32_t channels[0]; 7706} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */ 7707 7708/** 7709 * struct iwx_mcc_chub_notif - chub notifies of mcc change 7710 * (MCC_CHUB_UPDATE_CMD = 0xc9) 7711 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 7712 * the cellular and connectivity cores that gets updates of the mcc, and 7713 * notifies the ucode directly of any mcc change. 7714 * The ucode requests the driver to request the device to update geographic 7715 * regulatory profile according to the given MCC (Mobile Country Code). 7716 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 7717 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 7718 * MCC in the cmd response will be the relevant MCC in the NVM. 7719 * @mcc: given mobile country code 7720 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_* 7721 * @reserved1: reserved for alignment 7722 */ 7723struct iwx_mcc_chub_notif { 7724 uint16_t mcc; 7725 uint8_t source_id; 7726 uint8_t reserved1; 7727} __packed; /* LAR_MCC_NOTIFY_S */ 7728 7729enum iwx_mcc_update_status { 7730 IWX_MCC_RESP_NEW_CHAN_PROFILE, 7731 IWX_MCC_RESP_SAME_CHAN_PROFILE, 7732 IWX_MCC_RESP_INVALID, 7733 IWX_MCC_RESP_NVM_DISABLED, 7734 IWX_MCC_RESP_ILLEGAL, 7735 IWX_MCC_RESP_LOW_PRIORITY, 7736 IWX_MCC_RESP_TEST_MODE_ACTIVE, 7737 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE, 7738 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 7739}; 7740 7741#define IWX_MCC_SOURCE_OLD_FW 0 7742#define IWX_MCC_SOURCE_ME 1 7743#define IWX_MCC_SOURCE_BIOS 2 7744#define IWX_MCC_SOURCE_3G_LTE_HOST 3 7745#define IWX_MCC_SOURCE_3G_LTE_DEVICE 4 7746#define IWX_MCC_SOURCE_WIFI 5 7747#define IWX_MCC_SOURCE_RESERVED 6 7748#define IWX_MCC_SOURCE_DEFAULT 7 7749#define IWX_MCC_SOURCE_UNINITIALIZED 8 7750#define IWX_MCC_SOURCE_MCC_API 9 7751#define IWX_MCC_SOURCE_GET_CURRENT 0x10 7752#define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 7753 7754/* 7755 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 7756 * As the firmware is slowly running out of command IDs and grouping of 7757 * commands is desirable anyway, the firmware is extending the command 7758 * header from 4 bytes to 8 bytes to introduce a group (in place of the 7759 * former flags field, since that's always 0 on commands and thus can 7760 * be easily used to distinguish between the two). 7761 * 7762 * These functions retrieve specific information from the id field in 7763 * the iwx_host_cmd struct which contains the command id, the group id, 7764 * and the version of the command. 7765*/ 7766static inline uint8_t 7767iwx_cmd_opcode(uint32_t cmdid) 7768{ 7769 return cmdid & 0xff; 7770} 7771 7772static inline uint8_t 7773iwx_cmd_groupid(uint32_t cmdid) 7774{ 7775 return ((cmdid & 0Xff00) >> 8); 7776} 7777 7778static inline uint8_t 7779iwx_cmd_version(uint32_t cmdid) 7780{ 7781 return ((cmdid & 0xff0000) >> 16); 7782} 7783 7784static inline uint32_t 7785iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 7786{ 7787 return opcode + (groupid << 8) + (version << 16); 7788} 7789 7790/* make uint16_t wide id out of uint8_t group and opcode */ 7791#define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 7792 7793struct iwx_cmd_header { 7794 uint8_t code; 7795 uint8_t flags; 7796 uint8_t idx; 7797 uint8_t qid; 7798} __packed; 7799 7800struct iwx_cmd_header_wide { 7801 uint8_t opcode; 7802 uint8_t group_id; 7803 uint8_t idx; 7804 uint8_t qid; 7805 uint16_t length; 7806 uint8_t reserved; 7807 uint8_t version; 7808} __packed; 7809 7810#define IWX_POWER_SCHEME_CAM 1 7811#define IWX_POWER_SCHEME_BPS 2 7812#define IWX_POWER_SCHEME_LP 3 7813 7814#define IWX_DEF_CMD_PAYLOAD_SIZE 320 7815#define IWX_MAX_CMD_PAYLOAD_SIZE (4096 - sizeof(struct iwx_cmd_header_wide)) 7816#define IWX_CMD_FAILED_MSK 0x40 7817 7818/** 7819 * struct iwx_device_cmd 7820 * 7821 * For allocation of the command and tx queues, this establishes the overall 7822 * size of the largest command we send to uCode, except for commands that 7823 * aren't fully copied and use other TFD space. 7824 */ 7825struct iwx_device_cmd { 7826 union { 7827 struct { 7828 struct iwx_cmd_header hdr; 7829 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE]; 7830 }; 7831 struct { 7832 struct iwx_cmd_header_wide hdr_wide; 7833 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE - 7834 sizeof(struct iwx_cmd_header_wide) + 7835 sizeof(struct iwx_cmd_header)]; 7836 }; 7837 }; 7838} __packed; 7839 7840struct iwx_rx_packet { 7841 /* 7842 * The first 4 bytes of the RX frame header contain both the RX frame 7843 * size and some flags. 7844 * Bit fields: 7845 * 31: flag flush RB request 7846 * 30: flag ignore TC (terminal counter) request 7847 * 29: flag fast IRQ request 7848 * 28-26: Reserved 7849 * 25: Offload enabled 7850 * 24: RPF enabled 7851 * 23: RSS enabled 7852 * 22: Checksum enabled 7853 * 21-16: RX queue 7854 * 15-14: Reserved 7855 * 13-00: RX frame size 7856 */ 7857 uint32_t len_n_flags; 7858 struct iwx_cmd_header hdr; 7859 uint8_t data[]; 7860} __packed; 7861 7862#define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 7863#define IWX_FH_RSCSR_FRAME_INVALID 0x55550000 7864#define IWX_FH_RSCSR_FRAME_ALIGN 0x40 7865#define IWX_FH_RSCSR_RPA_EN (1 << 25) 7866#define IWX_FH_RSCSR_RADA_EN (1 << 26) 7867#define IWX_FH_RSCSR_RXQ_POS 16 7868#define IWX_FH_RSCSR_RXQ_MASK 0x3F0000 7869 7870static uint32_t 7871iwx_rx_packet_len(const struct iwx_rx_packet *pkt) 7872{ 7873 7874 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK; 7875} 7876 7877static uint32_t 7878iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt) 7879{ 7880 7881 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr); 7882} 7883 7884 7885#define IWX_MIN_DBM -100 7886#define IWX_MAX_DBM -33 /* realistic guess */ 7887 7888#define IWX_READ(sc, reg) \ 7889 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 7890 7891#define IWX_WRITE(sc, reg, val) \ 7892 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7893 7894#define IWX_WRITE_1(sc, reg, val) \ 7895 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7896 7897#define IWX_SETBITS(sc, reg, mask) \ 7898 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)) 7899 7900#define IWX_CLRBITS(sc, reg, mask) \ 7901 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask)) 7902 7903#define IWX_BARRIER_WRITE(sc) \ 7904 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7905 BUS_SPACE_BARRIER_WRITE) 7906 7907#define IWX_BARRIER_READ_WRITE(sc) \ 7908 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7909 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 7910