Searched refs:slice (Results 26 - 50 of 75) sorted by relevance

123

/linux-master/arch/powerpc/mm/book3s64/
H A Dslice.c97 static int slice_low_has_vma(struct mm_struct *mm, unsigned long slice) argument
99 return !slice_area_is_free(mm, slice << SLICE_LOW_SHIFT,
103 static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice) argument
105 unsigned long start = slice << SLICE_HIGH_SHIFT;
191 /* Write the new slice psize bits */
255 * Compute which slice addr is part of;
256 * set *boundary_addr to the start or end boundary of that slice
258 * return boolean indicating if the slice is marked as available in the
265 unsigned long slice; local
267 slice
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H A DMakefile8 obj-y += hash_pgtable.o hash_utils.o hash_tlb.o slb.o slice.o
/linux-master/fs/erofs/
H A Dxattr.c183 unsigned int slice, processed; local
187 for (processed = 0; processed < len; processed += slice) {
194 slice = min_t(unsigned int, sb->s_blocksize -
196 memcpy(it->buffer + it->buffer_ofs, src, slice);
197 it->buffer_ofs += slice;
198 it->pos += slice;
259 unsigned int slice, processed, value_sz; local
293 for (processed = 0; processed < entry.e_name_len; processed += slice) {
299 slice = min_t(unsigned int,
303 it->kaddr + erofs_blkoff(sb, it->pos), slice))
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/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h74 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
79 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
444 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
445 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
505 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) *
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H A Dintel_sseu.c38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) argument
41 if (WARN_ON(slice >= sseu->max_slices))
44 return sseu->subslice_mask.hsw[slice];
47 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, argument
51 WARN_ON(slice > 0);
54 return sseu->eu_mask.hsw[slice][subslice];
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, argument
63 GEM_WARN_ON(slice > 0);
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask;
226 * The concept of slice ha
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H A Dintel_workarounds.c556 * ss_max == 4 (maximum number of subslices possible per slice)
1106 unsigned int slice, subslice; local
1113 * Before any MMIO read into slice/subslice specific registers, MCR
1122 slice = ffs(sseu->slice_mask) - 1;
1123 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
1124 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1132 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1135 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
1234 unsigned int slice, unsigne
1232 __set_mcr_steering(struct i915_wa_list *wal, i915_reg_t steering_reg, unsigned int slice, unsigned int subslice) argument
1253 __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, unsigned int slice, unsigned int subslice) argument
1299 unsigned long slice, subslice = 0, slice_mask = 0; local
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/linux-master/arch/mips/sgi-ip27/
H A Dip27-irq.c256 int slice = LOCAL_HUB_L(PI_CPU_NUM); local
259 resched = CPU_RESCHED_A_IRQ + slice;
263 call = CPU_CALL_A_IRQ + slice;
267 if (slice == 0) {
/linux-master/tools/perf/scripts/python/
H A Dsched-migration.py234 slice = TimeSlice(ts, TimeSlice(-1, None))
236 slice = self.data[-1].next(ts)
237 return slice
282 def update_rectangle_cpu(self, slice, cpu):
283 rq = slice.rqs[cpu]
285 if slice.total_load != 0:
286 load_rate = rq.load() / float(slice.total_load)
295 if cpu in slice.event_cpus:
298 self.root_win.paint_rectangle_zone(cpu, color, top_color, slice.start, slice
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/linux-master/drivers/misc/cxl/
H A Dguest.c216 dev_crit(&afu->dev, "Couldn't ack slice error interrupt: %d\n",
391 pr_devel("Disabling AFU(%d) interrupts\n", ctx->afu->slice);
407 pr_devel("Enabling AFU(%d) interrupts\n", ctx->afu->slice);
739 dev_info(&afu->dev, "Activating AFU(%d) directed mode\n", afu->slice);
780 dev_info(&afu->dev, "Deactivating AFU(%d) directed mode\n", afu->slice);
807 pr_devel("AFU(%d) reset request\n", afu->slice);
815 afu->slice);
838 pr_devel("AFU(%d) update state to %#x\n", afu->slice, cur_state);
875 afu->slice, cur_state);
923 int cxl_guest_init_afu(struct cxl *adapter, int slice, struc argument
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H A Dtrace.h76 __entry->afu = ctx->afu->slice;
105 __entry->afu = ctx->afu->slice;
145 __entry->afu = ctx->afu->slice;
178 __entry->afu = ctx->afu->slice;
212 __entry->afu = ctx->afu->slice;
243 __entry->afu = ctx->afu->slice;
270 __entry->afu = ctx->afu->slice;
299 __entry->afu = ctx->afu->slice;
331 __entry->afu = ctx->afu->slice;
360 __entry->afu = ctx->afu->slice;
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H A Dpci.c636 /* read/write masks for this slice */
638 /* APC read/write masks for this slice */
780 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
781 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
782 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
783 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1128 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) argument
1133 afu = cxl_alloc_afu(adapter, slice);
1143 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1164 adapter->afu[afu->slice]
1553 int slice; local
1732 int slice; local
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H A Dfile.c28 #define CXL_AFU_MINOR_D(afu) (CXL_CARD_MINOR(afu->adapter) + 1 + (3 * afu->slice))
47 int slice = CXL_DEVT_AFU(inode->i_rdev); local
50 pr_devel("afu_open afu%i.%i\n", slice, adapter_num);
55 if (slice > adapter->slices)
59 if (!(afu = adapter->afu[slice])) {
295 afuid.afu_offset = ctx->afu->slice;
580 "afu%i.%i%s", afu->adapter->adapter_num, afu->slice, postfix);
H A Dof.c457 int slice = 0, slice_ok = 0; local
474 if ((ret = cxl_guest_init_afu(adapter, slice, afu_np)))
476 slice, ret);
479 slice++;
H A Ddebugfs.c104 snprintf(buf, 32, "psl%i.%i", afu->adapter->adapter_num, afu->slice);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgm107.c110 const u32 slice = nvkm_rd32(device, 0x17e280) >> 28; local
117 ltc->lts_nr = slice;
H A Dgf100.c213 const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28; local
220 ltc->lts_nr = slice;
/linux-master/fs/efs/
H A Dsuper.c161 int pt_type, slice = -1; local
218 slice = i;
222 if (slice == -1) {
226 pr_info("using slice %d (type %s, offset 0x%x)\n", slice,
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_bw.c1022 enum dbuf_slice slice; local
1024 for_each_dbuf_slice(i915, slice) {
1025 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
1026 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
1046 enum dbuf_slice slice; local
1052 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
1053 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rat
1096 enum dbuf_slice slice; local
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H A Dskl_watermark_regs.h139 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
H A Dintel_display_power.c1059 enum dbuf_slice slice, bool enable)
1061 i915_reg_t reg = DBUF_CTL_S(slice);
1071 "DBuf slice %d power %s timeout!\n",
1072 slice, str_enable_disable(enable));
1080 enum dbuf_slice slice; local
1098 for_each_dbuf_slice(dev_priv, slice)
1099 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1119 * Just power up at least 1 slice, we will
1135 enum dbuf_slice slice; local
1058 gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, enum dbuf_slice slice, bool enable) argument
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/linux-master/drivers/net/ethernet/myricom/myri10ge/
H A Dmyri10ge.c955 * slice 0. It must also be called *after*
1549 /* an interrupt on a non-zero receive-only slice is implicitly
1592 /* Only slice 0 updates stats */
1746 "----------- slice ---------",
1796 int slice; local
1820 /* firmware stats are useful only in the first slice */
1837 for (slice = 0; slice < mgp->num_slices; slice++) {
1838 ss = &mgp->ss[slice];
1943 int i, slice, status; local
2231 myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice) argument
2265 myri10ge_set_stats(struct myri10ge_priv *mgp, int slice) argument
2299 int i, status, big_pow2, slice; local
3346 int slice = ss - mgp->ss; local
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/linux-master/fs/nfs/blocklayout/
H A Ddev.c101 p = xdr_decode_hyper(p, &b->slice.start);
102 p = xdr_decode_hyper(p, &b->slice.len);
103 b->slice.volume = be32_to_cpup(p++);
390 ret = bl_parse_deviceid(server, d, volumes, v->slice.volume, gfp_mask);
394 d->disk_offset = v->slice.start;
395 d->len = v->slice.len;
H A Dblocklayout.h74 } slice; member in union:pnfs_block_volume::__anon1815
/linux-master/arch/mips/include/asm/sn/sn0/
H A Daddrs.h143 #define KERN_NMI_ADDR(nasid, slice) \
145 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
/linux-master/drivers/gpu/drm/i915/
H A Di915_irq.c184 u8 slice = 0; local
200 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
203 slice--;
205 slice >= NUM_L3_SLICES(dev_priv)))
208 dev_priv->l3_parity.which_slice &= ~(1<<slice);
210 reg = GEN7_L3CDERRST1(slice);
224 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
232 slice, row, bank, subbank);

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