1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#ifndef __SKL_WATERMARK_REGS_H__ 7#define __SKL_WATERMARK_REGS_H__ 8 9#include "intel_display_reg_defs.h" 10 11#define _PIPEA_MBUS_DBOX_CTL 0x7003C 12#define _PIPEB_MBUS_DBOX_CTL 0x7103C 13#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 14 _PIPEB_MBUS_DBOX_CTL) 15#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 16#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 17#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 18#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 19#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 20#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 21#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 22#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) 23#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) 24#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 25#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 26#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) 27#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) 28#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 29#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 30 31#define MBUS_UBOX_CTL _MMIO(0x4503C) 32#define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 33#define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 34 35#define MBUS_CTL _MMIO(0x4438C) 36#define MBUS_JOIN REG_BIT(31) 37#define MBUS_HASHING_MODE_MASK REG_BIT(30) 38#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 39#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 40#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 41#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 42#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 43 44/* Watermark register definitions for SKL */ 45#define _CUR_WM_A_0 0x70140 46#define _CUR_WM_B_0 0x71140 47#define _CUR_WM_SAGV_A 0x70158 48#define _CUR_WM_SAGV_B 0x71158 49#define _CUR_WM_SAGV_TRANS_A 0x7015C 50#define _CUR_WM_SAGV_TRANS_B 0x7115C 51#define _CUR_WM_TRANS_A 0x70168 52#define _CUR_WM_TRANS_B 0x71168 53#define _PLANE_WM_1_A_0 0x70240 54#define _PLANE_WM_1_B_0 0x71240 55#define _PLANE_WM_2_A_0 0x70340 56#define _PLANE_WM_2_B_0 0x71340 57#define _PLANE_WM_SAGV_1_A 0x70258 58#define _PLANE_WM_SAGV_1_B 0x71258 59#define _PLANE_WM_SAGV_2_A 0x70358 60#define _PLANE_WM_SAGV_2_B 0x71358 61#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 62#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 63#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 64#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 65#define _PLANE_WM_TRANS_1_A 0x70268 66#define _PLANE_WM_TRANS_1_B 0x71268 67#define _PLANE_WM_TRANS_2_A 0x70368 68#define _PLANE_WM_TRANS_2_B 0x71368 69#define PLANE_WM_EN (1 << 31) 70#define PLANE_WM_IGNORE_LINES (1 << 30) 71#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 72#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 73 74#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 75#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 76#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 77#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 78#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 79#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 80#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 81#define _PLANE_WM_BASE(pipe, plane) \ 82 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 83#define PLANE_WM(pipe, plane, level) \ 84 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 85#define _PLANE_WM_SAGV_1(pipe) \ 86 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 87#define _PLANE_WM_SAGV_2(pipe) \ 88 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 89#define PLANE_WM_SAGV(pipe, plane) \ 90 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 91#define _PLANE_WM_SAGV_TRANS_1(pipe) \ 92 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 93#define _PLANE_WM_SAGV_TRANS_2(pipe) \ 94 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 95#define PLANE_WM_SAGV_TRANS(pipe, plane) \ 96 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 97#define _PLANE_WM_TRANS_1(pipe) \ 98 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 99#define _PLANE_WM_TRANS_2(pipe) \ 100 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 101#define PLANE_WM_TRANS(pipe, plane) \ 102 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 103 104#define _PLANE_BUF_CFG_1_B 0x7127c 105#define _PLANE_BUF_CFG_2_B 0x7137c 106#define _PLANE_BUF_CFG_1(pipe) \ 107 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 108#define _PLANE_BUF_CFG_2(pipe) \ 109 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 110#define PLANE_BUF_CFG(pipe, plane) \ 111 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 112 113#define _PLANE_NV12_BUF_CFG_1_B 0x71278 114#define _PLANE_NV12_BUF_CFG_2_B 0x71378 115#define _PLANE_NV12_BUF_CFG_1(pipe) \ 116 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 117#define _PLANE_NV12_BUF_CFG_2(pipe) \ 118 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 119#define PLANE_NV12_BUF_CFG(pipe, plane) \ 120 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 121 122/* SKL new cursor registers */ 123#define _CUR_BUF_CFG_A 0x7017c 124#define _CUR_BUF_CFG_B 0x7117c 125#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 126 127/* 128 * The below are numbered starting from "S1" on gen11/gen12, but starting 129 * with display 13, the bspec switches to a 0-based numbering scheme 130 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 131 * We'll just use the 0-based numbering here for all platforms since it's the 132 * way things will be named by the hardware team going forward, plus it's more 133 * consistent with how most of the rest of our registers are named. 134 */ 135#define _DBUF_CTL_S0 0x45008 136#define _DBUF_CTL_S1 0x44FE8 137#define _DBUF_CTL_S2 0x44300 138#define _DBUF_CTL_S3 0x44304 139#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 140 _DBUF_CTL_S0, \ 141 _DBUF_CTL_S1, \ 142 _DBUF_CTL_S2, \ 143 _DBUF_CTL_S3)) 144#define DBUF_POWER_REQUEST REG_BIT(31) 145#define DBUF_POWER_STATE REG_BIT(30) 146#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 147#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 148#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 149#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 150 151#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) 152#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) 153#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) 154#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) 155#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) 156 157#define MTL_LATENCY_SAGV _MMIO(0x4578c) 158#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) 159 160#define LNL_PKG_C_LATENCY _MMIO(0x46460) 161#define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16) 162#define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0) 163 164#endif /* __SKL_WATERMARK_REGS_H__ */ 165