Lines Matching refs:slice
38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
41 if (WARN_ON(slice >= sseu->max_slices))
44 return sseu->subslice_mask.hsw[slice];
47 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
51 WARN_ON(slice > 0);
54 return sseu->eu_mask.hsw[slice][subslice];
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
63 GEM_WARN_ON(slice > 0);
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask;
221 * The concept of slice has been removed in Xe_HP. To be compatible
222 * with prior generations, assume a single slice across the entire
224 * that software slice.
270 * DG1, and ADL only had a single slice.
288 /* TGL only supports slice-level power gating */
307 * EHL/JSL only had a single slice in practice.
390 /* BXT has a single slice and at most 3 subslices. */
408 /* skip disabled slice */
454 * SKL+ supports slice power gating on devices with more than
455 * one slice, and supports EU power gating on devices with
520 /* skip disabled slice */
561 * BDW supports slice power gating on devices with more than
562 * one slice.
667 * slice/subslice/EU enablement prior to Gen9.
698 * When more than one slice is enabled, hardware ignores the subslice
705 * slice.
718 * slice/subslice/EU in a partially enabled state. We
785 drm_printf(p, "slice total: %u, mask=%04x\n",
793 drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
800 drm_printf(p, "has slice power gating: %s\n",
816 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",