Searched refs:reg_name (Results 26 - 50 of 290) sorted by relevance

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/linux-master/tools/testing/selftests/kvm/aarch64/
H A Ddebug-exceptions.c40 #define GEN_DEBUG_WRITE_REG(reg_name) \
41 static void write_##reg_name(int num, uint64_t val) \
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce80/
H A Dhw_factory_dce80.c41 #define REG(reg_name)\
42 mm ## reg_name
83 #define SF_DDC(reg_name, field_name, post_fix)\
84 .field_name = reg_name ## __ ## field_name ## post_fix
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
H A Ddce60_clk_mgr.c50 #define FN(reg_name, field_name) \
54 #define SR(reg_name)\
55 .reg_name = mm ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce60/
H A Dhw_factory_dce60.c41 #define REG(reg_name)\
42 mm ## reg_name
83 #define SF_DDC(reg_name, field_name, post_fix)\
84 .field_name = reg_name ## __ ## field_name ## post_fix
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dpp.c36 #define FN(reg_name, field_name) \
H A Ddcn35_dwb.c35 #define FN(reg_name, field_name) \
H A Ddcn35_mmhubbub.c37 #define FN(reg_name, field_name) \
H A Ddcn35_opp.c33 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c251 #define SR(reg_name)\
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
255 #define SRI(reg_name, block, id)\
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_ID
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_hubbub.c37 #define FN(reg_name, field_name) \
47 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c63 #define REG(reg_name) \
64 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
66 #define FN(reg_name, field) \
67 FD(reg_name##__##field)
69 #define REG_NBIO(reg_name) \
70 (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr_vbios_smu.c40 #define REG(reg_name) \
41 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
43 #define FN(reg_name, field) \
44 FD(reg_name##__##field)
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c39 #define REG(reg_name) \
40 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
42 #define FN(reg_name, field) \
43 FD(reg_name##__##field)
/linux-master/tools/lib/bpf/
H A Dusdt.c1237 static int calc_pt_regs_off(const char *reg_name) argument
1273 if (strcmp(reg_name, reg_map[i].names[j]) == 0)
1278 pr_warn("usdt: unrecognized register '%s'\n", reg_name);
1284 char reg_name[16]; local
1288 if (sscanf(arg_str, " %d @ %ld ( %%%15[^)] ) %n", arg_sz, &off, reg_name, &len) == 3) {
1292 reg_off = calc_pt_regs_off(reg_name);
1296 } else if (sscanf(arg_str, " %d @ ( %%%15[^)] ) %n", arg_sz, reg_name, &len) == 2) {
1300 reg_off = calc_pt_regs_off(reg_name);
1304 } else if (sscanf(arg_str, " %d @ %%%15s %n", arg_sz, reg_name, &len) == 2) {
1309 reg_off = calc_pt_regs_off(reg_name);
1369 calc_pt_regs_off(const char *reg_name) argument
1385 char reg_name[16]; local
1428 calc_pt_regs_off(const char *reg_name) argument
1479 char reg_name[16]; local
1514 calc_pt_regs_off(const char *reg_name) argument
1550 char reg_name[16]; local
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c116 #define SR(reg_name)\
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c117 #define SR(reg_name)\
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
120 #define SR_ARR(reg_name, id)\
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
123 #define SR_ARR_INIT(reg_name, id, value)\
124 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c167 #define NBIO_SR(reg_name)\
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
169 mm ## reg_name
176 #define SR(reg_name)\
177 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
179 #define SF(reg_name, field_name, post_fix)\
180 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c163 #define NBIO_SR(reg_name)\
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 mm ## reg_name
172 #define SR(reg_name)\
173 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
175 #define SF(reg_name, field_name, post_fix)\
176 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c131 #define SR(reg_name)\
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
133 reg ## reg_name
135 #define SR_ARR(reg_name, id) \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 #define SR_ARR_INIT(reg_name, id, value) \
139 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c111 #define SR(reg_name)\
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
115 #define SR_ARR(reg_name, id) \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \
119 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c116 #define SR(reg_name)\
117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 mm ## reg_name
120 #define SRI(reg_name, block, id)\
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define SRI2(reg_name, block, id)\
125 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c145 #define SR(reg_name)\
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
149 #define SRI(reg_name, block, id)\
150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
153 #define SRI2(reg_name, block, id)\
154 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_helper.c54 #define FN(reg_name, field_name) \
/linux-master/include/uapi/regulator/
H A Dregulator.h64 char reg_name[32]; member in struct:reg_genl_event

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