1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "dcn35_dsc.h"
28#include "reg_helper.h"
29
30/* Macro definitios for REG_SET macros*/
31#define CTX \
32	dsc20->base.ctx
33
34#define REG(reg)\
35	dsc20->dsc_regs->reg
36
37#undef FN
38#define FN(reg_name, field_name)                                          \
39	((const struct dcn35_dsc_shift *)(dsc20->dsc_shift))->field_name, \
40		((const struct dcn35_dsc_mask *)(dsc20->dsc_mask))->field_name
41
42#define DC_LOGGER \
43	dsc->ctx->logger
44
45void dsc35_construct(struct dcn20_dsc *dsc,
46		struct dc_context *ctx,
47		int inst,
48		const struct dcn20_dsc_registers *dsc_regs,
49		const struct dcn35_dsc_shift *dsc_shift,
50		const struct dcn35_dsc_mask *dsc_mask)
51{
52	dsc2_construct(dsc, ctx, inst, dsc_regs,
53		(const struct dcn20_dsc_shift *)(dsc_shift),
54		(const struct dcn20_dsc_mask *)(dsc_mask));
55}
56
57void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)
58{
59	REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);
60}
61