Searched refs:divider (Results 26 - 50 of 147) sorted by last modified time

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/linux-master/drivers/clk/
H A Dclk-cdce925.c349 /* Disable clock by setting divider to "0" */
366 unsigned long divider; local
373 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
374 if (divider > 0x7F)
375 divider = 0x7F;
377 return (u16)divider;
427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); local
429 if (l_parent_rate / divider != rate) {
431 divider = cdce925_calc_divider(rate, l_parent_rate);
435 if (divider)
462 unsigned long divider; local
480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); local
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H A DMakefile6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
14 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
/linux-master/drivers/mmc/host/
H A Dmxcmmc.c788 unsigned int divider; local
793 for (divider = 1; divider <= 0xF; divider++) {
796 x = (clk_in / (divider + 1));
804 if (divider < 0x10)
813 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
815 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
816 prescaler, divider, clk_in, clk_ios);
/linux-master/drivers/hwmon/
H A Dltc4282.c1350 const char *divider; local
1464 &divider);
1467 ARRAY_SIZE(ltc4282_dividers), divider);
1470 "Invalid val(%s) for adi,overvoltage-divider\n",
1471 divider);
1479 &divider);
1482 ARRAY_SIZE(ltc4282_dividers), divider);
1485 "Invalid val(%s) for adi,undervoltage-divider\n",
1486 divider);
/linux-master/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c565 u32 index, u32 divider)
572 value |= DS_DIV(divider);
577 u32 index, u32 divider)
584 value |= DS_SH_DIV(divider);
1784 u32 divider; local
1787 divider = did * 25;
1789 divider = (did - 64) * 50 + 1600;
1791 divider = (did - 96) * 100 + 3200;
1793 divider = 128 * 100;
1797 return ((pi->sys_info.dentist_vco_freq * 100) + (divider
564 trinity_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
576 trinity_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
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H A Dsumo_dpm.c472 u32 index, u32 divider)
479 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
482 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
485 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
488 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
492 u32 index, u32 divider)
500 dpm_ctrl |= (divider << (index * 3));
506 u32 index, u32 divider)
514 dpm_ctrl |= (divider << (index * 3));
471 sumo_set_divider_value(struct radeon_device *rdev, u32 index, u32 divider) argument
491 sumo_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
505 sumo_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
H A Dr600_dpm.c477 u32 index, u32 divider)
480 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
484 u32 index, u32 divider)
487 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
491 u32 index, u32 divider)
494 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
476 r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
483 r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
490 r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
H A Dr600_dpm.h180 u32 index, u32 divider);
182 u32 index, u32 divider);
184 u32 index, u32 divider);
/linux-master/drivers/soc/qcom/
H A Dqcom-geni-se.c626 unsigned int divider; local
637 divider = DIV_ROUND_UP(tbl[i], req_freq);
638 new_delta = req_freq - tbl[i] / divider;
/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_ring.c115 fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
H A Dinv_mpu_core.c111 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
128 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
538 d = st->chip_config.divider;
556 NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
604 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
955 /* compute the chip sample rate divider */
962 if (d == st->chip_config.divider) {
981 st->chip_config.divider = d;
1014 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
H A Dinv_mpu_iio.h111 * @divider: chip sample rate divider (sample rate divider - 1)
126 u8 divider; member in struct:inv_mpu6050_chip_config
378 /* return the frequency divider (chip sample rate divider + 1) */
380 ((st)->chip_config.divider + 1)
381 /* chip sample rate divider to fifo rate */
384 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
385 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider)
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H A Dinv_mpu_aux.c49 d = st->chip_config.divider;
59 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider);
/linux-master/arch/sh/boards/mach-ecovec24/
H A Dsetup.c514 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
519 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
/linux-master/drivers/mfd/
H A Dsm501.c392 int divider; member in struct:sm501_clock
411 int divider; local
416 try divider 5 for panel only.*/
418 for (divider = 1; divider <= max_div; divider += 2) {
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
431 clock->divider = divider;
476 return clock->mclk / (clock->divider << cloc
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/linux-master/arch/mips/include/asm/sgi/
H A Dmc.h57 volatile u32 divider; /* Divider reg for RPSS */ member in struct:sgimc_regs
/linux-master/drivers/media/i2c/
H A Dmt9t112.c409 priv->info->divider.m, priv->info->divider.n,
410 priv->info->divider.p1, priv->info->divider.p2,
411 priv->info->divider.p3, priv->info->divider.p4,
412 priv->info->divider.p5, priv->info->divider.p6,
413 priv->info->divider.p7);
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c114 u64 divider; local
121 divider = fref * 2;
124 dec_multiple = div_u64(pll_freq * multiplier, divider);
619 * The post dividers and mux clocks are created using the standard divider and
621 * state to follow the master PLL's divider/mux state. Therefore, we don't
/linux-master/drivers/clk/zynqmp/
H A Ddivider.c7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
84 u32 clk_id = divider->clk_id;
85 u32 div_type = divider->div_type;
92 pr_debug("%s() get divider faile
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
172 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
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/linux-master/drivers/clk/stm32/
H A Dclk-stm32-core.c213 const struct stm32_div_cfg *divider = &data->dividers[div_id]; local
217 val = readl(base + divider->offset) >> divider->shift;
218 val &= clk_div_mask(divider->width);
219 div = _get_div(divider->table, val, divider->flags, divider->width);
222 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
236 const struct stm32_div_cfg *divider = &data->dividers[div_id]; local
240 value = divider_get_val(rate, parent_rate, divider
359 const struct stm32_div_cfg *divider; local
436 const struct stm32_div_cfg *divider; local
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/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c118 struct clk_divider divider; member in struct:mpfs_ccc_out_hw_clock
126 .divider.shift = _shift, \
127 .divider.width = _width, \
129 .divider.flags = _flags, \
130 .divider.lock = &mpfs_ccc_lock, \
172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
176 ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
181 data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
/linux-master/drivers/spi/
H A Dspi-xcomm.c79 unsigned int divider; local
81 divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
82 if (divider >= 64)
84 else if (divider >= 16)
/linux-master/sound/soc/ti/
H A Domap-mcbsp.c944 int divider = 0; local
958 divider = period_words / max_thrsh;
960 divider++;
961 while (period_words % divider &&
962 divider < period_words)
963 divider++;
964 if (divider == period_words)
967 pkt_size = period_words / divider;
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c29 unsigned int divider)
31 int i = fls(divider) - fls(counter);
36 if (divider >> i < counter)
28 imgu_css_scaler_get_exp(unsigned int counter, unsigned int divider) argument
/linux-master/drivers/iio/adc/
H A Dstm32-dfsdm-core.c96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
227 unsigned long clk_freq, divider; local
269 divider = div_u64_rem(clk_freq, spi_freq, &rem);
270 /* Round up divider when ckout isn't precise, not to exceed spi_freq */
272 divider++;
274 /* programmable divider is in range of [2:256] */
275 if (divider < 2 || divider > 256) {
280 /* SPI clock output divider is: divider
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