clk/stm32/clk-stm32-core.c

213 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
217 	val =  readl(base + divider->offset) >> divider->shift;
218 	val &= clk_div_mask(divider->width);
219 	div = _get_div(divider->table, val, divider->flags, divider->width);
222 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
236 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
240 	value = divider_get_val(rate, parent_rate, divider->table,
241 				divider->width, divider->flags);
245 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
246 		val = clk_div_mask(divider->width) << (divider->shift + 16);
248 		val = readl(base + divider->offset);
249 		val &= ~(clk_div_mask(divider->width) << divider->shift);
252 	val |= (u32)value << divider->shift;
254 	writel(val, base + divider->offset);
359 	const struct stm32_div_cfg *divider;
364 	divider = &div->clock_data->dividers[div->div_id];
367 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
370 		val =  readl(div->base + divider->offset) >> divider->shift;
371 		val &= clk_div_mask(divider->width);
373 		return divider_ro_round_rate(hw, rate, prate, divider->table,
374 				divider->width, divider->flags,
379 					 rate, prate, divider->table,
380 					 divider->width, divider->flags);
436 	const struct stm32_div_cfg *divider;
442 	divider = &composite->clock_data->dividers[composite->div_id];
445 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
448 		val =  readl(composite->base + divider->offset) >> divider->shift;
449 		val &= clk_div_mask(divider->width);
452 					     divider->table, divider->width, divider->flags,
463 					 divider->table, divider->width, divider->flags);