/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 725 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local 1295 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local 3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; local [all...] |
H A D | SelectionDAGBuilder.cpp | 774 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt, Optional<CallingConv::ID> CC) argument 779 RegsForValue(LLVMContext &Context, const TargetLowering &TLI, const DataLayout &DL, unsigned Reg, Type *Ty, Optional<CallingConv::ID> CC) argument 1884 CallingConv::ID CC = F->getCallingConv(); local 8810 CallingConv::ID CC = CS.getCallingConv(); local 10301 ISD::CondCode CC; local 10336 caseClusterRank(const CaseCluster &CC, CaseClusterIt First, CaseClusterIt Last) argument 10393 CaseCluster &CC = *FirstRight; local 10514 CaseCluster &CC = Clusters[Index]; local [all...] |
H A D | DAGCombiner.cpp | 2030 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); local 7067 SDValue LHS, RHS, CC; local 8319 combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) argument 8384 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); local 8640 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local 8895 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local 8995 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); local 9185 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); local 9585 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); local 9744 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local 12499 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); local 13655 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); local 20053 ISD::CondCode CC; local 20234 foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC) argument 20309 convertSelectOfFPConstantsToLoadOffset( const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC) argument 20364 SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 833 struct CCOp CC; member in union:__anon2168::ARMOperand::__anon2171 3390 CreateCondCode(ARMCC::CondCodes CC, SMLoc S) argument 3399 CreateVPTPred(ARMVCC::VPTCodes CC, SMLoc S) argument 4153 unsigned CC = ARMCondCodeFromString(Tok.getString()); local 6263 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2)); local 6311 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1)); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 5963 int CC; local 6041 int CC; local 6106 int CC; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 795 getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument 818 getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument 843 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument 2580 canGuaranteeTCO(CallingConv::ID CC) argument 2585 mayTailCallThisCC(CallingConv::ID CC) argument 9827 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaDeclAttr.cpp | 4510 bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, argument [all...] |
H A D | SemaChecking.cpp | 5636 CallingConv CC = CC_C; local 11396 CheckImplicitArgumentConversions(Sema &S, CallExpr *TheCall, SourceLocation CC) argument 11417 DiagnoseNullConversion(Sema &S, Expr *E, QualType T, SourceLocation CC) argument 11562 isSameWidthConstantConversion(Sema &S, Expr *E, QualType T, SourceLocation CC) argument 11635 CheckImplicitConversion(Sema &S, Expr *E, QualType T, SourceLocation CC, bool *ICContext = nullptr, bool IsListInit = false) argument 12070 CheckConditionalOperand(Sema &S, Expr *E, QualType T, SourceLocation CC, bool &ICContext) argument 12082 CheckConditionalOperator(Sema &S, ConditionalOperator *E, SourceLocation CC, QualType T) argument 12115 CheckBoolLikeConversion(Sema &S, Expr *E, SourceLocation CC) argument 12126 AnalyzeImplicitConversions(Sema &S, Expr *OrigE, SourceLocation CC, bool IsListInit ) argument 12505 CheckImplicitConversions(Expr *E, SourceLocation CC) argument 12525 CheckBoolLikeConversion(Expr *E, SourceLocation CC) argument [all...] |
H A D | SemaDecl.cpp | 9213 CallingConv CC = FT->getExtInfo().getCC(); local
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H A D | SemaExpr.cpp | 15443 CallingConv CC = FD->getType()->castAs<FunctionType>()->getCallConv(); local
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/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Sema/ |
H A D | Sema.h | 4119 FullExprArg MakeFullExpr(Expr *Arg, SourceLocation CC) { argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1520 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { argument 1548 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument 1611 static void changeFPCCToANDAArch64CC(ISD::CondCode CC, argument 1641 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument 1690 isCMN(SDValue Op, ISD::CondCode CC) argument 1706 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument 1804 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument 1922 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get(); local 2074 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) argument 2206 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument 2362 AArch64CC::CondCode CC; local 2465 AArch64CC::CondCode CC; local 3290 CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const argument 3738 canGuaranteeTCO(CallingConv::ID CC) argument 3743 mayTailCallThisCC(CallingConv::ID CC) argument 4948 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local 5226 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get(); local 5301 LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, SDValue TVal, SDValue FVal, const SDLoc &dl, SelectionDAG &DAG) const argument 5491 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local 5524 ISD::CondCode CC; local 8376 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) argument 8473 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local 10537 ISD::CondCode CC; member in struct:GenericSetCCInfo 10543 AArch64CC::CondCode CC; member in struct:AArch64SetCCInfo 10987 SDValue CC = DAG.getConstant(getInvertedCondCode(Cond), DL, MVT::i32); local 11866 isEquivalentMaskless(unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant) argument 11946 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue(); local 12034 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue(); local 13281 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 3038 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local 3145 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, local 12337 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local 12386 ISD::CondCode CC = local 12928 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local 14339 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 523 const CallingConv::ID CC; member in struct:__anon3 620 const CallingConv::ID CC; member in struct:__anon4 643 const CallingConv::ID CC; member in struct:__anon5 690 const CallingConv::ID CC; member in struct:__anon6 1148 const CallingConv::ID CC; member in struct:__anon7 1169 const CallingConv::ID CC; member in struct:__anon8 1833 IntCCToARMCC(ISD::CondCode CC) argument 1850 FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2) argument 1886 getEffectiveCallingConv(CallingConv::ID CC, bool isVarArg) const argument 1924 CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const argument 1929 CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const argument 1936 CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const argument 4216 getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const argument 4648 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument 4724 isGTorGE(ISD::CondCode CC) argument 4728 isLTorLE(ISD::CondCode CC) argument 4738 isLowerSaturate(const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K) argument 4748 isUpperSaturate(const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K) argument 4878 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local 4956 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local 5162 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local 5249 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local 6221 SDValue CC = Op.getOperand(2); local 8920 CallingConv::ID CC = getLibcallCallingConv(LC); local 9250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get(); local 10980 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument 12412 isValidMVECond(unsigned CC, bool IsFloat) argument 14162 auto CC = CCNode->getAPIntValue().getLimitedValue(); local 14241 SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate) argument 14293 ISD::CondCode CC; local 14415 ARMCC::CondCodes CC = local 14455 ARMCC::CondCodes CC = local [all...] |